CN109300840B - Display substrate, manufacturing method thereof and display device - Google Patents

Display substrate, manufacturing method thereof and display device Download PDF

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CN109300840B
CN109300840B CN201811159425.1A CN201811159425A CN109300840B CN 109300840 B CN109300840 B CN 109300840B CN 201811159425 A CN201811159425 A CN 201811159425A CN 109300840 B CN109300840 B CN 109300840B
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layer
interlayer dielectric
substrate
dielectric layer
electrode
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CN109300840A (en
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周天民
王利忠
杨维
黄睿
卢鑫泓
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

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Abstract

The application discloses a display substrate, a manufacturing method thereof and a display device, and belongs to the technical field of display. The method comprises the following steps: sequentially forming a first active layer, a first gate insulating layer, a first gate and a first interlayer dielectric layer on a substrate; sequentially forming an active layer material layer, a second gate insulating layer, a second gate and an interlayer dielectric material layer on the substrate with the first interlayer dielectric layer; and processing the active layer material layer and the interlayer dielectric layer by a one-time composition process to obtain a second active layer and a second interlayer dielectric layer. The manufacturing method and the manufacturing device solve the problems that the manufacturing process of the display substrate is complex and the manufacturing cost is high, simplify the manufacturing process of the display substrate and reduce the manufacturing cost of the display substrate. The application is for the manufacture of LTPO substrates.

Description

Display substrate, manufacturing method thereof and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
Background
The Low Temperature Polysilicon Oxide (LTPO) substrate is a novel display substrate, has the advantages of a Low Temperature Polysilicon (LTPS) substrate and an Oxide (Oxide) substrate, and is a main development direction of future display substrates. The LTPS substrate refers to a display substrate in which a Thin Film Transistor (TFT) in a display unit is an LTPS TFT, the oxide substrate refers to a display substrate in which a TFT in a display unit is an oxide TFT, each display unit in the LTPO substrate refers to a display substrate in which an LTPS TFT and an oxide TFT are included, and the display unit is also referred to as a subpixel.
In the related art, the LTPO substrate includes a substrate, and a polyimide layer, a barrier layer, a first buffer layer, a polysilicon active layer, a first gate insulating layer, a first gate electrode, a first interlayer dielectric layer, a second buffer layer, an oxide active layer, a second gate insulating layer, a second gate electrode, a second interlayer dielectric layer, a source/drain connection line, a first source/drain electrode layer, a passivation layer, a first planarization layer, a second source/drain electrode layer, a second planarization layer, an anode, a pixel defining layer, and a spacer layer disposed on the substrate. In the process of manufacturing the LTPO substrate, 14 film layers, namely, a polysilicon active layer, a first gate electrode, a first interlayer dielectric layer, an oxide active layer, a second gate electrode, a second interlayer dielectric layer, a source-drain connection line, a first source-drain layer, a passivation layer, a first planarization layer, a second source-drain layer, a second planarization layer, an anode, and a pixel definition layer, are manufactured through one-time composition process.
In the course of implementing the present application, the inventors found that the related art has at least the following problems:
because 14 film layers, namely the polysilicon active layer, the first grid electrode, the first interlayer dielectric layer, the oxide active layer, the second grid electrode, the second interlayer dielectric layer, the source and drain connecting line, the first source and drain electrode layer, the passivation layer, the first flat layer, the second source and drain electrode layer, the second flat layer, the anode and the pixel defining layer, need to be processed by one-time composition process, the manufacturing process of the LTPO substrate at least needs 14 composition processes, the manufacturing process of the LTPO substrate is complex, and the manufacturing cost is high.
Disclosure of Invention
The application provides a display substrate, a manufacturing method thereof and a display device, which can simplify the manufacturing process of the display substrate and reduce the manufacturing cost. The technical scheme of the application is as follows:
in a first aspect, a method for manufacturing a display substrate is provided, the method including:
sequentially forming a first active layer, a first gate insulating layer, a first gate and a first interlayer dielectric layer on a substrate;
sequentially forming an active layer material layer, a second gate insulating layer, a second gate and an interlayer dielectric material layer on the substrate with the first interlayer dielectric layer;
and processing the active layer material layer and the interlayer dielectric layer by a one-time composition process to obtain a second active layer and a second interlayer dielectric layer.
Optionally, the shape of the second gate insulating layer is the same as that of the second gate electrode, the second active layer, the second gate insulating layer and the second gate electrode are sequentially stacked, the second interlayer dielectric layer covers a part of the upper surfaces of the second gate insulating layer, the second gate electrode and the second active layer, and an area of the upper surface of the second active layer, which is not covered by the second interlayer dielectric layer, is a step surface of a step structure overlapping with the first source electrode and the first drain electrode to be formed.
Optionally, the processing the active layer material layer and the interlayer dielectric layer by a one-step composition process to obtain a second active layer and a second interlayer dielectric layer includes:
forming a photoresist layer on the interlayer dielectric material layer;
sequentially carrying out exposure, development and etching on the substrate base plate with the photoresist layer to obtain an initial interlayer dielectric layer and a photoresist pattern which are sequentially superposed, wherein the shape of the initial interlayer dielectric layer is the same as that of the photoresist pattern;
etching the area, which is not covered by the initial interlayer dielectric layer, on the active layer material layer to obtain a second active layer;
ashing the photoresist pattern to expose a region to be etched of the initial interlayer dielectric layer;
etching the area to be etched of the initial interlayer dielectric layer to obtain a second interlayer dielectric layer, and exposing the step surface of the step structure, which is used for being lapped with the first source electrode and the first drain electrode to be formed, on the second active layer;
and stripping the residual photoresist.
Optionally, after the active layer material layer and the interlayer dielectric material layer are processed by a one-step composition process to obtain a second active layer and a second interlayer dielectric layer, the method further includes:
respectively forming a plurality of first via holes on the first interlayer dielectric layer and the first gate insulating layer by a one-time composition process, wherein the plurality of first via holes on the first interlayer dielectric layer are communicated with the plurality of first via holes on the first gate insulating layer in a one-to-one correspondence manner;
sequentially forming a first source drain electrode layer, a passivation layer, a first flat layer, a second source drain electrode layer and a second flat layer on the substrate with the second interlayer dielectric layer;
wherein, the display substrate is provided with a plurality of display units, in each display unit, the first source drain layer comprises two first source electrodes and one first drain electrode, the second source drain layer comprises a second source electrode and a second drain electrode, one end of one first source electrode and one end of the first drain electrode in the two first source electrodes are respectively lapped on the step structure of the second active layer, the other end of the other first source electrode and the other end of the first drain electrode in the two first source electrodes are respectively connected with the first active layer through a group of first through holes, each group of first through holes comprises two first through holes communicated with the second buffer layer and the first interlayer dielectric layer, a plurality of second through holes are respectively formed on the passivation layer and the first flat layer, and the plurality of second through holes on the passivation layer are communicated with the plurality of second through holes on the first flat layer in a one-to-one correspondence manner, the second source electrode is connected with the other first source electrode through a group of second through holes, the second drain electrode is connected with the first drain electrode through a group of second through holes, and each group of second through holes comprises two second through holes communicated with the first flat layer and the passivation layer.
Optionally, after sequentially forming a first source/drain electrode layer, a passivation layer, a first planarization layer, a second source/drain electrode layer, and a second planarization layer on the substrate base plate on which the second interlayer dielectric layer is formed, the method further includes:
and sequentially forming an anode, a pixel defining layer and a spacer layer on the substrate base plate on which the second flat layer is formed, wherein a third through hole is formed on the second flat layer, and the anode is connected with the second drain electrode through the third through hole.
Optionally, before the first active layer, the first gate insulating layer, the first gate electrode, and the first interlayer dielectric layer are sequentially formed on the substrate, the method further includes:
sequentially forming a flexible base layer, a barrier layer and a first buffer layer on a substrate;
a first active layer, a first gate insulating layer, a first gate electrode and a first interlayer dielectric layer are sequentially formed on the substrate base plate, and the method comprises the following steps:
and sequentially forming a first active layer, a first gate insulating layer, a first gate electrode and a first interlayer dielectric layer on the substrate on which the first buffer layer is formed.
Optionally, before an active layer material layer, a second gate insulating layer, a second gate electrode, and an interlayer dielectric material layer are sequentially formed on the substrate with the first interlayer dielectric layer formed thereon, the method further includes:
forming a second buffer layer on the substrate with the first interlayer dielectric layer;
the substrate base plate on which the first interlayer dielectric layer is formed is sequentially provided with an active layer material layer, a second gate insulating layer, a second gate and an interlayer dielectric layer, and the method comprises the following steps:
sequentially forming an active layer material layer, a second gate insulating layer, a second gate and an interlayer dielectric material layer on the substrate with the second buffer layer;
forming a plurality of first via holes on the first interlayer dielectric layer and the first gate insulating layer respectively through a one-time composition process, wherein the plurality of first via holes on the first interlayer dielectric layer are communicated with the plurality of first via holes on the first gate insulating layer in a one-to-one correspondence manner, and the method comprises the following steps:
forming a plurality of first via holes on the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer respectively through a one-time composition process, wherein the plurality of first via holes on the second buffer layer, the plurality of first via holes on the first interlayer dielectric layer and the plurality of first via holes on the first gate insulating layer are communicated in a one-to-one correspondence manner;
the other end of the other first source electrode and the other end of the other first drain electrode are respectively connected with the first active layer through a group of first via holes, and each group of first via holes comprise three first via holes communicated with the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer.
Optionally, the first active layer is a polysilicon active layer, the second active layer is an oxide active layer, and the method further includes:
and forming a light shielding layer on the substrate with the first gate insulating layer, wherein the light shielding layer and the first gate are arranged on the same layer and are formed by the same composition process, and the orthographic projection of the second active layer on the substrate is positioned in the orthographic projection area of the light shielding layer on the substrate.
In a second aspect, a display substrate is provided, the display substrate comprising: the structure comprises a substrate and a first active layer, a first gate insulating layer, a first grid electrode, a first interlayer dielectric layer, a second active layer, a second gate insulating layer, a second grid electrode and a second interlayer dielectric layer which are arranged on the substrate, wherein the shape of the second gate insulating layer is the same as that of the second grid electrode, the second active layer, the second gate insulating layer and the second grid electrode are sequentially overlapped, the second interlayer dielectric layer covers partial areas of the upper surfaces of the second gate insulating layer, the second grid electrode and the second active layer, and the area, which is not covered by the second interlayer dielectric layer, of the upper surface of the second active layer is a step surface of a step structure overlapped with a first source electrode and a first drain electrode to be formed.
In a third aspect, a display device is provided, which comprises the display substrate of the second aspect
The beneficial effect that technical scheme that this application provided brought is:
according to the display substrate, the manufacturing method of the display substrate and the display device, the second active layer and the second interlayer dielectric layer are formed through the same composition process, so that compared with the related art, the manufacturing process of the display substrate can be reduced by one composition process, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced. Furthermore, the second interlayer dielectric layer covers the second gate insulating layer, the second gate electrode and partial area of the upper surface of the second active layer, so that the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology is larger, the area of the second interlayer dielectric layer in the application is smaller, the second interlayer dielectric layer in the application is obtained by patterning the second interlayer dielectric layer in the related technology, the second interlayer dielectric layer in the application is obtained by releasing the stress of the second interlayer dielectric layer in the related technology, so that the stress of the second interlayer dielectric layer in the application is smaller, the stress of the second interlayer dielectric layer is easier to control, the display substrate is prevented from being warped, the display substrate can be better applied to products such as flexible and foldable products, and the yield of the display substrate is higher. In addition, the second interlayer dielectric layer in the application is obtained by patterning the second interlayer dielectric layer in the related art, and compared with the related art, the film structure of the display substrate can be simplified.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an LTPO substrate provided in the related art;
fig. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another display substrate provided in this embodiment of the present application;
FIG. 4 is a flowchart of a method of fabricating a display substrate according to an embodiment of the present disclosure;
fig. 5 is a flowchart of another method for manufacturing a display substrate according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram illustrating a flexible base layer, a barrier layer, and a first buffer layer sequentially formed on a substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic view illustrating a first active layer and a first gate insulating layer sequentially formed on a substrate having a first buffer layer formed thereon according to an embodiment of the present disclosure;
fig. 8 is a schematic view illustrating a substrate with a first gate insulating layer formed thereon after a first gate electrode and a light-shielding layer are formed thereon according to an embodiment of the present disclosure;
fig. 9 is a schematic view illustrating a first interlayer dielectric layer and a second buffer layer sequentially formed on a substrate having a first gate electrode and a light-shielding layer formed thereon according to an embodiment of the present disclosure;
fig. 10 is a schematic view illustrating an active layer material layer, a second gate insulating layer, a second gate electrode, and an interlayer dielectric material layer sequentially formed on a substrate having a second buffer layer formed thereon according to an embodiment of the present disclosure;
fig. 11 is a flowchart of a method for processing an active layer material layer and an interlayer dielectric material layer by a single patterning process according to an embodiment of the present disclosure;
FIG. 12 is a schematic view of a photoresist layer formed on an interlayer dielectric layer according to an embodiment of the present disclosure;
FIG. 13 is a schematic view of a substrate with a photoresist layer formed thereon after sequentially exposing, developing and etching according to an embodiment of the present disclosure;
fig. 14 is a schematic diagram illustrating an active layer material layer after etching according to an embodiment of the present disclosure;
FIG. 15 is a schematic diagram illustrating a photoresist pattern after ashing in accordance with an embodiment of the present disclosure;
FIG. 16 is a schematic diagram illustrating an etched region of an initial interlayer dielectric layer according to an embodiment of the present disclosure;
FIG. 17 is a schematic view of the present application after stripping the remaining photoresist;
fig. 18 is a schematic view illustrating a plurality of first via holes respectively formed on the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer according to an embodiment of the present disclosure;
fig. 19 is a schematic diagram illustrating a first source/drain electrode layer, a passivation layer, a first planarization layer, a second source/drain electrode layer, and a second planarization layer sequentially formed on a substrate base plate on which a second interlayer dielectric layer is formed according to an embodiment of the present disclosure.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The display substrate is a main component of a display device, and includes a base substrate and a display unit disposed on the base substrate, the display unit including a TFT. The LTPS substrate refers to a display substrate in which TFTs in the display unit are LTPS TFTs, and the oxide substrate refers to a display substrate in which TFTs in the display unit are oxide TFTs. The mobility of the polysilicon active layer is high, so that the leakage current (English: Ioff) of the LTPS TFT is high, the power consumption of the LTPS substrate under low-frequency driving is high, a static black picture is difficult to well maintain, and the picture quality is poor; moreover, in order to better develop gray scale, the channel of a Driving Thin Film Transistor (DTFT) needs to be made very long in the LTPS substrate, so that it is difficult to realize high resolution of the LTPS substrate, which means the number of Pixels Per Inch (PPI); in addition, the poly active layer has a large Hysteresis (english: hystersis), so the LTPS substrate is prone to the problem of image sticking. The mobility of the oxide active layer is low, so that the leakage current of the oxide TFT is low, the power consumption of the oxide substrate under low-frequency driving is low, a static black picture can be well kept, and the picture quality is improved; in addition, in the oxide substrate, the gray scale can be better expanded without making the channel of the DTFT very long, and high PPI is realized; in addition, the hysteresis of the oxide active layer is small, and the problem of image retention of the oxide substrate is not easy to occur; further, the uniformity of the oxide TFT is better than that of the LTPS TFT.
From the above description, it can be seen that the oxide process can well compensate for some of the deficiencies of the LTPS process. However, the LTPS process and the oxide process have respective advantages and disadvantages, and thus, the LTPS process and the oxide process are very competitive process schemes, and the process combining the LTPS process and the oxide process is the LTPO process, which is likely to be applied to the development of high-end products in the future. However, the LTPS process is different from the oxide process, and the compatibility of the processes is difficult, so that the stability of the LTPO process is difficult to ensure.
The LTPO process-based display substrate is an LTPO substrate in which each display cell includes an LTPS TFT and an oxide TFT. Referring to fig. 1, a schematic structural diagram of an LTPO substrate provided in the related art is shown, referring to fig. 1, the LTPO substrate includes a substrate 101, and a Polyimide (PI) layer 102, a Barrier (Barrier) layer 103, a first Buffer (Buffer) layer 104, a polysilicon (P-Si) active layer 105, a first Gate Insulator (GI) layer 106, a first Gate 107, a first interlayer Dielectric (ILD) layer 108, a second Buffer layer 109, a Source/Drain zinc oxide (indium gallium zinc oxide (SD) active layer 110, a second GI layer 111, a second Gate 112, a second ILD layer 113, a Source/Drain connection line 114, a first Drain layer 115, a Source SD layer 110, a second GI layer 111, a second Gate 112, a second ILD layer 113, a Source/Drain connection line 114, and a first Buffer layer 115, A Passivation (PVX) Layer 116, a first Planarization (PLN) Layer 117, a second source/drain Layer 118, a second PLN Layer 119, an Anode (AND) 120, a Pixel Definition Layer (PDL) 121, AND a Spacer (PS) Layer 122. The drain connection line 114 includes a source connection line 1141 and a drain connection line 1142, the first source-drain layer 115 includes a first source 1151 and a first drain 1152, and the second source-drain layer 118 includes a second source 1181 and a second drain 1182.
The LTPO substrate shown in fig. 1 requires at least 14 patterning processes, and thus the LTPO substrate has a complicated manufacturing process and a high manufacturing cost. In addition, the LTPO substrate has a complicated film structure, the area of the second ILD layer 113 is large, and the thickness of the second ILD layer 113 is large, so that the stress of the second ILD layer 113 is large, the stress of the second ILD layer 113 is difficult to control, the LTPO substrate is easy to warp, and the requirements of products such as flexible and foldable products are difficult to meet. In addition, the warpage of the LTPO substrate may cause the substrate (usually made of glass) of the LTPO substrate to be broken during the transportation of the LTPO substrate, which may affect the yield of the LTPO substrate.
According to the display substrate, the manufacturing method thereof and the display device, the display substrate can be an LTPO (low temperature poly oxide) substrate, and in the manufacturing process of the display substrate, a second active layer (such as an IGZO active layer) and a second interlayer dielectric layer are formed through the same composition process, so that the number of composition processes required in the manufacturing process of the display substrate can be reduced, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced; in addition, in the display substrate, the area of the second interlayer dielectric layer is smaller, so that the stress of the second interlayer dielectric layer is smaller, the stress of the second interlayer dielectric layer is easier to control, the warping of the display substrate is improved, the display substrate can meet the requirements of products such as flexible and foldable products, and the yield of the display substrate is improved. For details of the present application, reference is made to the following examples.
Referring to fig. 2, a schematic structural diagram of a display substrate according to an embodiment of the present disclosure is shown, where the display substrate may be an LTPO substrate, and referring to fig. 2, the display substrate includes:
the semiconductor device comprises a substrate base plate 201, and a first active layer 202, a first gate insulating layer 203, a first gate electrode 204, a first interlayer dielectric layer 205, a second active layer 206, a second gate insulating layer 207, a second gate electrode 208 and a second interlayer dielectric layer 209 which are arranged on the substrate base plate 201.
The shape of the second gate insulating layer 207 is the same as that of the second gate electrode 208, the second active layer 206, the second gate insulating layer 207 and the second gate electrode 208 are sequentially overlapped, the second interlayer dielectric layer 209 covers partial areas of the upper surfaces of the second gate insulating layer 207, the second gate electrode 208 and the second active layer 206, and an area, which is not covered by the second interlayer dielectric layer 209, of the upper surface of the second active layer 206 is a step surface of a step structure for overlapping with the first source electrode and the first drain electrode to be formed.
The upper surface of the second active layer 206 is a surface of the second active layer 206 away from the substrate 201, and the second active layer 206 and the second interlayer dielectric layer 209 are formed by the same patterning process.
In summary, according to the display substrate provided in the embodiment of the present application, since the second active layer and the second interlayer dielectric layer are formed by the same patterning process, compared with the related art, the manufacturing process of the display substrate can reduce one patterning process, thereby simplifying the manufacturing process of the display substrate and reducing the manufacturing cost.
Further, the second interlayer dielectric layer covers the second gate insulating layer, the second gate electrode and a partial region of the upper surface of the second active layer, so that the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology is larger, the area of the second interlayer dielectric layer in the embodiment of the application is smaller, the second interlayer dielectric layer in the embodiment of the application is obtained by patterning the second interlayer dielectric layer in the related technology, and the stress of the second interlayer dielectric layer in the embodiment of the application is released, so that the stress of the second interlayer dielectric layer in the embodiment of the application is smaller, the stress of the second interlayer dielectric layer is easier to control, the display substrate is prevented from being warped, the display substrate can be better applied to products such as flexible and foldable products, and the yield of the display substrate is higher. In addition, the second interlayer dielectric layer in the embodiment of the present application is obtained by patterning the second interlayer dielectric layer in the related art, and compared with the related art, the embodiment of the present application can simplify the film structure of the display substrate.
Further, please refer to fig. 3, which shows a schematic structural diagram of another display substrate provided in the embodiment of the present application, and on the basis of fig. 2, the display substrate further includes: a flexible base layer 210, a barrier layer 211, and a first buffer layer 212 disposed on the substrate base plate 201, a Light Shielding (LS) layer 213 disposed on the first gate insulating layer 203, a second buffer layer 214 disposed between the first interlayer dielectric layer 205 and the second active layer 206, and a first source drain layer 215, a passivation layer 216, a first flat layer 217, a second source drain layer 218, and a second flat layer 219 sequentially disposed on the substrate base plate 201 on which the second interlayer dielectric layer 205 is formed. The first active layer 202 is disposed on the first buffer layer 212, the light shielding layer 213 is disposed on the same layer as the first gate electrode 204, the light shielding layer 213 and the first gate electrode 204 can be formed by the same patterning process, and an orthographic projection of the second active layer 206 on the substrate 201 is located in an orthographic projection area of the light shielding layer 213 on the substrate 201. In the embodiment of the present invention, the second active layer 206 may be an oxide active layer, and since the mobility of the oxide active layer is affected by light irradiation, the switching characteristic of the TFT is affected, in the embodiment of the present invention, the orthographic projection of the second active layer 206 on the substrate 201 is located in the orthographic projection area of the light shielding layer 213 on the substrate 201, so that the light shielding layer 213 can shield the second active layer 206, and the influence of light irradiation on the second active layer 206 is avoided, thereby avoiding the influence of light irradiation on the switching characteristic of the TFT.
In the embodiment of the present application, the display substrate has a plurality of display units (only one is shown in fig. 3), in each of the display units, the first source-drain layer 215 includes two first source electrodes 2151 and one first drain electrode 2152, the second source-drain layer 218 includes a second source electrode 2181, a second drain electrode 2182, and a source-drain lead 2183, and the source-drain lead 2183 is used for leading the second source electrode 2181 out of the display substrate to apply a data voltage to the display substrate. A plurality of first via holes (not labeled in fig. 3) are respectively formed on the second buffer layer 214, the first interlayer dielectric layer 205 and the first gate insulating layer 203, the plurality of first via holes on the second buffer layer 214, the plurality of first via holes on the first interlayer dielectric layer 205 and the plurality of first via holes on the first gate insulating layer 203 are in one-to-one correspondence, one end of one first source 2151 and one end of one first drain 2152 of the two first sources 2151 are respectively lapped on the step surface of the step structure of the second active layer 206, the other end of the other first source 2151 and the other end of the first drain 2152 of the two first sources 2151 are respectively connected with the first active layer 202 through a group of first via holes, each group of first via holes includes three first via holes communicated with each other on the first gate insulating layer 203, the first interlayer dielectric layer 205 and the second buffer layer 214 are respectively provided with a connecting hole, the first drain electrode 2152 is connected to the light-shielding layer 213 through a connection hole. A plurality of second via holes (not shown in fig. 3) are respectively formed in the passivation layer 216 and the first flat layer 217, the second via holes in the passivation layer 216 are in one-to-one correspondence with the second via holes in the first flat layer 217, the second source electrode 2181 is connected to the first drain electrode 2152 through a set of second via holes, the second drain electrode 2182 is connected to the first source electrode 2151 through a set of second via holes, and each set of second via holes includes two second via holes communicated with the passivation layer 216 and the first flat layer 217.
Optionally, the display substrate provided in the embodiment of the present application may be an Organic Light Emitting Diode (OLED) display substrate, as shown in fig. 3, the display substrate further includes: an anode 220, a pixel defining layer 221 and a spacer layer 222 are sequentially disposed on the second planarization layer 219, a third via hole (not shown in fig. 3) is disposed on the second planarization layer 219, and the anode 220 is connected to the second source 2181 through the third via hole. Of course, in addition, the display substrate may further include an organic light emitting layer and a cathode, and the description of the embodiments of the present application is omitted here.
In the present embodiment, the flexible substrate layer 210 may be a PI layer, and the first active layer 202 may be a polysilicon active layer, for example, the first active layer 202 may be an LTPS active layer, when the first active layer 202 is an LTPS active layer, the first active layer 202, the first gate insulating layer 203, the first gate electrode 204, the first drain electrode 2152, and the first source electrode 2151 connected to the first active layer 202 constitute an LTPS TFT, the second active layer 206 may be an oxide active layer, for example, the second active layer 206 may be an IGZO active layer or an Indium Tin Zinc Oxide (ITZO) active layer, when the second active layer 206 is an oxide active layer, the second active layer 206, the second gate insulating layer 207, the second gate electrode 208, the first drain electrode 2152, and the first source electrode 2151 connected to the second active layer 206 constitute an oxide TFT, as shown in fig. 3, the LTPS TFT and the oxide TFT are connected through a first drain electrode 2152 common to both.
As shown in fig. 3, in the embodiment of the present application, the display substrate has an EB region (not labeled in fig. 3), the EB region of the first buffer layer 212, the EB region of the first gate insulating layer 203, the EB region of the first interlayer dielectric layer 205, the EB region of the second buffer layer 214, and the EB region of the passivation layer 216 are all provided with EB vias (not labeled in fig. 3), and a portion of the first planarization layer 217 located in the EB region is filled in the EB vias. An EB region of any one of the first buffer layer 212, the first gate insulating layer 203, the first interlayer dielectric layer 205, the second buffer layer 214, and the passivation layer 216 is a corresponding region of the EB region of the display substrate on the any one of the layers. In the finished display product, the EB region of the display substrate is bent, and the peripheral region adjacent to the EB region on the display substrate is bent to the back surface (i.e., the non-display surface) of the display substrate, so that the area of the non-display region of the display surface of the display product is small, and even the display surface of the display product does not have the non-display region, thereby facilitating the realization of full-screen display.
In summary, according to the display substrate provided in the embodiment of the present application, since the second active layer and the second interlayer dielectric layer are formed by the same patterning process, compared with the related art, the manufacturing process of the display substrate can reduce one patterning process, thereby simplifying the manufacturing process of the display substrate and reducing the manufacturing cost.
Further, the second interlayer dielectric layer covers the second gate insulating layer, the second gate electrode and a partial region of the upper surface of the second active layer, so that the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology is larger, the area of the second interlayer dielectric layer in the embodiment of the application is smaller, the second interlayer dielectric layer in the embodiment of the application is obtained by patterning the second interlayer dielectric layer in the related technology, and the stress of the second interlayer dielectric layer in the embodiment of the application is released, so that the stress of the second interlayer dielectric layer in the embodiment of the application is smaller, the stress of the second interlayer dielectric layer is easier to control, the display substrate is prevented from being warped, the display substrate can be better applied to products such as flexible and foldable products, and the yield of the display substrate is higher. In addition, the second interlayer dielectric layer in the embodiment of the present application is obtained by patterning the second interlayer dielectric layer in the related art, and compared with the related art, the embodiment of the present application can simplify the film structure of the display substrate.
The display substrate provided by the embodiments of the present application can be applied to the following methods, and the manufacturing method and the manufacturing principle of the display substrate in the embodiments of the present application can be referred to the description of the embodiments below.
Referring to fig. 4, a method flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure is shown, where the method for manufacturing a display substrate can be used to manufacture the display substrate shown in fig. 2 or fig. 3. Referring to fig. 4, the method includes:
step 401, sequentially forming a first active layer, a first gate insulating layer, a first gate electrode and a first interlayer dielectric layer on a substrate.
Step 402, sequentially forming an active layer material layer, a second gate insulating layer, a second gate electrode and an interlayer dielectric material layer on the substrate with the first interlayer dielectric layer.
Step 403, processing the active layer material layer and the interlayer dielectric layer by a one-step composition process to obtain a second active layer and a second interlayer dielectric layer.
In summary, according to the manufacturing method of the display substrate provided in the embodiment of the present application, since the second active layer and the second interlayer dielectric layer are formed through the same patterning process, compared with the related art, the manufacturing process of the display substrate can reduce one patterning process, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced.
Optionally, the shape of the second gate insulating layer is the same as that of the second gate electrode, the second active layer, the second gate insulating layer and the second gate electrode are sequentially stacked, the second interlayer dielectric layer covers partial regions of the upper surfaces of the second gate insulating layer, the second gate electrode and the second active layer, and a region of the upper surface of the second active layer, which is not covered by the second interlayer dielectric layer, is a step surface of a step structure for overlapping with the first source electrode and the first drain electrode to be formed.
Optionally, step 403 includes:
forming a photoresist layer on the interlayer dielectric material layer;
sequentially exposing, developing and etching the substrate base plate with the photoresist layer to obtain an initial interlayer dielectric layer and a photoresist pattern which are sequentially superposed, wherein the shape of the initial interlayer dielectric layer is the same as that of the photoresist pattern;
etching the area, which is not covered by the initial interlayer dielectric layer, on the active layer material layer to obtain a second active layer;
ashing the photoresist pattern to expose an area to be etched of the initial interlayer dielectric layer;
etching the area to be etched of the initial interlayer dielectric layer to obtain a second interlayer dielectric layer, and exposing a step surface of a step structure, which is used for being lapped with a first source electrode and a first drain electrode to be formed, on the second active layer;
and stripping the residual photoresist.
Optionally, after step 403, the method further comprises:
respectively forming a plurality of first through holes on the first interlayer dielectric layer and the first gate insulating layer through a one-time composition process, wherein the plurality of first through holes on the first interlayer dielectric layer are communicated with the plurality of first through holes on the first gate insulating layer in a one-to-one correspondence manner;
sequentially forming a first source drain electrode layer, a passivation layer, a first flat layer, a second source drain electrode layer and a second flat layer on the substrate base plate on which the second interlayer dielectric layer is formed;
wherein, the display substrate is provided with a plurality of display units, in each display unit, the first source drain layer comprises two first source electrodes and one first drain electrode, the second source drain layer comprises a second source electrode and a second drain electrode, one end of one first source electrode and one end of the first drain electrode in the two first source electrodes are respectively lapped on the step structure of the second active layer, the other end of the other first source electrode and the other end of the first drain electrode in the two first source electrodes are respectively connected with the first active layer through a group of first via holes, each group of first via holes comprises two first via holes which are communicated with the first interlayer dielectric layer on the second buffer layer, a plurality of second via holes are respectively formed on the passivation layer and the first flat layer, the plurality of second via holes on the passivation layer are correspondingly communicated with the plurality of second via holes on the first flat layer one by one group of second via holes, the second source electrodes are connected with the first source electrodes through a group of second via holes, and the second drain electrodes are connected with the first drain electrodes through a group of second via, each group of second via holes comprises two second via holes communicated with the first flat layer and the passivation layer.
Optionally, after sequentially forming the first source/drain electrode layer, the passivation layer, the first planarization layer, the second source/drain electrode layer, and the second planarization layer on the substrate base plate on which the second interlayer dielectric layer is formed, the method further includes:
and sequentially forming an anode, a pixel defining layer and a spacer layer on the substrate base plate on which the second flat layer is formed, wherein a third through hole is formed on the second flat layer, and the anode is connected with the second drain electrode through the third through hole.
Optionally, before step 401, the method further comprises:
sequentially forming a flexible base layer, a barrier layer and a first buffer layer on a substrate;
step 401 comprises: a first active layer, a first gate insulating layer, a first gate electrode and a first interlayer dielectric layer are sequentially formed on the substrate base plate with the first buffer layer.
Optionally, before step 402, the method further comprises:
forming a second buffer layer on the substrate with the first interlayer dielectric layer;
step 402 comprises: sequentially forming an active layer material layer, a second gate insulating layer, a second gate and an interlayer dielectric material layer on the substrate with the second buffer layer;
forming a plurality of first via holes on the first interlayer dielectric layer and the first gate insulating layer respectively through a one-time composition process, wherein the plurality of first via holes on the first interlayer dielectric layer are communicated with the plurality of first via holes on the first gate insulating layer in a one-to-one correspondence manner, and the method comprises the following steps:
forming a plurality of first through holes on the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer respectively through a one-time composition process, wherein the plurality of first through holes on the second buffer layer, the plurality of first through holes on the first interlayer dielectric layer and the plurality of first through holes on the first gate insulating layer are communicated in a one-to-one correspondence manner;
the other end of the other first source electrode and the other end of the other first drain electrode are respectively connected with the first active layer through a group of first via holes, and each group of first via holes comprise three first via holes communicated with the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer.
Optionally, the first active layer is a polysilicon active layer, the second active layer is an oxide active layer, and the method further comprises: and forming a shading layer on the substrate with the first grid insulating layer, wherein the shading layer and the first grid are arranged on the same layer and are formed by the same composition process, and the orthographic projection of the second active layer on the substrate is positioned in the orthographic projection area of the shading layer on the substrate.
All the above optional technical solutions may be combined arbitrarily to form optional embodiments of the present application, and are not described herein again.
Referring to fig. 5, a method flowchart of another method for manufacturing a display substrate according to an embodiment of the present disclosure is shown, where the method for manufacturing a display substrate can be used to manufacture the display substrate shown in fig. 2 or fig. 3. This embodiment will be described by taking the example of manufacturing the display substrate shown in fig. 3. Referring to fig. 5, the method includes:
step 501, forming a flexible base layer, a barrier layer and a first buffer layer on a substrate in sequence.
Referring to fig. 6, a flexible base layer 210 formed on a substrate 201 sequentially is shown,In the schematic diagram behind the barrier layer 211 and the first buffer layer 212, the substrate 201 may be a transparent substrate, which may be a substrate made of light-guiding and non-metallic materials with certain firmness, such as glass, quartz or transparent resin, the flexible base layer 210 may be a PI layer, and the barrier layer 211 and the first buffer layer 212 may be made of SiOx (chinese: silicon oxide), SiNx (chinese: silicon nitride), Al (chinese: silicon nitride), or any other material2O3An inorganic material such as (Chinese: alumina) or SiOxNx (Chinese: silicon oxynitride), and a material for forming the barrier layer 211 and a material for forming the first buffer layer 212 may be the same or different.
Optionally, first, a layer of PI is coated on the substrate base plate 201 as the flexible base layer 210; then, a layer of SiOx is deposited as a barrier layer 211 on the substrate 201 on which the flexible base layer 210 is formed by coating, magnetron sputtering, thermal evaporation, or Plasma Enhanced Chemical Vapor Deposition (PECVD); finally, a layer of Al is deposited on the substrate 201 with the barrier layer 211 formed thereon by coating, magnetron sputtering, thermal evaporation or PECVD method2O3As the first buffer layer 212.
Step 502, sequentially forming a first active layer and a first gate insulating layer on the substrate on which the first buffer layer is formed.
Referring to fig. 7, which illustrates a schematic view after a first active layer 202 and a first gate insulating layer 203 are sequentially formed on a substrate 201 on which a first buffer layer 212 is formed, according to an embodiment of the present disclosure, the first active layer 202 may be an amorphous silicon active layer, for example, the first active layer 202 may be an LTPS active layer, and the first gate insulating layer 203 may be formed of SiOx, SiNx, or Al2O3Or an inorganic material such as SiOxNx.
Alternatively, first, a layer of amorphous silicon (a-si) is deposited on the substrate 201 on which the first buffer layer 212 is formed by coating, magnetron sputtering, thermal evaporation, or PECVD, to obtain an amorphous silicon layer, then, the amorphous silicon layer is annealed to convert the amorphous silicon into polysilicon, then, the annealed amorphous silicon layer is processed by a one-step composition process to obtain the first active layer 202, and finally, a layer of SiNx is deposited on the substrate 201 on which the first active layer 202 is formed by coating, magnetron sputtering, thermal evaporation, or PECVD, to serve as the first gate insulating layer 203.
The one-step patterning process includes photoresist coating, exposing, developing, etching, and photoresist stripping, and the annealed amorphous silicon layer is processed by the one-step patterning process to obtain the first active layer 202, including: coating a layer of photoresist on the annealed amorphous silicon layer to obtain a photoresist layer, exposing the photoresist layer by using a mask to form a fully exposed region and a non-exposed region on the photoresist layer, then completely removing the photoresist in the fully exposed region by a developing process, completely retaining the photoresist in the non-exposed region, etching a region corresponding to the fully exposed region on the annealed amorphous silicon layer by using an etching process, and finally stripping the photoresist in the non-exposed region, wherein the region corresponding to the non-exposed region on the annealed amorphous silicon layer is the first active layer 202. It should be noted that, in the embodiment of the present application, the first active layer 202 is formed by using a positive photoresist, and the first active layer 202 may also be formed by using a negative photoresist, which is not limited in the embodiment of the present application.
Step 503, forming a first gate electrode and a light shielding layer on the substrate with the first gate insulating layer formed thereon.
Referring to fig. 8, a schematic diagram of a substrate 201 with a first gate insulating layer 203 formed thereon after forming a first gate electrode 204 and a light-shielding layer 213 is shown, in which the first gate electrode 204 and the light-shielding layer 213 are disposed in the same layer, and the first gate electrode 204 and the light-shielding layer 213 are formed by the same patterning process, so as to simplify a manufacturing process of the display substrate. The material for forming the first gate 204 may be Mo (chinese: molybdenum), Cu (chinese: copper), Al (chinese: aluminum), Ti (chinese: titanium), or an alloy thereof.
Alternatively, a metal Mo material layer is first deposited on the substrate 201 on which the first gate insulating layer 203 is formed by coating, magnetron sputtering, thermal evaporation, or PECVD, and then the metal Mo material layer is processed by a one-step composition process to obtain the first gate electrode 204 and the light-shielding layer 213. The process of processing the metal Mo material layer by the one-step composition process may refer to the process of processing the annealed amorphous silicon layer by the one-step composition process in step 502, which is not described herein again in this embodiment.
Step 504, a first interlayer dielectric layer and a second buffer layer are sequentially formed on the substrate with the first grid electrode and the shading layer.
Referring to fig. 9, which illustrates a schematic view of a substrate 201 having a first gate electrode 204 and a light-shielding layer 213 formed thereon after a first interlayer dielectric layer 205 and a second buffer layer 214 are sequentially formed thereon according to an embodiment of the present disclosure, the first interlayer dielectric layer 205 and the second buffer layer 214 may be formed of SiOx, SiNx, Al2O3Or SiOxNx, the material forming the first interlayer dielectric layer 205 and the material forming the second buffer layer 214 may be the same or different.
Alternatively, first, a layer of SiOxNx is deposited as the first interlayer dielectric layer 205 on the substrate 201 on which the first gate electrode 204 and the light-shielding layer 213 are formed by coating, magnetron sputtering, thermal evaporation, or PECVD; thereafter, a layer of SiOx is deposited as a second buffer layer 214 on the substrate 201 on which the first gate electrode 204 and the light-shielding layer 213 are formed by coating, magnetron sputtering, thermal evaporation, PECVD, or the like.
Step 505, an active layer material layer, a second gate insulating layer, a second gate electrode and an interlayer dielectric material layer are sequentially formed on the substrate with the second buffer layer formed thereon.
Referring to fig. 10, a schematic diagram of an embodiment of the present application is shown after an active layer material layer X, a second gate insulating layer 207, a second gate 208 and an interlayer dielectric material layer Y are sequentially formed on a substrate 201 with a second buffer layer 214 formed thereon, where the second gate insulating layer 207 and the second gate 208 are sequentially stacked, and a shape of the second gate insulating layer 207 is the same as a shape of the second gate 208. The active layer material layer X may be formed of an oxide such as IGZO or ITZO, and the second gate insulating layer 207 and the interlayer dielectric layer Y may be formed of SiOx, SiNx, or Al2O3Or SiOxNx, the second gate insulating layer 207 and the interlayer dielectric layer Y may be formed of the same material or different materials, and the second gate electrode 208 may be formed of Mo, Cu, Al, Ti, or an alloy thereof.
Alternatively, first, a layer of IGZO is deposited as the active layer material layer X on the substrate base plate 201 on which the second buffer layer 214 is formed by a method such as coating, magnetron sputtering, thermal evaporation, or PECVD; then, a second gate insulating layer 207 and a second gate electrode 208 are formed on the substrate base 201 on which the active layer material layer X is formed; finally, a layer of SiOx is deposited as the interlayer dielectric material layer Y on the substrate 201 on which the second gate electrode 208 is formed by coating, magnetron sputtering, thermal evaporation, or PECVD.
The forming of the second gate insulating layer 207 and the second gate 208 on the substrate 201 on which the active layer material layer X is formed includes: the SiNx and the metal Mo are sequentially deposited on the substrate 201 on which the active layer material layer X is formed by coating, magnetron sputtering, thermal evaporation or PECVD, and the like, so that the SiNx material layer and the metal Mo material layer which are sequentially stacked are obtained, and then the SiNx material layer and the metal Mo material layer are processed by a one-step composition process to obtain the second gate insulating layer 207 and the second gate electrode 208. The process of processing the SiNx material layer and the Mo metal layer through the one-step composition process may refer to the process of processing the annealed amorphous silicon layer through the one-step composition process in step 502, which is not described herein again in this embodiment.
Step 506, the active layer material layer and the interlayer dielectric layer are processed through a one-time composition process to obtain a second active layer and a second interlayer dielectric layer.
Referring to fig. 11, a flowchart of a method for processing an active layer material layer and an interlayer dielectric material layer by a one-step patterning process according to an embodiment of the present application is shown, and referring to fig. 11, the method includes:
substep 5061, a photoresist layer is formed on the interlevel dielectric layer.
Referring to fig. 12, a schematic diagram of a photoresist layer Z formed on an interlayer dielectric layer Y according to an embodiment of the present disclosure is shown, wherein the photoresist layer Z may be formed on the interlayer dielectric layer Y by a coating process.
And a substep 5062 of exposing, developing and etching the substrate base plate formed with the photoresist layer in sequence to obtain an initial interlayer dielectric layer and a photoresist pattern which are sequentially superposed, wherein the shape of the initial interlayer dielectric layer is the same as that of the photoresist pattern.
Referring to fig. 13, which shows a schematic diagram of the substrate 201 with the photoresist layer Z formed thereon after sequentially performing exposure, development and etching, an initial interlayer dielectric layer Y1 and a photoresist pattern Z1 are sequentially stacked, a shape of the initial interlayer dielectric layer Y1 is the same as that of the photoresist pattern Z1, and all regions of the photoresist pattern Z1 have the same thickness. Optionally, first, the photoresist layer Z is exposed through an exposure process to form a fully exposed region and a non-exposed region, then, the exposed photoresist layer Z is processed through a development process to completely remove the photoresist in the fully exposed region and completely retain the photoresist in the non-exposed region, and finally, the region corresponding to the fully exposed region on the interlayer dielectric layer Y is etched through an etching process.
And a substep 5063 of etching the area, which is not covered by the initial interlayer dielectric layer, on the active layer material layer to obtain a second active layer.
Referring to fig. 14, a schematic diagram of an area of the active layer material layer X not covered by the initial interlayer dielectric layer Y1 after etching is shown, the active layer material layer X is etched to obtain the second active layer 206, and an orthographic projection of the second active layer 206 on the substrate 201 is located in an orthographic projection area of the light shielding layer 213 on the substrate 201, so that the light shielding layer 213 can shield the second active layer 206 to avoid an influence of light on the second active layer 206, thereby avoiding an influence of light on a switching characteristic of a TFT where the second active layer 206 is located.
It should be noted that, in the embodiment of the present application, the initial interlayer dielectric layer Y1 is used as a mask (mask) to etch the active layer material layer X to obtain the second active layer 206, and compared with the related art in which the second active layer is obtained by processing the active layer material layer through a one-step composition process, the scheme provided in the embodiment of the present application can save a one-step photoresist coating process, a one-step exposure process, a one-step development process, and a one-step photoresist stripping process, so that the manufacturing process of the second active layer 206 can be simplified, thereby simplifying the manufacturing process of the display substrate.
And a substep 5064 of ashing the photoresist pattern to expose the region to be etched of the initial interlayer dielectric layer.
Referring to fig. 15, which shows a schematic diagram of the photoresist pattern Z1 after ashing provided in the present embodiment, the photoresist pattern Z1 may be ashed by using oxygen and sulfur hexafluoride gas, so that the photoresist pattern Z1 is reduced to expose an area to be etched (not shown in fig. 15) of the initial interlayer dielectric layer Y1, and the shape of the photoresist pattern Z1 is changed to obtain a photoresist pattern Z2.
And a substep 5065 of etching the region to be etched of the initial interlayer dielectric layer to obtain a second interlayer dielectric layer, and exposing a step surface of the step structure on the second active layer, wherein the step surface is used for being lapped with the first source electrode and the first drain electrode to be formed.
Referring to fig. 16, a schematic diagram of an area to be etched of the initial interlayer dielectric layer Y1 provided in this embodiment of the present application is shown, after etching, a second interlayer dielectric layer 209 is obtained, and a step surface of a step structure on the second active layer 206 for overlapping with a first source electrode (not shown in fig. 16) and a first drain electrode (not shown in fig. 16) to be formed is exposed.
Substep 5066, strip the remaining photoresist.
Referring to fig. 17, which shows a schematic diagram after stripping the remaining photoresist according to an embodiment of the present application, after stripping the remaining photoresist, the second active layer 206, the second gate insulating layer 207 and the second gate electrode 208 are sequentially stacked, and the second interlayer dielectric layer 209 covers a partial region of the upper surfaces of the second gate insulating layer 207, the second gate electrode 208 and the second active layer 206.
It should be noted that the process of forming the second active layer and the second interlayer dielectric layer shown in fig. 6 is only an example, and in practical applications, a half exposure process may be used for the process of forming the second active layer and the second interlayer dielectric layer. Thus, the sub-steps 5061 to 5066 described above may be replaced with the sub-steps 5061a to 5066a described below:
sub-step 5061a, forming a photoresist layer on the interlevel dielectric material layer.
And a substep 5062a of sequentially performing semi-exposure, development and etching on the substrate base plate on which the photoresist layer is formed to obtain an initial interlayer dielectric layer and a photoresist pattern which are sequentially overlapped, wherein the photoresist pattern comprises a first photoresist region and a second photoresist region, the thickness of the first photoresist region is smaller than that of the second photoresist region, and the first photoresist region corresponds to a region to be etched of the initial interlayer dielectric layer.
Alternatively, the substrate base plate on which the photoresist layer is formed may be half-exposed using a half-tone mask.
And a substep 5063a of etching the area which is not covered by the initial interlayer dielectric layer on the active layer material layer to obtain a second active layer.
And a substep 5064a of removing the photoresist in the first photoresist region to expose the region to be etched of the initial interlayer dielectric layer.
Alternatively, the photoresist in the first photoresist region may be removed by a developing, stripping, or ashing process.
And a substep 5065a of etching the region to be etched of the initial interlayer dielectric layer to obtain a second interlayer dielectric layer, and exposing a step surface of the step structure on the second active layer, wherein the step surface is used for lapping the first source electrode and the first drain electrode to be formed.
Substep 5066a, stripping the photoresist of the second photoresist region.
The sub-steps 5061a to 5066a may be implemented by referring to the sub-steps 5061 to 5066 and related technologies, and the description of the embodiments of the present application is omitted here.
Step 508, a plurality of first via holes are respectively formed on the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer through a one-time composition process, and the plurality of first via holes on the second buffer layer, the plurality of first via holes on the first interlayer dielectric layer and the plurality of first via holes on the first gate insulating layer are communicated in a one-to-one correspondence manner.
Referring to fig. 18, a schematic diagram of a case where a plurality of first via holes are formed on the second buffer layer 214, the first interlayer dielectric layer 205 and the first gate insulating layer 203 through a single patterning process according to an embodiment of the present disclosure is shown, where the plurality of first via holes on the second buffer layer 214, the plurality of first via holes on the first interlayer dielectric layer 205 and the plurality of first via holes on the first gate insulating layer 203 are communicated in a one-to-one correspondence manner to form a plurality of groups of first via holes K1, and each group of first via holes K1 includes three first via holes communicated on the second buffer layer 214, on the first interlayer dielectric layer 205 and on the first gate insulating layer 203. As shown in fig. 18, in the process of forming the first via hole, a connection hole K2 is also formed on the second buffer layer 214 and the first interlayer dielectric layer 205, and an EB via hole K3 is formed in the EB region of the second buffer layer 214, the EB region of the first interlayer dielectric layer 205, the EB region of the first gate insulating layer 203, and the EB region of the first buffer layer 212. The display substrate has an EB region that is bent, and an ED region of any one of the second buffer layer 214, the first interlayer dielectric layer 205, the first gate insulating layer 203, and the first buffer layer 212 is a corresponding region of the EB region of the display substrate on the any one of the layers. The process of forming the first via hole through the one-step patterning process may refer to the process of processing the annealed amorphous silicon layer through the one-step patterning process in step 502, and details of this embodiment are not repeated herein.
Step 509, sequentially forming a first source/drain electrode layer, a passivation layer, a first planarization layer, a second source/drain electrode layer, and a second planarization layer on the substrate with the second interlayer dielectric layer.
Referring to fig. 19, which shows a schematic diagram after a first source-drain layer 215, a passivation layer 216, a first planar layer 217, a second source-drain layer 218, and a second planar layer 219 are sequentially formed on a substrate 201 on which a second interlayer dielectric layer 209 is formed according to an embodiment of the present disclosure, referring to fig. 18 and fig. 19, the first source-drain layer 215 includes two first source electrodes 2151 and a first drain electrode 2152, one end of one first source electrode 2151 and one end of one first drain electrode 2152 of the two first source electrodes 2151 are respectively overlapped on a step structure of the second active layer 206, the other end of the other first source electrode 2151 and the other end of the first drain electrode 2152 of the two first source electrodes 2151 are respectively connected to the first active layer 202 through a group of first via holes K1, and the first drain electrode 2152 is connected to the light-shielding layer 213 through a connection hole K2. The second source/drain layer 218 includes a second source/drain 2181, a second drain/drain 2182 and a source/drain lead 2183, wherein a plurality of second via holes (not shown in fig. 19) are formed on the passivation layer 216 and the first planarization layer 217, the plurality of second via holes on the passivation layer 216 are in one-to-one correspondence with the plurality of second via holes on the first planarization layer 217, the second source/drain 2181 is connected to the first drain/drain 2152 through a set of second via holes, the second drain/drain 2182 is connected to the first source/drain 2151 through a set of second via holes, and each set of second via holes includes two second via holes communicating with the first planarization layer 217 and the passivation layer 216. Further, as shown in fig. 19, EB regions of the passivation layer 216 are formed with EB vias, the EB vias on the passivation layer 216 communicate with the EB vias on the second buffer layer 214, and a portion of the first planarization layer 217 located in the EB regions fills all the EB vias that communicate with each other. The EB area of the passivation layer 216 is the corresponding area of the EB area of the display substrate on the passivation layer 216.
Optionally, the forming materials of the first source drain layer 215 and the second source drain layer 218 may be metal Mo, metal Cu, metal Al, metal Ti, and an alloy material thereof, the forming material of the first source drain layer 215 may be the same as or different from the forming material of the second source drain layer 218, and the forming materials of the passivation layer 216, the first planarization layer 217, and the second planarization layer 219 may be organic resin. Sequentially forming the first source/drain layer 215, the passivation layer 216, the first planarization layer 217, the second source/drain layer 218, and the second planarization layer 219 on the substrate base plate 201 on which the second interlayer dielectric layer 209 is formed may include the following steps:
step (1), depositing a layer of metal Al on the substrate 201 on which the second interlayer dielectric layer 209 is formed by methods such as coating, magnetron sputtering, thermal evaporation or PECVD to obtain a metal Al material layer, and then processing the metal Al material layer by a one-step composition process to obtain the first source drain layer 215.
And (2) depositing a layer of organic resin as a passivation layer 216 on the substrate 201 on which the first source/drain layer 215 is formed by coating, magnetron sputtering, thermal evaporation or PECVD (plasma enhanced chemical vapor deposition) and the like, and then processing the passivation layer 216 by a one-step composition process to form EB (electron beam) via holes on the passivation layer 216.
And (3) depositing an organic resin layer as a first flat layer 217 on the substrate 201 on which the passivation layer 216 is formed by coating, magnetron sputtering, thermal evaporation or PECVD.
And (4) depositing a layer of metal Ti on the substrate base plate 201 on which the first flat layer 217 is formed by methods such as coating, magnetron sputtering, thermal evaporation or PECVD (plasma enhanced chemical vapor deposition), so as to obtain a metal Ti material layer, and then processing the metal Ti material layer by a one-step composition process so as to obtain a second source drain layer 218.
And (5) depositing a layer of organic resin as a second flat layer 219 on the substrate 201 on which the second source/drain layer 218 is formed by coating, magnetron sputtering, thermal evaporation or PECVD and the like.
And 510, sequentially forming an anode, a pixel defining layer and a spacer layer on the substrate with the second flat layer, wherein a third through hole is formed on the second flat layer, and the anode is connected with the second drain through the third through hole.
Referring to fig. 3, after the anode 220, the pixel defining layer 221 and the spacer layer 222 are sequentially formed on the substrate 201 with the second planarization layer 219 formed thereon, a third via hole (not shown in fig. 3) is formed on the second planarization layer 219, and the anode 220 is connected to the second source 2181 through the third via hole.
Alternatively, the anode may be formed of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO) or aluminum-doped zinc oxide (ZnO: Al), and the pixel defining layer 221 and the spacer layer 222 may be formed of an organic resin. Sequentially forming the anode 220, the pixel defining layer 221, and the spacer layer 222 on the substrate base plate 201 on which the second planarization layer 217 is formed may include the steps of:
step (1), depositing a layer of ITO on the substrate base plate 201 on which the second flat layer 217 is formed by methods such as coating, magnetron sputtering, thermal evaporation or PECVD and the like to obtain an ITO material layer, and then processing the ITO material layer by a one-step composition process to obtain the anode 220.
And (2) depositing a layer of organic resin on the substrate 201 on which the anode 220 is formed by coating, magnetron sputtering, thermal evaporation or PECVD (plasma enhanced chemical vapor deposition) and other methods to obtain an organic material layer, and then processing the organic material layer by a one-step composition process to obtain the pixel defining layer 221.
And (3) depositing a layer of organic resin on the substrate 201 on which the pixel defining layer 221 is formed by coating, magnetron sputtering, thermal evaporation or PECVD (plasma enhanced chemical vapor deposition) and other methods to obtain an organic material layer, and then processing the organic material layer by a one-step composition process to obtain the spacer layer 222.
It should be noted that, the sequence of the steps of the method for manufacturing the display substrate provided in the embodiments of the present application may be appropriately adjusted, and the steps may also be increased or decreased according to the circumstances.
In summary, according to the manufacturing method of the display substrate provided in the embodiment of the present application, since the second active layer and the second interlayer dielectric layer are formed through the same patterning process, compared with the related art, the manufacturing process of the display substrate can reduce one patterning process, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced.
Further, the second interlayer dielectric layer covers the second gate insulating layer, the second gate electrode and a partial region of the upper surface of the second active layer, so that the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology is larger, the area of the second interlayer dielectric layer in the embodiment of the application is smaller, the second interlayer dielectric layer in the embodiment of the application is obtained by patterning the second interlayer dielectric layer in the related technology, and the stress of the second interlayer dielectric layer in the embodiment of the application is released, so that the stress of the second interlayer dielectric layer in the embodiment of the application is smaller, the stress of the second interlayer dielectric layer is easier to control, the display substrate is prevented from being warped, the display substrate can be better applied to products such as flexible and foldable products, and the yield of the display substrate is higher. In addition, since the second interlayer dielectric layer in the embodiment of the present application is obtained by patterning the second interlayer dielectric layer in the related art, the embodiment of the present application can simplify the film structure of the display substrate, compared with the related art.
The embodiment of the application also provides a display device which comprises the display substrate provided by the embodiment. The display device may be a full-screen display device, for example, the display device may be a wearable device such as a watch and a bracelet, or the display device may be a mobile terminal such as a mobile phone or a tablet computer, or the display device may be any product or component having a display function such as a television, a display, a notebook computer, a digital photo frame, or a navigator.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (9)

1. A method of manufacturing a display substrate, the method comprising:
sequentially forming a first active layer, a first gate insulating layer, a first gate and a first interlayer dielectric layer on a substrate;
forming a second buffer layer on the substrate with the first interlayer dielectric layer;
sequentially forming an active layer material layer, a second gate insulating layer, a second gate and an interlayer dielectric material layer on the substrate with the second buffer layer;
processing the active layer material layer and the interlayer dielectric layer by a one-time composition process to obtain a second active layer and a second interlayer dielectric layer;
respectively forming a plurality of first via holes on the first interlayer dielectric layer and the first gate insulating layer by a one-time composition process, wherein the plurality of first via holes on the first interlayer dielectric layer are communicated with the plurality of first via holes on the first gate insulating layer in a one-to-one correspondence manner;
sequentially forming a first source drain electrode layer, a passivation layer, a first flat layer, a second source drain electrode layer and a second flat layer on the substrate with the second interlayer dielectric layer;
wherein, the display substrate is provided with a plurality of display units, in each display unit, the first source drain layer comprises two first source electrodes and one first drain electrode, the second source drain layer comprises a second source electrode and a second drain electrode, one end of one first source electrode and one end of the first drain electrode in the two first source electrodes are respectively lapped on the step structure of the second active layer, the other end of the other first source electrode and the other end of the first drain electrode in the two first source electrodes are respectively connected with the first active layer through a group of first through holes, each group of first through holes comprises two first through holes communicated with the second buffer layer and the first interlayer dielectric layer, a plurality of second through holes are respectively formed on the passivation layer and the first flat layer, and the plurality of second through holes on the passivation layer are communicated with the plurality of second through holes on the first flat layer in a one-to-one correspondence manner, the second source electrode is connected with the other first source electrode through a group of second through holes, the second drain electrode is connected with the first drain electrode through a group of second through holes, and each group of second through holes comprises two second through holes communicated with the first flat layer and the passivation layer.
2. The method of claim 1,
the shape of the second gate insulating layer is the same as that of the second gate electrode, the second active layer, the second gate insulating layer and the second gate electrode are sequentially overlapped, the second interlayer dielectric layer covers partial areas of the upper surfaces of the second gate insulating layer, the second gate electrode and the second active layer, and an area, which is not covered by the second interlayer dielectric layer, of the upper surface of the second active layer is a step surface of a step structure overlapped with the first source electrode and the first drain electrode to be formed.
3. The method of claim 2,
the step of processing the active layer material layer and the interlayer dielectric layer by the one-time composition process to obtain a second active layer and a second interlayer dielectric layer comprises the following steps:
forming a photoresist layer on the interlayer dielectric material layer;
sequentially carrying out exposure, development and etching on the substrate base plate with the photoresist layer to obtain an initial interlayer dielectric layer and a photoresist pattern which are sequentially superposed, wherein the shape of the initial interlayer dielectric layer is the same as that of the photoresist pattern;
etching the area, which is not covered by the initial interlayer dielectric layer, on the active layer material layer to obtain a second active layer;
ashing the photoresist pattern to expose a region to be etched of the initial interlayer dielectric layer;
etching the area to be etched of the initial interlayer dielectric layer to obtain a second interlayer dielectric layer, and exposing the step surface of the step structure, which is used for being lapped with the first source electrode and the first drain electrode to be formed, on the second active layer;
and stripping the residual photoresist.
4. The method of claim 1,
after sequentially forming a first source drain layer, a passivation layer, a first flat layer, a second source drain layer and a second flat layer on the substrate base plate on which the second interlayer dielectric layer is formed, the method further comprises:
and sequentially forming an anode, a pixel defining layer and a spacer layer on the substrate base plate on which the second flat layer is formed, wherein a third through hole is formed on the second flat layer, and the anode is connected with the second drain electrode through the third through hole.
5. The method of claim 1,
before a first active layer, a first gate insulating layer, a first gate electrode and a first interlayer dielectric layer are sequentially formed on a substrate, the method further comprises:
sequentially forming a flexible base layer, a barrier layer and a first buffer layer on the substrate base plate;
a first active layer, a first gate insulating layer, a first gate electrode and a first interlayer dielectric layer are sequentially formed on the substrate base plate, and the method comprises the following steps:
and sequentially forming the first active layer, the first gate insulating layer, the first gate electrode and the first interlayer dielectric layer on the substrate with the first buffer layer.
6. The method of claim 1,
forming a plurality of first via holes on the first interlayer dielectric layer and the first gate insulating layer respectively through a one-time composition process, wherein the plurality of first via holes on the first interlayer dielectric layer are communicated with the plurality of first via holes on the first gate insulating layer in a one-to-one correspondence manner, and the method comprises the following steps:
forming a plurality of first via holes on the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer respectively through a one-time composition process, wherein the plurality of first via holes on the second buffer layer, the plurality of first via holes on the first interlayer dielectric layer and the plurality of first via holes on the first gate insulating layer are communicated in a one-to-one correspondence manner;
the other end of the other first source electrode and the other end of the other first drain electrode are respectively connected with the first active layer through a group of first via holes, and each group of first via holes comprise three first via holes communicated with the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer.
7. The method of any of claims 1 to 6, wherein the first active layer is a polysilicon active layer and the second active layer is an oxide active layer, the method further comprising:
and forming a light shielding layer on the substrate with the first gate insulating layer, wherein the light shielding layer and the first gate are arranged on the same layer and are formed by the same composition process, and the orthographic projection of the second active layer on the substrate is positioned in the orthographic projection area of the light shielding layer on the substrate.
8. A display substrate, comprising: the structure comprises a substrate base plate, a first active layer, a first grid electrode, a first interlayer dielectric layer, a second buffer layer, a second active layer, a second grid electrode, a second interlayer dielectric layer, a first source drain electrode layer, a passivation layer, a first flat layer, a second source drain electrode layer and a second flat layer, wherein the first active layer, the first grid electrode, the second buffer layer, the second active layer, the second grid electrode, the second interlayer dielectric layer, the first source drain electrode layer, the passivation layer, the first flat layer, the second source drain electrode layer and the second flat layer are arranged on the substrate base plate, the shape of the second grid electrode insulating layer is the same as that of the second grid electrode, the second active layer, the second grid electrode and the second grid electrode are sequentially overlapped, the second interlayer dielectric layer covers the second grid electrode insulating layer, the second grid electrode and partial area of the upper surface of the second active layer, the area, which is not covered by the second interlayer dielectric layer, of the upper surface of the second active layer, a plurality of first via holes are respectively formed in the second buffer layer, the first interlayer dielectric layer and the first gate insulating layer through a one-time composition process, and the plurality of first via holes in the second buffer layer, the plurality of first via holes in the first interlayer dielectric layer and the plurality of first via holes in the first gate insulating layer are communicated in a one-to-one correspondence manner;
the display substrate is also provided with a plurality of display units, in each display unit, the first source drain layer comprises two first source electrodes and one first drain electrode, the second source drain layer comprises a second source electrode and a second drain electrode, one end of one first source electrode and one end of the first drain electrode in the two first source electrodes are respectively lapped on the step structure of the second active layer, the other end of the other first source electrode and the other end of the first drain electrode in the two first source electrodes are respectively connected with the first active layer through a group of first through holes, each group of first through holes comprises two first through holes communicated with the first interlayer dielectric layer on the second buffer layer, a plurality of second through holes are respectively formed on the passivation layer and the first flat layer, and the plurality of second through holes on the passivation layer are communicated with the plurality of second through holes on the first flat layer in a one-to-one correspondence manner, the second source electrode is connected with the other first source electrode through a group of second through holes, the second drain electrode is connected with the first drain electrode through a group of second through holes, and each group of second through holes comprises two second through holes communicated with the first flat layer and the passivation layer.
9. A display device, characterized in that the display device comprises the display substrate of claim 8.
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