CN109300840A - Display base plate and its manufacturing method, display device - Google Patents

Display base plate and its manufacturing method, display device Download PDF

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Publication number
CN109300840A
CN109300840A CN201811159425.1A CN201811159425A CN109300840A CN 109300840 A CN109300840 A CN 109300840A CN 201811159425 A CN201811159425 A CN 201811159425A CN 109300840 A CN109300840 A CN 109300840A
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layer
interlayer dielectric
gate insulation
dielectric layer
active layer
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CN109300840B (en
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周天民
王利忠
杨维
黄睿
卢鑫泓
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses a kind of display base plate and its manufacturing method, display device, belongs to field of display technology.This method comprises: sequentially forming the first active layer, the first gate insulation layer, first grid and the first interlayer dielectric layer on underlay substrate；Active layer material layers, the second gate insulation layer, second grid and inter-level dielectric material layers are sequentially formed on the underlay substrate for being formed with the first interlayer dielectric layer；Active layer material layers and inter-level dielectric material layers are handled by a patterning processes, obtain the second active layer and the second interlayer dielectric layer.Present application addresses the manufacturing process of display base plate complexity, the higher problem of manufacturing cost simplifies the manufacturing process of display base plate, reduces the manufacturing cost of display base plate.The application is used for the manufacture of LTPO substrate.

Description

Display base plate and its manufacturing method, display device
Technical field
This application involves field of display technology, in particular to a kind of display base plate and its manufacturing method, display device.
Background technique
Low-temperature polysilicon oxide (English: Low temperature polycrystalline oxide；Referred to as: LTPO) Substrate is a kind of novel display base plate, with low temperature polycrystalline silicon (English: Low Temperature Poly-silicon； Referred to as: LTPS) substrate and oxide (English: Oxide) substrate the advantages of, be the main direction of development of the following display base plate.Its In, LTPS substrate refers to the thin film transistor (TFT) (English: Thin Film Transistor in display unit；Referred to as: TFT) it is The display base plate of LTPS TFT, oxide substrate refer to that the TFT in display unit is the display base plate of oxide TFT, LTPO It include the display base plate of LTPS TFT and oxide TFT in each display unit that substrate refers to, display unit is also referred to as sub-pixel.
In the related technology, LTPO substrate includes underlay substrate, and, polyimide layer on underlay substrate, resistance are set Barrier, first buffer layer, polysilicon active layer, the first gate insulation layer, first grid, the first interlayer dielectric layer, second buffer layer, Oxide active layer, the second gate insulation layer, second grid, the second interlayer dielectric layer, source-drain electrode connecting line, the first source-drain electrode layer, Passivation layer, the first flatness layer, the second source-drain electrode layer, the second flatness layer, anode, pixel defining layer and spacer layer.It is somebody's turn to do in manufacture During LTPO substrate, polysilicon active layer, first grid, the first interlayer dielectric layer, oxide active layer, second grid, Second interlayer dielectric layer, source-drain electrode connecting line, the first source-drain electrode layer, passivation layer, the first flatness layer, the second source-drain electrode layer, second The manufacture of this 14 film layers of flatness layer, anode and pixel defining layer is required to handle by a patterning processes.
During realizing the application, inventor find the relevant technologies the prior art has at least the following problems:
Due to polysilicon active layer, first grid, the first interlayer dielectric layer, oxide active layer, second grid, the second layer Between dielectric layer, source-drain electrode connecting line, the first source-drain electrode layer, passivation layer, the first flatness layer, the second source-drain electrode layer, the second flatness layer, The manufacture of this 14 film layers of anode and pixel defining layer is required to handle by a patterning processes, therefore the manufacture of LTPO substrate Process at least needs 14 patterning processes, and the manufacturing process of the LTPO substrate is complicated, and manufacturing cost is higher.
Summary of the invention
The application provides a kind of display base plate and its manufacturing method, display device, can simplify the manufacture of display base plate Journey reduces manufacturing cost.The technical solution of the application is as follows:
In a first aspect, providing a kind of manufacturing method of display base plate, which comprises
The first active layer, the first gate insulation layer, first grid and the first interlayer dielectric layer are sequentially formed on underlay substrate；
Active layer material layers, the second gate insulation are sequentially formed on the underlay substrate for being formed with first interlayer dielectric layer Layer, second grid and inter-level dielectric material layers；
The active layer material layers and the inter-level dielectric material layers are handled by a patterning processes, obtain Two active layers and the second interlayer dielectric layer.
Optionally, the shape of second gate insulation layer is identical as the shape of the second grid, second active layer, Second gate insulation layer and the second grid are sequentially overlapped, and second interlayer dielectric layer covers second gate insulation The partial region of the upper surface of layer, the second grid and second active layer, in the upper surface of second active layer not The region covered by second interlayer dielectric layer be for the first source electrode to be formed and the first drain electrode overlapped Step-edge Junction The step surface of structure.
Optionally, described to pass through a patterning processes to the active layer material layers and inter-level dielectric material layers progress Processing, obtains the second active layer and the second interlayer dielectric layer, comprising:
Photoresist layer is formed in the inter-level dielectric material layers；
The underlay substrate for being formed with the photoresist layer is successively exposed, developed and etched, is sequentially overlapped Initial interlayer dielectric layer and photoetching offset plate figure, the shape and the shape phase of the photoetching offset plate figure of the initial interlayer dielectric layer Together；
To in the active layer material layers, is not performed etching by the region that the initial interlayer dielectric layer covers, obtain institute State the second active layer；
The photoetching offset plate figure is ashed, the region to be etched of the initial interlayer dielectric layer is exposed；
The region to be etched of the initial interlayer dielectric layer is performed etching, obtains the second interlayer dielectric layer, described in exposing For the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure on second active layer；
Remove remaining photoresist.
Optionally, by a patterning processes to the active layer material layers and the inter-level dielectric material layers at Reason, after obtaining the second active layer and the second interlayer dielectric layer, the method also includes:
It is respectively formed on first interlayer dielectric layer and on first gate insulation layer by a patterning processes more A first via hole, multiple first mistakes on multiple first via holes and first gate insulation layer on first interlayer dielectric layer Hole corresponds connection；
The first source-drain electrode layer, passivation layer, are sequentially formed on the underlay substrate for being formed with second interlayer dielectric layer One flatness layer, the second source-drain electrode layer and the second flatness layer；
Wherein, the display base plate has multiple display units, in each display unit, the first source-drain electrode layer packet Two the first source electrodes and one first drain electrode are included, the second source-drain electrode layer includes that the second source electrode and second drain, described two One end of first source electrode and first drain electrode in first source electrode is overlapped on the Step-edge Junction of second active layer respectively On structure, the other end of another first source electrode and first drain electrode in described two first source electrodes passes through respectively described in one group First via hole is connect with first active layer, and the first via hole described in every group includes in the second buffer layer and the first layer Between coconnected two the first via holes of dielectric layer, be respectively formed with multiple second on the passivation layer and on first flatness layer Via hole, multiple second via holes on the passivation layer are connected to multiple second via holes one-to-one correspondence on first flatness layer, Second source electrode is connect by the second via hole described in one group with another described first source electrode, and second drain electrode passes through one group Second via hole and first drain electrode connect, and the second via hole described in every group includes on first flatness layer and the passivation Coconnected two the second via hole of layer.
Optionally, the first source-drain electrode layer, blunt is sequentially formed on the underlay substrate for being formed with second interlayer dielectric layer After changing layer, the first flatness layer, the second source-drain electrode layer and the second flatness layer, the method also includes:
Anode, pixel defining layer and spacer layer are sequentially formed on the underlay substrate for being formed with second flatness layer, Third via hole is formed on second flatness layer, the anode is connected by the third via hole and second drain electrode.
Optionally, the first active layer, the first gate insulation layer, first grid and the first interlayer are sequentially formed on underlay substrate Before dielectric layer, the method also includes:
Flexible base layer, barrier layer and first buffer layer are sequentially formed on underlay substrate；
The first active layer, the first gate insulation layer, first grid and the first inter-level dielectric are sequentially formed on the underlay substrate Layer, comprising:
The first active layer, the first gate insulation layer, are sequentially formed on the underlay substrate for being formed with the first buffer layer One grid and the first interlayer dielectric layer.
Optionally, active layer material layers, are sequentially formed on the underlay substrate for being formed with first interlayer dielectric layer Before two gate insulation layers, second grid and inter-level dielectric material layers, the method also includes:
Second buffer layer is formed on the underlay substrate for being formed with first interlayer dielectric layer；
It is described to sequentially form active layer material layers, second gate on the underlay substrate for being formed with first interlayer dielectric layer Insulating layer, second grid and inter-level dielectric material layers, comprising:
Sequentially formed on the underlay substrate for being formed with the second buffer layer active layer material layers, the second gate insulation layer, Second grid and inter-level dielectric material layers；
It is described to distinguish shape on first interlayer dielectric layer and on first gate insulation layer by a patterning processes At multiple first via holes, on multiple first via holes on first interlayer dielectric layer and first gate insulation layer multiple the One via hole corresponds connection, comprising:
Through a patterning processes in the second buffer layer, on first interlayer dielectric layer and the first grid is exhausted Multiple first via holes are respectively formed in edge layer, multiple first via holes, first interlayer dielectric layer in the second buffer layer On multiple first via holes and first gate insulation layer on multiple first via holes correspond connection；
Wherein, another described first source electrode and it is described first drain electrode the other end pass through one group respectively described in the first via hole It is connect with first active layer, the first via hole described in every group includes in the second buffer layer, first interlayer dielectric layer Upper and coconnected three the first via holes of first gate insulation layer.
Optionally, first active layer is polysilicon active layer, and second active layer is oxide active layer, described Method further include:
Light shield layer, the light shield layer and the first grid are formed on the underlay substrate for being formed with first gate insulation layer Pole same layer is arranged and by being formed with a patterning processes, and orthographic projection of second active layer on the underlay substrate is located at The light shield layer is in the orthographic projection region on the underlay substrate.
Second aspect provides a kind of display base plate, and the display base plate includes: underlay substrate, and, it is arranged in the lining The first active layer, the first gate insulation layer, first grid, the first interlayer dielectric layer, the second active layer, second gate on substrate is exhausted The shape of edge layer, second grid and the second interlayer dielectric layer, second gate insulation layer is identical as the shape of the second grid, Second active layer, second gate insulation layer and the second grid are sequentially overlapped, the second interlayer dielectric layer covering The partial region of the upper surface of second gate insulation layer, the second grid and second active layer, described second is active The region not covered by second interlayer dielectric layer in the upper surface of layer is for leaking with the first source electrode to be formed and first The step surface of overlapped for pole step structure.
The third aspect, provides a kind of display device, and the display device includes display base plate described in second aspect
Technical solution provided by the present application has the benefit that
Display base plate provided by the present application and its manufacturing method, display device, since the second active layer and the second interlayer are situated between Matter layer with a patterning processes by forming, therefore compared to the relevant technologies, the manufacturing process of the display base plate can reduce one Secondary patterning processes simplify the manufacturing process of display base plate, reduce manufacturing cost.Further, due to the second inter-level dielectric The partial region of the upper surface of the second gate insulation layer of layer covering, second grid and the second active layer, therefore the second interlayer dielectric layer Area it is smaller, the area of the second interlayer dielectric layer in the related technology is larger, the face of the second interlayer dielectric layer in the application Product is smaller, and the second interlayer dielectric layer in the application, which is equivalent to, pattern to the second interlayer dielectric layer in the related technology It arrives, the second interlayer dielectric layer in the application, which is equivalent to, releases the stress of the second interlayer dielectric layer in the related technology It puts, therefore the stress of the second interlayer dielectric layer in the application is smaller, the stress of the second interlayer dielectric layer is relatively easy to control, and avoids showing Show the warpage of substrate, it is higher that display base plate can preferably be applied to products, the yields of display base plate such as flexible foldable.This Outside, the second interlayer dielectric layer in the application is equivalent to is patterned to obtain to the second interlayer dielectric layer in the related technology , relative to the relevant technologies, the application can simplify the film layer structure of display base plate.
It should be understood that the above general description and the following detailed description are merely exemplary, this can not be limited Application.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of structural schematic diagram for LTPO substrate that the relevant technologies provide；
Fig. 2 is a kind of structural schematic diagram of display base plate provided by the embodiments of the present application；
Fig. 3 is the structural schematic diagram of another display base plate provided by the embodiments of the present application；
Fig. 4 is a kind of method flow diagram of the manufacturing method of display base plate provided by the embodiments of the present application；
Fig. 5 is the method flow diagram of the manufacturing method of another display base plate provided by the embodiments of the present application.
Fig. 6 is that one kind provided by the embodiments of the present application sequentially forms flexible base layer, barrier layer and on underlay substrate Schematic diagram after one buffer layer；
Fig. 7 is provided by the embodiments of the present application a kind of first to be sequentially formed on the underlay substrate for be formed with first buffer layer Schematic diagram after active layer and the first gate insulation layer；
Fig. 8 is provided by the embodiments of the present application a kind of to form the first grid on the underlay substrate for being formed with the first gate insulation layer Schematic diagram behind pole and light shield layer；
Fig. 9 is a kind of successively shape on the underlay substrate for being formed with first grid and light shield layer provided by the embodiments of the present application At the schematic diagram after the first interlayer dielectric layer and second buffer layer；
Figure 10 is provided by the embodiments of the present application a kind of is sequentially formed on the underlay substrate for be formed with second buffer layer Schematic diagram after active layer material layers, the second gate insulation layer, second grid and inter-level dielectric material layers；
Figure 11 is that one kind provided by the embodiments of the present application passes through a patterning processes to active layer material layers and inter-level dielectric The method flow diagram that material layers are handled；
Figure 12 is a kind of schematic diagram formed after photoresist layer in inter-level dielectric material layers provided by the embodiments of the present application；
Figure 13 is provided by the embodiments of the present application a kind of to be successively exposed, show to the underlay substrate for being formed with photoresist layer Schematic diagram after shadow and etching；
Figure 14 is the schematic diagram after a kind of pair of active layer material layers provided by the embodiments of the present application perform etching；
Figure 15 is the schematic diagram after a kind of pair of photoetching offset plate figure provided by the embodiments of the present application is ashed；
Figure 16 is after a kind of region to be etched to initial interlayer dielectric layer provided by the embodiments of the present application performs etching Schematic diagram；
Figure 17 is a kind of schematic diagram removed after remaining photoresist provided by the embodiments of the present application；
Figure 18 is one kind provided by the embodiments of the present application in second buffer layer, on the first interlayer dielectric layer and the first grid is exhausted Schematic diagram after being respectively formed multiple first via holes in edge layer；
Figure 19 is a kind of successively shape on the underlay substrate for being formed with the second interlayer dielectric layer provided by the embodiments of the present application At the schematic diagram after the first source-drain electrode layer, passivation layer, the first flatness layer, the second source-drain electrode layer and the second flatness layer.
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the application Example, and together with specification it is used to explain the principle of the application.
Specific embodiment
In order to keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with attached drawing to the application make into It is described in detail to one step, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole implementation Example.Based on the embodiment in the application, obtained by those of ordinary skill in the art without making creative efforts All other embodiment, shall fall in the protection scope of this application.
Display base plate is the main component of display device comprising underlay substrate and the display being arranged on underlay substrate Unit, display unit include TFT.LTPS substrate refers to that the TFT in display unit is the display base plate of LTPS TFT, oxide Substrate refers to that the TFT in display unit is the display base plate of oxide TFT.The mobility of polysilicon active layer is larger, so that The leakage current (English: Ioff) of LTPS TFT is larger, and power consumption of the LTPS substrate under low frequency driving is larger, it is difficult to keep well Static dark picture, picture quality are poor；Also, in order to which grayscale is preferably unfolded, in LTPS substrate, need that film will be driven brilliant Body pipe (English: Driver Thin Film Transistor；Channel referred to as: DTFT) makes very long, is thus difficult to reality The high-resolution of existing LTPS substrate, resolution ratio refer to the (English: Pixel Per Inch of number of pixels set by per inch； Referred to as: PPI)；In addition, the sluggishness (English: Hysteresis) of polysilicon active layer is larger, therefore LTPS substrate is easy to appear picture The problem of face image retention.The mobility of oxide active layer is smaller, so that the leakage current of oxide TFT is smaller, oxide substrate exists Power consumption under low frequency driving is smaller, can be good at keeping static dark picture, promotes picture quality；Also, in oxide substrate In, without grayscale can preferably be unfolded, realize high PPI by the very long of the channel production of DTFT；In addition, oxide active layer Sluggishness it is smaller, oxide substrate is not easy damaged picture problem occur；Further, the homogeneity ratio LTPS of oxide TFT The homogeneity of TFT is good.
From the above description, it can be seen that oxide process can be good at making up some shortcomings of LTPS technique.But LTPS Technique and oxide process cut both ways, and are a kind of very competitive technique by LTPS technique and oxide process therefore The technique that LTPS technique and oxide process combine is LTPO technique by scheme, and LTPO technique is following probably to be applied in height In the exploitation for holding product.But the difference of LTPS technique and oxide process is larger, process compatible is more difficult, leads to LTPO The stability of technique is difficult to ensure.
Display base plate based on LTPO technique is LTPO substrate, and in LTPO substrate, each display unit includes LTPS TFT and oxide TFT.Referring to FIG. 1, a kind of structural schematic diagram of the LTPO substrate provided it illustrates the relevant technologies, referring to Fig. 1, the LTPO substrate include underlay substrate 101 and the polyimides being successively set on underlay substrate 101 (English: Polyimide；Referred to as: PI) layer 102, stop (English: Barrier) layer 103, first buffering (English: Buffer) layer 104, be more Crystal silicon (referred to as: P-Si) active layer 105, the first gate insulation (English: Gate Insulator；Referred to as: GI) layer 106, the first grid Pole (English: Gate) the 107, first inter-level dielectric (English: inter-layer Dielectric；Referred to as: ILD) layer 108, second Buffer layer 109, indium gallium zinc oxide (English: indium gallium zinc oxide；Referred to as: IGZO) active layer 110, Two GI layers 111, second grid 112, the second ILD layer 113, source-drain electrode connecting line 114, the first source and drain (English: Source Drain；Referred to as: SD) pole layer 115, passivation (English: Passivation；Referred to as: PVX) layer 116, first it is flat (English: Planarization；Referred to as: PLN) layer 117, the second source-drain electrode layer 118, the 2nd PLN layer 119, anode (English: Anode；Letter Claim: AND) 120, pixel defining layer (English: Pixel Definition Layer；Referred to as: PDL) 121 and spacer material (English: Photo Spacer；Referred to as: PS) layer 122.Drain bond wires 114 include source connection lines 1141 and drain bond wires 1142, the One source-drain electrode layer 115 includes the first source electrode 1151 and the first drain electrode 1152, and the second source-drain electrode layer 118 includes 1181 He of the second source electrode Second drain electrode 1182.
The manufacturing process of LTPO substrate shown in FIG. 1 at least needs 14 patterning processes, therefore the manufacture of the LTPO substrate Process is complicated, and manufacturing cost is higher.In addition, the film layer structure of the LTPO substrate is complicated, the area of the second ILD layer 113 it is larger and The thickness of second ILD layer 113 is larger, causes the stress of the second ILD layer 113 larger, and the stress of the second ILD layer 113 is difficult to control, LTPO substrate is easy to happen warpage, it is difficult to meet the needs of products such as flexible foldable.In addition, LTPO substrate warp can also be led During carrying LTPO substrate, underlay substrate (underlay substrate is usually glass material) generation fragment of LTPO substrate, shadow Ring the yield of LTPO substrate.
Display base plate provided by the present application and its manufacturing method, display device, display base plate can be LTPO substrate, aobvious Show in the manufacturing process of substrate, the second active layer (such as IGZO active layer) and the second interlayer dielectric layer pass through with a composition work Skill is formed, therefore can reduce the number of the patterning processes of the manufacturing process needs of display base plate, simplifies the manufacture of display base plate Process reduces manufacturing cost, wherein the application uses during forming the second active layer and the second interlayer dielectric layer Cineration technics or half-exposure technique；In addition, the area of the second interlayer dielectric layer is smaller in the display base plate, so that the second interlayer The stress of dielectric layer is smaller, and the stress of the second interlayer dielectric layer is relatively easy to control, and improves the warpage of display base plate, the display base plate The demand that can satisfy the products such as flexible foldable improves the yield of display base plate.The detailed protocol of the application please refers to down State embodiment.
Referring to FIG. 2, it illustrates a kind of structural schematic diagram of display base plate provided by the embodiments of the present application, the display base Plate can be LTPO substrate, and referring to fig. 2, which includes:
Underlay substrate 201, and, be arranged in the first active layer 202 on underlay substrate 201, the first gate insulation layer 203, First grid 204, the first interlayer dielectric layer 205, the second active layer 206, the second gate insulation layer 207, second grid 208 and second Interlayer dielectric layer 209.
The shape of second gate insulation layer 207 is identical as the shape of second grid 208, the second active layer 206, the second gate insulation Layer 207 and second grid 208 are sequentially overlapped, and the second interlayer dielectric layer 209 covers the second gate insulation layer 207,208 and of second grid The partial region of the upper surface of second active layer 206, not by the second interlayer dielectric layer 209 in the upper surface of the second active layer 206 The region of covering is for the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure.
Wherein, the upper surface of the second active layer 206 is the table in the surface of the second active layer 206 far from underlay substrate 201 Face, the second active layer 206 and the second interlayer dielectric layer 209 with a patterning processes by forming.
In conclusion display base plate provided by the embodiments of the present application, since the second active layer and the second interlayer dielectric layer are logical It crosses and is formed with a patterning processes, therefore compared to the relevant technologies, the manufacturing process of the display base plate can reduce by a composition Technique simplifies the manufacturing process of display base plate, reduces manufacturing cost.
Further, since the second interlayer dielectric layer covers the upper of the second gate insulation layer, second grid and the second active layer The partial region on surface, therefore the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology Larger, the area of the second interlayer dielectric layer in the embodiment of the present application is smaller, the second interlayer dielectric layer in the embodiment of the present application It is equivalent to and the second interlayer dielectric layer in the related technology is patterned, the second interlayer in the embodiment of the present application is situated between Matter layer, which is equivalent to, discharges the stress of the second interlayer dielectric layer in the related technology, therefore the second interlayer of the application is situated between The stress of matter layer is smaller, and the stress of the second interlayer dielectric layer is relatively easy to control, and avoids the warpage of display base plate, and display base plate can be more Good is higher applied to products, the yields of display base plate such as flexible foldables.In addition, the second interlayer in the embodiment of the present application is situated between Matter layer, which is equivalent to, patterns the second interlayer dielectric layer in the related technology, relative to the relevant technologies, the application Embodiment can simplify the film layer structure of display base plate.
Further, referring to FIG. 3, it illustrates the structural representations of another display base plate provided by the embodiments of the present application Figure, on the basis of Fig. 2, the display base plate further include: flexible base layer 210 on underlay substrate 201, barrier layer are set 211 and first buffer layer 212, the shading (English: Light shield on the first gate insulation layer 203 is set；Referred to as: LS) layer 213, the second buffer layer 214 between the first interlayer dielectric layer 205 and the second active layer 206 is set, and, it is successively set on The first source-drain electrode layer 215, passivation layer 216, the first flatness layer being formed on the underlay substrate 201 of the second interlayer dielectric layer 205 217, the second source-drain electrode layer 218 and the second flatness layer 219.First active layer 202 is arranged in first buffer layer 212, light shield layer 213 are arranged with 204 same layer of first grid, and light shield layer 213 can be formed with first grid 204 by a same patterning processes, the Two active layers 206 are located at light shield layer 213 in the orthographic projection region on underlay substrate 201 in the orthographic projection on underlay substrate 201. In the embodiment of the present application, the second active layer 206 can be oxide active layer, since illumination will affect oxide active layer Mobility, to influence the switching characteristic of TFT, in the embodiment of the present application, the second active layer 206 on underlay substrate 201 just Projection is located at light shield layer 213 in the orthographic projection region on underlay substrate 201, and so, light shield layer 213 can have to second Active layer 206 is blocked, and influence of the illumination to the second active layer 206 is avoided, to avoid illumination to the shadow of the switching characteristic of TFT It rings.
In the embodiment of the present application, display base plate has multiple display units (one is only shown in Fig. 3), in each display In unit, the first source-drain electrode layer 215 includes two the first source electrodes 2151 and one first drain electrode 2152, the second source-drain electrode layer 218 Including the second source electrode 2181, second drain electrode 2182 and source-drain electrode lead 2183, source-drain electrode lead 2183 is used for the second source electrode 2181 lead to outside display base plate, to apply data voltage to display base plate.In second buffer layer 214, the first interlayer dielectric layer 205 Be respectively arranged on the first gate insulation layer 203 multiple first via holes (not marked in Fig. 3), it is multiple in second buffer layer 214 Multiple first via holes on multiple first via holes and the first gate insulation layer 203 on first via hole, the first interlayer dielectric layer 205 Connection is corresponded, one end of first source electrode 2151 in two the first source electrodes 2151 and the first drain electrode 2152 overlaps respectively Another 2151 He of the first source electrode on the step surface of the step structure of the second active layer 206, in two the first source electrodes 2151 The other end of first drain electrode 2152 passes through one group of first via hole respectively and connect with the first active layer 202, and every group of first via hole includes On first gate insulation layer 203, on the first interlayer dielectric layer 205 and 214 coconnected three the first via holes of second buffer layer, first Interlayer dielectric layer 205 and second buffer layer 214 are respectively arranged with connecting hole, and the first drain electrode 2152 passes through connecting hole and light shield layer 213 connections.On passivation layer 216 and multiple second via holes (not marking in Fig. 3) are respectively arranged on the first flatness layer 217, are passivated Multiple second via holes on layer 216 are connected to multiple second via holes one-to-one correspondence on the first flatness layer 217, the second source electrode 2181 It is connect by one group of second via hole with another described first source electrode 2151, the second drain electrode 2182 passes through one group of second via hole and the One drain electrode, 2152 connection, every group of second via hole includes on passivation layer 216 and coconnected two the second mistakes of the first flatness layer 217 Hole.
Optionally, display base plate provided by the embodiments of the present application can be Organic Light Emitting Diode (English: Organic Light Emitting Diode；Referred to as: OLED) display base plate, as shown in figure 3, the display base plate further include: be successively set on Anode 220, pixel defining layer 221 and spacer layer 222 on second flatness layer 219 are provided with third on second flatness layer 219 Via hole (does not mark) in Fig. 3, and anode 220 is connect by third via hole with the second drain electrode 2182.Certainly, in addition to this, base is shown Plate can also include the structures such as organic luminous layer and cathode, and details are not described herein for the embodiment of the present application.
In the embodiment of the present application, flexible base layer 210 can be PI layers, and the first active layer 202 can have for polysilicon Active layer, for example, the first active layer 202 can be LTPS active layer, when the first active layer 202 is LTPS active layer, first has Active layer 202, the first gate insulation layer 203, first grid 204, first drain electrode 2152 and connect with the first active layer 202 first Source electrode 2151 constitutes LTPS TFT, and the second active layer 206 can be oxide active layer, for example, the second active layer 206 can be IGZO active layer or indium tin zinc oxide (English: indium tin zinc oxide；Referred to as: ITZO) active layer etc., when second When active layer 206 is oxide active layer, the second active layer 206, the second gate insulation layer 207, second grid 208, first drain 2152 and the first source electrode 2151 for being connect with the second active layer 206 constitute oxide TFT, as shown in figure 3, LTPS TFT and oxygen 2152 connection of the first drain electrode that compound TFT is shared by the two.
As shown in figure 3, in the embodiment of the present application, display base plate has the region EB (not marking in Fig. 3), first buffer layer 212 region EB, the region EB of the first gate insulation layer 203, the region EB of the first interlayer dielectric layer 205, second buffer layer 214 The region EB and the region EB of passivation layer 216 are provided with EB via hole (not marking in Fig. 3), and the first flatness layer 217 is located at the region EB In part be filled in EB via hole.Wherein, first buffer layer 212, the first gate insulation layer 203, the first interlayer dielectric layer 205, The region EB of any film layer is the region EB of display base plate in any film layer in second buffer layer 214 and passivation layer 216 Corresponding region.In the display product of finished product, the region EB of display base plate is bent over, adjacent with the region EB on display base plate Neighboring area is bent over to the back side of display base plate (that is to say non-display face) and so shows the non-of the display surface of product The area of display area is smaller, it might even be possible to so that the display surface for showing product is not had non-display area, be easy to implement comprehensive screen Display.
In conclusion display base plate provided by the embodiments of the present application, since the second active layer and the second interlayer dielectric layer are logical It crosses and is formed with a patterning processes, therefore compared to the relevant technologies, the manufacturing process of the display base plate can reduce by a composition Technique simplifies the manufacturing process of display base plate, reduces manufacturing cost.
Further, since the second interlayer dielectric layer covers the upper of the second gate insulation layer, second grid and the second active layer The partial region on surface, therefore the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology Larger, the area of the second interlayer dielectric layer in the embodiment of the present application is smaller, the second interlayer dielectric layer in the embodiment of the present application It is equivalent to and the second interlayer dielectric layer in the related technology is patterned, the second interlayer in the embodiment of the present application is situated between Matter layer, which is equivalent to, discharges the stress of the second interlayer dielectric layer in the related technology, therefore the second interlayer of the application is situated between The stress of matter layer is smaller, and the stress of the second interlayer dielectric layer is relatively easy to control, and avoids the warpage of display base plate, and display base plate can be more Good is higher applied to products, the yields of display base plate such as flexible foldables.In addition, the second interlayer in the embodiment of the present application is situated between Matter layer, which is equivalent to, patterns the second interlayer dielectric layer in the related technology, relative to the relevant technologies, the application Embodiment can simplify the film layer structure of display base plate.
Display base plate provided by the embodiments of the present application can be applied to method hereafter, display base plate in the embodiment of the present application Manufacturing method and manufacturing theory may refer to the description in hereafter each embodiment.
Referring to FIG. 4, it illustrates a kind of method flows of the manufacturing method of display base plate provided by the embodiments of the present application Figure, the manufacturing method of the display base plate can be used for manufacturing Fig. 2 or display base plate shown in Fig. 3.Referring to fig. 4, this method comprises:
Step 401 sequentially forms the first active layer, the first gate insulation layer, first grid and first layer on underlay substrate Between dielectric layer.
Step 402 sequentially forms active layer material layers, second gate on the underlay substrate for being formed with the first interlayer dielectric layer Insulating layer, second grid and inter-level dielectric material layers.
Step 403 is handled active layer material layers and inter-level dielectric material layers by a patterning processes, obtains Two active layers and the second interlayer dielectric layer.
In conclusion the manufacturing method of display base plate provided by the embodiments of the present application, due to the second active layer and the second layer Between dielectric layer by being formed with a patterning processes, therefore compared to the relevant technologies, the manufacturing process of the display base plate can subtract Few patterning processes, simplify the manufacturing process of display base plate, reduce manufacturing cost.
Optionally, the shape of the second gate insulation layer and the shape of second grid are identical, the second active layer, the second gate insulation layer It is sequentially overlapped with second grid, the second interlayer dielectric layer covers the upper table of the second gate insulation layer, second grid and the second active layer The partial region in face, the region not covered by the second interlayer dielectric layer in the upper surface of the second active layer be for it is to be formed The step surface of first source electrode and the first drain electrode overlapped step structure.
Optionally, step 403 includes:
Photoresist layer is formed in inter-level dielectric material layers；
The underlay substrate for being formed with photoresist layer is successively exposed, developed and etched, what is be sequentially overlapped is initial Interlayer dielectric layer and photoetching offset plate figure, the shape of initial interlayer dielectric layer and the shape of photoetching offset plate figure are identical；
It in active layer material layers, is not performed etching by the region that initial interlayer dielectric layer covers, obtains the second active layer；
Photoetching offset plate figure is ashed, the region to be etched of initial interlayer dielectric layer is exposed；
The region to be etched of initial interlayer dielectric layer is performed etching, the second interlayer dielectric layer is obtained, it is active to expose second For the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure on layer；
Remove remaining photoresist.
Optionally, after step 403, this method further include:
By a patterning processes on the first interlayer dielectric layer and multiple first mistakes are respectively formed on the first gate insulation layer Hole, multiple first via holes on the first interlayer dielectric layer are connected to multiple first via holes one-to-one correspondence on the first gate insulation layer；
The first source-drain electrode layer, passivation layer, first flat is sequentially formed on the underlay substrate for being formed with the second interlayer dielectric layer Smooth layer, the second source-drain electrode layer and the second flatness layer；
Wherein, display base plate has multiple display units, and in each display unit, the first source-drain electrode layer includes two the One source electrode and one first drain electrode, the second source-drain electrode layer include that the second source electrode and second drain, one in two the first source electrodes One end of first source electrode and the first drain electrode is overlapped on respectively on the step structure of the second active layer, another in two the first source electrodes A first source electrode and the other end of the first drain electrode pass through one group of first via hole respectively and connect with the first active layer, every group of first via hole Including in second buffer layer and coconnected two the first via holes of the first interlayer dielectric layer, on passivation layer and on the first flatness layer point It is not formed with multiple second via holes, multiple second via holes on passivation layer and multiple second via holes on the first flatness layer one are a pair of It should be connected to, the second source electrode is connect by one group of second via hole with the first source electrode, and the second drain electrode passes through one group of second via hole and first Drain electrode connection, every group of second via hole include on the first flatness layer and coconnected two the second via holes of passivation layer.
Optionally, sequentially formed on the underlay substrate for being formed with the second interlayer dielectric layer the first source-drain electrode layer, passivation layer, After first flatness layer, the second source-drain electrode layer and the second flatness layer, this method further include:
Sequentially form anode, pixel defining layer and spacer layer on the underlay substrate for being formed with the second flatness layer, second Third via hole is formed on flatness layer, anode is connected by third via hole and the second drain electrode.
Optionally, before step 401, this method further include:
Flexible base layer, barrier layer and first buffer layer are sequentially formed on underlay substrate；
Step 401 includes: that the first active layer, the first grid are sequentially formed on the underlay substrate for be formed with first buffer layer is exhausted Edge layer, first grid and the first interlayer dielectric layer.
Optionally, before step 402, this method further include:
Second buffer layer is formed on the underlay substrate for being formed with the first interlayer dielectric layer；
Step 402 includes: that active layer material layers, second gate are sequentially formed on the underlay substrate for be formed with second buffer layer Insulating layer, second grid and inter-level dielectric material layers；
By a patterning processes on the first interlayer dielectric layer and multiple first mistakes are respectively formed on the first gate insulation layer Hole, multiple first via holes on the first interlayer dielectric layer are connected to multiple first via holes one-to-one correspondence on the first gate insulation layer, Include:
Shape is distinguished in second buffer layer, on the first interlayer dielectric layer and on the first gate insulation layer by a patterning processes At multiple first via holes, multiple first via holes on multiple first via holes, the first interlayer dielectric layer in second buffer layer and Multiple first via holes on first gate insulation layer correspond connection；
Wherein, another first source electrode and the other end of the first drain electrode pass through one group of first via hole and the first active layer respectively Connection, every group of first via hole include in second buffer layer, on the first interlayer dielectric layer and the first gate insulation layer coconnected three First via hole.
Optionally, the first active layer is polysilicon active layer, and the second active layer is oxide active layer, and this method is also wrapped It includes: forming light shield layer on the underlay substrate for being formed with the first gate insulation layer, light shield layer is arranged and passes through with first grid same layer It is formed with a patterning processes, orthographic projection of second active layer on underlay substrate is located at positive throwing of the light shield layer on underlay substrate In the domain of shadow zone.
All the above alternatives can form the alternative embodiment of the application, herein no longer using any combination It repeats one by one.
Referring to FIG. 5, it illustrates the method streams of the manufacturing method of another display base plate provided by the embodiments of the present application Cheng Tu, the manufacturing method of the display base plate can be used for manufacturing Fig. 2 or display base plate shown in Fig. 3.The present embodiment is to manufacture Fig. 3 Shown in be illustrated for display base plate.Referring to Fig. 5, this method comprises:
Step 501 sequentially forms flexible base layer, barrier layer and first buffer layer on underlay substrate.
Referring to FIG. 6, it illustrates one kind provided by the embodiments of the present application to sequentially form flexible base on underlay substrate 201 Schematic diagram after bottom 210, barrier layer 211 and first buffer layer 212, underlay substrate 201 can be transparent substrate, can be Using substrate made of the leaded light with certain robustness such as glass, quartz or transparent resin and nonmetallic materials, flexible substrates Layer 210 can be PI layer, the forming material of both barrier layer 211 and first buffer layer 212 all can be SiOx it is (Chinese: oxygen SiClx), SiNx (Chinese: silicon nitride), Al2O3The inorganic material such as (Chinese: aluminium oxide) or SiOxNx (Chinese: silicon oxynitride), and The forming material of the forming material on barrier layer 211 and first buffer layer 212 can be identical or different.
Optionally, firstly, coating one layer of PI on underlay substrate 201 as flexible base layer 210；Later, by coating, Magnetron sputtering, thermal evaporation or plasma enhanced chemical vapor deposition method (English: Plasma Enhanced Chemical Vapor Deposition；The methods of referred to as: PECVD) one is deposited on the underlay substrate 201 for being formed with flexible base layer 210 Layer SiOx is as barrier layer 211；Finally, being formed with barrier layer by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of Al is deposited on 211 underlay substrate 2012O3As first buffer layer 212.
Step 502 sequentially forms the first active layer and the first gate insulation on the underlay substrate for be formed with first buffer layer Layer.
Referring to FIG. 7, it illustrates provided by the embodiments of the present application a kind of in the substrate base for being formed with first buffer layer 212 Schematic diagram after sequentially forming the first active layer 202 and the first gate insulation layer 203 on plate 201, the first active layer 202 can be non- Crystal silicon active layer, for example, the first active layer 202 is LTPS active layer, the forming material of the first gate insulation layer 203 can be SiOx、SiNx、Al2O3Or the inorganic material such as SiOxNx.
Optionally, firstly, being formed with first buffer layer by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of amorphous silicon (referred to as: a-si) is deposited on 212 underlay substrate 201, obtains amorphous silicon layer, and then, amorphous silicon layer is carried out Annealing makes amorphous silicon be converted into polysilicon, later, is handled by a patterning processes the amorphous silicon layer after annealing, The first active layer 202 is obtained, finally, by the methods of coating, magnetron sputtering, thermal evaporation or PECVD to be formed with first active Deposition layer of sin x is as the first gate insulation layer 203 on the underlay substrate 201 of layer 202.
Wherein, a patterning processes include photoresist coating, exposure, development, etching and photoresist lift off, pass through a structure Figure technique handles the amorphous silicon layer after annealing, obtains the first active layer 202, comprising: on amorphous silicon layer after annealing It coats a layer photoresist and obtains photoresist layer, photoresist layer is exposed using mask plate, photoresist layer is made to form complete exposure Light area and non-exposed area are handled by developing process later, are completely removed the photoresist of complete exposure region, non-exposed area Photoresist all retains, and is performed etching using etching technics to the corresponding region of exposure region complete on the amorphous silicon layer after annealing, It is finally peeled away the photoresist of non-exposed area, region corresponding with non-exposed area is the first active layer on the amorphous silicon layer after annealing 202.It should be noted that the embodiment of the present application is illustrated for forming the first active layer 202 using positive photoresist, also First active layer 202 can be formed using negative photoresist, the embodiment of the present application does not limit this.
Step 503 forms first grid and light shield layer on the underlay substrate for being formed with the first gate insulation layer.
Referring to FIG. 8, it illustrates provided by the embodiments of the present application a kind of in the substrate for being formed with the first gate insulation layer 203 The schematic diagram after first grid 204 and light shield layer 213, first grid 204 and the setting of 213 same layer of light shield layer are formed on substrate 201, First grid 204 and light shield layer 213 with a patterning processes by forming, to simplify the manufacturing process of display base plate.Wherein, The forming material of one grid 204 can be metal Mo (Chinese: molybdenum), Ni metal (Chinese: copper), metal Al (Chinese: aluminium), metal Ti (Chinese: titanium) and its alloy material.
Optionally, firstly, being formed with the first gate insulation layer by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of metal Mo is deposited on 203 underlay substrate 201, metal Mo material layers is obtained, then, by a patterning processes to metal Mo material layers are handled to obtain first grid 204 and light shield layer 213.Metal Mo material layers are carried out by a patterning processes The process of processing can be with reference to the process that step 502 is handled the amorphous silicon layer after annealing by a patterning processes, this Details are not described herein for embodiment.
Step 504, sequentially formed on the underlay substrate for being formed with first grid and light shield layer the first interlayer dielectric layer and Second buffer layer.
Referring to FIG. 9, it illustrates one kind provided by the embodiments of the present application to be formed with first grid 204 and light shield layer Schematic diagram after sequentially forming the first interlayer dielectric layer 205 and second buffer layer 214 on 213 underlay substrate 201, the first interlayer The forming material of both dielectric layer 205 and second buffer layer 214 all can be SiOx, SiNx, Al2O3Or SiOxNx etc. is inorganic Material, the forming material of the first interlayer dielectric layer 205 and the forming material of second buffer layer 214 can be identical or different.
Optionally, firstly, being formed with first grid 204 by the methods of coating, magnetron sputtering, thermal evaporation or PECVD With one layer of SiOxNx of deposition on the underlay substrate 201 of light shield layer 213 as the first interlayer dielectric layer 205；Later, by coating, The methods of magnetron sputtering, thermal evaporation or PECVD deposit on the underlay substrate 201 for being formed with first grid 204 and light shield layer 213 One layer of SiOx is as second buffer layer 214.
Step 505 sequentially forms active layer material layers, the second gate insulation on the underlay substrate for be formed with second buffer layer Layer, second grid and inter-level dielectric material layers.
Referring to FIG. 10, it illustrates provided by the embodiments of the present application a kind of in the substrate for being formed with second buffer layer 214 After sequentially forming active layer material layers X, the second gate insulation layer 207, second grid 208 and inter-level dielectric material layers Y on substrate 201 Schematic diagram, the second gate insulation layer 207 and second grid 208 be sequentially overlapped, the shape and second grid of the second gate insulation layer 207 208 shape is identical.The forming material of active layer material layers X can be the oxides such as IGZO or ITZO, the second gate insulation layer 207 Forming material with both inter-level dielectric material layers Y all can be SiOx, SiNx, Al2O3Or the inorganic material such as SiOxNx, and The forming material of second gate insulation layer 207 and the forming material of inter-level dielectric material layers Y can be identical or different, second grid 208 forming material can be metal Mo, Ni metal, metal Al, metal Ti and its alloy material.
Optionally, firstly, being formed with second buffer layer by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of IGZO is deposited on 214 underlay substrate 201 as active layer material layers X；Then, in the lining for forming active layer material layers X The second gate insulation layer 207 and second grid 208 are formed on substrate 201；Finally, by coating, magnetron sputtering, thermal evaporation or The methods of PECVD forms one layer of SiOx of deposition as inter-level dielectric material on the underlay substrate 201 for be formed with second grid 208 Layer Y.
Wherein, the second gate insulation layer 207 and second grid are formed on the underlay substrate 201 for forming active layer material layers X 208, comprising: by the methods of coating, magnetron sputtering, thermal evaporation or PECVD in the underlay substrate for forming active layer material layers X SiNx and metal Mo are sequentially depositing on 201, the SiNx material layers and metal Mo material layers being sequentially overlapped, then by primary Patterning processes are handled to obtain the second gate insulation layer 207 and second grid 208 to SiNx material layers and metal Mo material layers.Its In, it can be with reference in step 502 by the process that a patterning processes handle SiNx material layers and metal Mo material layers The process handled by a patterning processes the amorphous silicon layer after annealing, details are not described herein for the present embodiment.
Step 506 is handled active layer material layers and inter-level dielectric material layers by a patterning processes, obtains Two active layers and the second interlayer dielectric layer.
Figure 11 is please referred to, it illustrates one kind provided by the embodiments of the present application by a patterning processes to active layer material The method flow diagram that layer and inter-level dielectric material layers are handled, referring to Figure 11, this method comprises:
Sub-step 5061 forms photoresist layer in inter-level dielectric material layers.
Figure 12 is please referred to, it illustrates one kind provided by the embodiments of the present application to form photoetching on inter-level dielectric material layers Y Schematic diagram after glue-line Z can form photoresist layer Z by coating processes on inter-level dielectric material layers Y.
Sub-step 5062 is successively exposed, develops and etches to the underlay substrate for being formed with photoresist layer, obtains successively The initial interlayer dielectric layer and photoetching offset plate figure of superposition, the shape of initial interlayer dielectric layer and the shape of photoetching offset plate figure are identical.
Figure 13 is please referred to, it illustrates provided by the embodiments of the present application a kind of to the underlay substrate for being formed with photoresist layer Z 201 be successively exposed, develop and etch after schematic diagram, initial interlayer dielectric layer Y1 and photoetching offset plate figure Z1 be sequentially overlapped, The shape of initial interlayer dielectric layer Y1 is identical as the shape of photoetching offset plate figure Z1, the thickness phase of all areas of photoetching offset plate figure Z1 Deng.Optionally, firstly, being exposed by exposure technology to photoresist layer Z, keep photoresist layer Z-shaped into complete exposure region and non- Exposure region handles the photoresist layer Z after exposure by developing process, goes the photoresist of complete exposure region completely later It removes, the photoresist of non-exposed area all retains, finally, by etching technics to complete exposure region pair on inter-level dielectric material layers Y The region answered performs etching.
Sub-step 5063, in active layer material layers, do not performed etching, obtain by the region that initial interlayer dielectric layer covers Second active layer.
Figure 14 is please referred to, it illustrates on a kind of pair of active layer material layers X provided by the embodiments of the present application, not by initiation layer Between dielectric layer Y1 cover region perform etching after schematic diagram, it is active to obtain second after performing etching to active layer material layers X Layer 206, the second active layer 206 is located at positive throwing of the light shield layer 213 on underlay substrate 201 in the orthographic projection on underlay substrate 201 In the domain of shadow zone, so, light shield layer 213 can be blocked the second active layer 206, avoid illumination to the second active layer 206 influence, to avoid influence of the illumination to the switching characteristic of the TFT where the second active layer 206.
It should be noted that the embodiment of the present application is mask plate (mask) to active layer material using initial interlayer dielectric layer Y1 Layer X performs etching to obtain the second active layer 206, is carried out by a patterning processes to active layer material layers compared to the relevant technologies Processing obtains the second active layer, and scheme provided by the embodiments of the present application can save photoresist coating processes, a single exposure Technique, a developing process and a photoresist stripping process, therefore can simplify the manufacturing process of the second active layer 206, from And simplify the manufacturing process of display base plate.
Sub-step 5064 is ashed photoetching offset plate figure, exposes the region to be etched of initial interlayer dielectric layer.
Figure 15 is please referred to, showing after being ashed it illustrates a kind of couple of photoetching offset plate figure Z1 provided by the embodiments of the present application It is intended to, photoetching offset plate figure Z1 can be ashed using oxygen and sulfur hexafluoride gas, reduce photoetching offset plate figure Z1, exposed The region to be etched (not marking in Figure 15) of initial interlayer dielectric layer Y1, the shape of photoetching offset plate figure Z1 change to obtain photoresist figure Shape Z2.
Sub-step 5065 performs etching the region to be etched of initial interlayer dielectric layer, obtains the second interlayer dielectric layer, dew Out for the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure on the second active layer.
Figure 16 is please referred to, it illustrates a kind of areas to be etched to initial interlayer dielectric layer Y1 provided by the embodiments of the present application Domain perform etching after schematic diagram, obtain the second interlayer dielectric layer 209 after etching, on the second active layer 206 for to shape At the first source electrode (being not shown in Figure 16) and the step surface of first drain electrode (being not shown in Figure 16) overlapped step structure expose.
Sub-step 5066, the remaining photoresist of removing.
Figure 17 is please referred to, it illustrates a kind of schematic diagram removed after remaining photoresist provided by the embodiments of the present application, After removing remaining photoresist, the second active layer 206, the second gate insulation layer 207 and second grid 208 are sequentially overlapped, the second layer Between dielectric layer 209 cover the second gate insulation layer 207, second grid 208 and the second active layer 206 upper surface partial region.
It should be noted that the second active layer and the process of the second interlayer dielectric layer shown in fig. 6 of being formed is only example Property, in practical application, in the process for forming the second active layer and the second interlayer dielectric layer, it can be carried out using half-exposure technique Processing.To which above-mentioned sub-step 5061 to sub-step 5066 can be replaced using following sub-step 5061a to sub-step 5066a:
Sub-step 5061a, photoresist layer is formed in inter-level dielectric material layers.
Sub-step 5062a, half-exposure, development and etching are successively carried out to the underlay substrate for being formed with photoresist layer, obtained The initial interlayer dielectric layer and photoetching offset plate figure being sequentially overlapped, photoetching offset plate figure include the first photoresist area and the second photoresist Area, the thickness in the first photoresist area less than the second photoresist area thickness, the first photoresist area and initial interlayer dielectric layer to Etch areas is corresponding.
It is alternatively possible to carry out half-exposure to the underlay substrate for being formed with photoresist layer using intermediate tone mask version.
Sub-step 5063a, in active layer material layers, do not performed etching, obtain by the region that initial interlayer dielectric layer covers To the second active layer.
Sub-step 5064a, the photoresist for removing the first photoresist area, expose the region to be etched of initial interlayer dielectric layer.
It is alternatively possible to remove the photoresist in the first photoresist area using techniques such as development, removing or ashing.
Sub-step 5065a, the region to be etched of initial interlayer dielectric layer is performed etching, obtains the second interlayer dielectric layer, Expose on the second active layer for the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure.
Sub-step 5066a, the photoresist for removing the second photoresist area.
The realization process of sub-step 5061a to sub-step 5066a can with reference to sub-step 5061 to sub-step 5066 with And the relevant technologies, details are not described herein for the embodiment of the present application.
Step 508, by a patterning processes in second buffer layer, on the first interlayer dielectric layer and the first gate insulation layer On be respectively formed multiple first via holes, multiple first on multiple first via holes, the first interlayer dielectric layer in second buffer layer Multiple first via holes on via hole and the first gate insulation layer correspond connection.
Figure 18 is please referred to, it illustrates one kind provided by the embodiments of the present application by a patterning processes in second buffer layer It is respectively formed the schematic diagram after multiple first via holes on 214, on the first interlayer dielectric layer 205 and on the first gate insulation layer 203, Multiple first via holes and the first gate insulation layer on multiple first via holes, the first interlayer dielectric layer 205 on two buffer layers 214 Multiple first via holes on 203 correspond connection and form the first via hole of multiple groups K1, and every group of first via hole K1 includes the second buffering On layer 214, on the first interlayer dielectric layer 205 and coconnected three the first via holes of the first gate insulation layer 203.As shown in figure 18, During forming the first via hole, the connection being connected to is formed on the first interlayer dielectric layer 205 also in second buffer layer 214 Hole K2, the region EB of second buffer layer 214, the region EB of the first interlayer dielectric layer 205, the first gate insulation layer 203 the area EB Domain forms the EB via hole K3 being connected to the region EB of first buffer layer 212.Wherein, there is display base plate the region EB to be bent over, the Two buffer layers 214, the first interlayer dielectric layer 205, the first gate insulation layer 203 and any film layer in first buffer layer 212 ED Region is corresponding region of the region EB of display base plate in any film layer.The first via hole is formed by a patterning processes Process can be with reference to the process handled by a patterning processes the amorphous silicon layer after annealing in step 502, this implementation Details are not described herein for example.
Step 509 sequentially forms the first source-drain electrode layer, passivation on the underlay substrate for being formed with the second interlayer dielectric layer Layer, the first flatness layer, the second source-drain electrode layer and the second flatness layer.
Figure 19 is please referred to, a kind of is being formed with the second interlayer dielectric layer 209 it illustrates provided by the embodiments of the present application The first source-drain electrode layer 215, passivation layer 216, the first flatness layer 217, the second source-drain electrode layer 218 are sequentially formed on underlay substrate 201 With the schematic diagram after the second flatness layer 219, referring to Figure 18 and Figure 19, the first source-drain electrode layer 215 includes two the first source electrodes 2151 With one first drain electrode 2152, one end point of one first source electrode 2151 and the first drain electrode 2152 in two the first source electrodes 2151 It is not overlapped on the step structure of the second active layer 206, another first source electrode 2151 in two the first source electrodes 2151 and The other end of one drain electrode 2152 passes through one group of first via hole K1 respectively and connect with the first active layer 202, and the first drain electrode 2152 passes through Connecting hole K2 is connect with light shield layer 213.Second source-drain electrode layer 218 includes the second source electrode 2181, second drain electrode 2182 and source-drain electrode Lead 2183 is respectively formed with multiple second via holes (not marking in Figure 19) on passivation layer 216 and on the first flatness layer 217, blunt Multiple second via holes changed on layer 216 are connected to multiple second via holes one-to-one correspondence on the first flatness layer 217, the second source electrode 2181 are connect by one group of second via hole with another described first source electrode 2151, and the second drain electrode 2182 passes through one group of second via hole 2052 connect with the first drain electrode, every group of second via hole include on the first flatness layer 217 with passivation layer 216 coconnected two second Via hole.In addition, as shown in figure 19, the region EB of passivation layer 216 is formed with EB via hole, the EB via hole and second on passivation layer 216 EB via hole connection on buffer layer 214, the part that the first flatness layer 217 is located in the region EB is filled in interconnected all EB In via hole.The region EB of passivation layer 216 is corresponding region of the region EB of display base plate on passivation layer 216.
Optionally, the forming material of both the first source-drain electrode layer 215 and second source-drain electrode layer 218 all can be metal Mo, Ni metal, metal Al, metal Ti and its alloy material, the forming material of the first source-drain electrode layer 215 and the second source-drain electrode layer 218 forming material can be identical or different, the shape of 219 this three of passivation layer 216, the first flatness layer 217 and the second flatness layer It all can be organic resin at material.The first source is sequentially formed on the underlay substrate 201 for being formed with the second interlayer dielectric layer 209 Drain electrode layer 215, passivation layer 216, the first flatness layer 217, the second source-drain electrode layer 218 and the second flatness layer 219 may include following Step:
Step (1) is being formed with the second interlayer dielectric layer by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of metal Al is deposited on 209 underlay substrate 201, obtains metal Al material layers, then by a patterning processes to metal Al material layers are handled to obtain the first source-drain electrode layer 215.
Step (2) is being formed with the first source-drain electrode layer 215 by the methods of coating, magnetron sputtering, thermal evaporation or PECVD Underlay substrate 201 on deposition one layer of organic resin as passivation layer 216, then pass through a patterning processes to passivation layer 216 It is handled, to form EB via hole on passivation layer 216.
Step (3), by the methods of coating, magnetron sputtering, thermal evaporation or PECVD in the substrate for being formed with passivation layer 216 One layer of organic resin is deposited on substrate 201 as the first flatness layer 217.
Step (4) is being formed with the first flatness layer 217 by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of metal Ti is deposited on underlay substrate 201, obtains metal Ti material layers, then by a patterning processes to metal Ti material Layer is handled to obtain the second source-drain electrode layer 218.
Step (5) is being formed with the second source-drain electrode layer 218 by the methods of coating, magnetron sputtering, thermal evaporation or PECVD Underlay substrate 201 on deposition one layer of organic resin as the second flatness layer 219.
Step 510 sequentially forms anode, pixel defining layer and spacer material on the underlay substrate for being formed with the second flatness layer Layer, third via hole is formed on the second flatness layer, anode is connected by third via hole and the second drain electrode.
Sequentially formed on the underlay substrate 201 for being formed with the second flatness layer 219 anode 220, pixel defining layer 221 and every Schematic diagram after underbed layer 222 can refer to Fig. 3, be formed with third via hole (not marking in Fig. 3) on the second flatness layer 219, sun Pole 220 is connect by third via hole with the second drain electrode 2182.
Optionally, the forming material of anode can be tin indium oxide (English: Indium tin oxide；Referred to as: ITO), Indium zinc oxide (English: Indium zinc oxide；Referred to as: IZO) or Al-Doped ZnO is (English: aluminum-doped zinc oxide；Referred to as: ZnO:Al), the forming material of both pixel defining layer 221 and spacer layer 222 all can be have Machine resin.Sequentially formed on the underlay substrate 201 for being formed with the second flatness layer 217 anode 220, pixel defining layer 221 and every Underbed layer 222 may comprise steps of:
Step (1) is being formed with the second flatness layer 217 by the methods of coating, magnetron sputtering, thermal evaporation or PECVD On underlay substrate 201 deposit one layer of ITO, obtain ITO material layers, then by a patterning processes to ITO material layers at Reason obtains anode 220.
Step (2), by the methods of coating, magnetron sputtering, thermal evaporation or PECVD in the substrate base for being formed with anode 220 On plate 201 deposit one layer of organic resin, obtain organic material layer, then by a patterning processes to organic material layer at Reason obtains pixel defining layer 221.
Step (3) is being formed with pixel defining layer 221 by the methods of coating, magnetron sputtering, thermal evaporation or PECVD One layer of organic resin is deposited on underlay substrate 201, obtains organic material layer, then by a patterning processes to organic material layer It is handled to obtain spacer layer 222.
It should be noted that the sequencing of the manufacturing method step of display base plate provided by the embodiments of the present application can be into Row appropriate adjustment, step according to circumstances can also accordingly be increased and decreased, and anyone skilled in the art is in this Shen In the technical scope that please be disclosed, the method that can readily occur in variation should all cover within the scope of protection of this application, therefore not It repeats again.
In conclusion the manufacturing method of display base plate provided by the embodiments of the present application, due to the second active layer and the second layer Between dielectric layer by being formed with a patterning processes, therefore compared to the relevant technologies, the manufacturing process of the display base plate can subtract Few patterning processes, simplify the manufacturing process of display base plate, reduce manufacturing cost.
Further, since the second interlayer dielectric layer covers the upper of the second gate insulation layer, second grid and the second active layer The partial region on surface, therefore the area of the second interlayer dielectric layer is smaller, the area of the second interlayer dielectric layer in the related technology Larger, the area of the second interlayer dielectric layer in the embodiment of the present application is smaller, the second interlayer dielectric layer in the embodiment of the present application It is equivalent to and the second interlayer dielectric layer in the related technology is patterned, the second interlayer in the embodiment of the present application is situated between Matter layer, which is equivalent to, discharges the stress of the second interlayer dielectric layer in the related technology, therefore the second interlayer of the application is situated between The stress of matter layer is smaller, and the stress of the second interlayer dielectric layer is relatively easy to control, and avoids the warpage of display base plate, and display base plate can be more Good is higher applied to products, the yields of display base plate such as flexible foldables.Further, since the second layer in the embodiment of the present application Between dielectric layer be equivalent to the second interlayer dielectric layer in the related technology patterned, relative to the relevant technologies, this Application embodiment can simplify the film layer structure of display base plate.
The embodiment of the present application also provides a kind of display device, which includes display base provided by the above embodiment Plate.The display device can be comprehensive screen display device, for example, the display device can be the wearable devices such as wrist-watch, bracelet, Alternatively, the display device can be the mobile terminals such as mobile phone or tablet computer, alternatively, the display device can be television set, show Show any products or components having a display function such as device, laptop, Digital Frame or navigator.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely the alternative embodiments of the application, not to limit the application, it is all in spirit herein and Within principle, any modification, equivalent replacement, improvement and so on be should be included within the scope of protection of this application.

Claims (10)

1. a kind of manufacturing method of display base plate, which is characterized in that the described method includes:
The first active layer, the first gate insulation layer, first grid and the first interlayer dielectric layer are sequentially formed on underlay substrate；
Sequentially formed on the underlay substrate for being formed with first interlayer dielectric layer active layer material layers, the second gate insulation layer, Second grid and inter-level dielectric material layers；
The active layer material layers and the inter-level dielectric material layers are handled by a patterning processes, obtaining second has Active layer and the second interlayer dielectric layer.
2. the method according to claim 1, wherein
The shape of second gate insulation layer is identical as the shape of the second grid, second active layer, the second gate Insulating layer and the second grid are sequentially overlapped, and second interlayer dielectric layer covers second gate insulation layer, described second The partial region of the upper surface of grid and second active layer, not by the second layer in the upper surface of second active layer Between the region that covers of dielectric layer be for the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure.
3. according to the method described in claim 2, it is characterized in that,
It is described that the active layer material layers and the inter-level dielectric material layers are handled by a patterning processes, obtain Two active layers and the second interlayer dielectric layer, comprising:
Photoresist layer is formed in the inter-level dielectric material layers；
The underlay substrate for being formed with the photoresist layer is successively exposed, developed and etched, what is be sequentially overlapped is initial The shape of interlayer dielectric layer and photoetching offset plate figure, the initial interlayer dielectric layer is identical as the shape of the photoetching offset plate figure；
It in the active layer material layers, is not performed etching by the region that the initial interlayer dielectric layer covers, obtains described the Two active layers；
The photoetching offset plate figure is ashed, the region to be etched of the initial interlayer dielectric layer is exposed；
The region to be etched of the initial interlayer dielectric layer is performed etching, the second interlayer dielectric layer is obtained, exposes described second For the step surface with the first source electrode to be formed and the first drain electrode overlapped step structure on active layer；
Remove remaining photoresist.
4. the method according to claim 1, wherein
The active layer material layers and the inter-level dielectric material layers are being handled by a patterning processes, are obtaining second After active layer and the second interlayer dielectric layer, the method also includes:
Multiple the are respectively formed on first interlayer dielectric layer and on first gate insulation layer by a patterning processes One via hole, multiple first via holes one on multiple first via holes and first gate insulation layer on first interlayer dielectric layer One corresponding connection；
The first source-drain electrode layer, passivation layer, first flat is sequentially formed on the underlay substrate for being formed with second interlayer dielectric layer Smooth layer, the second source-drain electrode layer and the second flatness layer；
Wherein, the display base plate has multiple display units, and in each display unit, the first source-drain electrode layer includes two A first source electrode and one first drain electrode, the second source-drain electrode layer include that the second source electrode and second drain, and described two first One end of first source electrode and first drain electrode in source electrode is overlapped on respectively on the step structure of second active layer, Another first source electrode in described two first source electrodes and the other end of first drain electrode pass through one group respectively described in first Via hole is connect with first active layer, and the first via hole described in every group includes being situated between in the second buffer layer with first interlayer Matter layer coconnected two the first via hole is respectively formed with multiple second mistakes on the passivation layer and on first flatness layer Hole, multiple second via holes on the passivation layer are connected to multiple second via holes one-to-one correspondence on first flatness layer, institute It states the second source electrode to connect by the second via hole described in one group with another described first source electrode, second drain electrode passes through one group of institute It states the second via hole and first drain electrode connects, the second via hole described in every group includes on first flatness layer and the passivation layer Coconnected two the second via holes.
5. according to the method described in claim 4, it is characterized in that,
The first source-drain electrode layer, passivation layer, first flat is sequentially formed on the underlay substrate for being formed with second interlayer dielectric layer After smooth layer, the second source-drain electrode layer and the second flatness layer, the method also includes:
Anode, pixel defining layer and spacer layer are sequentially formed on the underlay substrate for being formed with second flatness layer, it is described Third via hole is formed on second flatness layer, the anode is connected by the third via hole and second drain electrode.
6. the method according to claim 1, wherein
Before sequentially forming the first active layer, the first gate insulation layer, first grid and the first interlayer dielectric layer on underlay substrate, The method also includes:
Flexible base layer, barrier layer and first buffer layer are sequentially formed on underlay substrate；
The first active layer, the first gate insulation layer, first grid and the first interlayer dielectric layer are sequentially formed on the underlay substrate, are wrapped It includes:
The first active layer, the first gate insulation layer, the first grid are sequentially formed on the underlay substrate for being formed with the first buffer layer Pole and the first interlayer dielectric layer.
7. according to the method described in claim 4, it is characterized in that,
Sequentially formed on the underlay substrate for being formed with first interlayer dielectric layer active layer material layers, the second gate insulation layer, Before second grid and inter-level dielectric material layers, the method also includes:
Second buffer layer is formed on the underlay substrate for being formed with first interlayer dielectric layer；
It is described that active layer material layers, the second gate insulation are sequentially formed on the underlay substrate for being formed with first interlayer dielectric layer Layer, second grid and inter-level dielectric material layers, comprising:
Active layer material layers, the second gate insulation layer, second are sequentially formed on the underlay substrate for being formed with the second buffer layer Grid and inter-level dielectric material layers；
It is described by a patterning processes on first interlayer dielectric layer and first gate insulation layer on be respectively formed it is more A first via hole, multiple first mistakes on multiple first via holes and first gate insulation layer on first interlayer dielectric layer Hole corresponds connection, comprising:
Through a patterning processes in the second buffer layer, on first interlayer dielectric layer and first gate insulation layer On be respectively formed multiple first via holes, on multiple first via holes, first interlayer dielectric layer in the second buffer layer Multiple first via holes on multiple first via holes and first gate insulation layer correspond connection；
Wherein, another described first source electrode and it is described first drain electrode the other end pass through one group respectively described in the first via hole and institute State the connection of the first active layer, the first via hole described in every group includes in the second buffer layer, on first interlayer dielectric layer and Coconnected three first via holes of first gate insulation layer.
8. method according to any one of claims 1 to 7, which is characterized in that first active layer is polysilicon active layer, Second active layer is oxide active layer, the method also includes:
Light shield layer is formed on the underlay substrate for being formed with first gate insulation layer, the light shield layer and the first grid are same Layer is arranged and by being formed with a patterning processes, and orthographic projection of second active layer on the underlay substrate is located at described Light shield layer is in the orthographic projection region on the underlay substrate.
9. a kind of display base plate, which is characterized in that the display base plate includes: underlay substrate, and, it is arranged in the substrate base The first active layer, the first gate insulation layer, first grid, the first interlayer dielectric layer, the second active layer, the second gate insulation on plate Layer, second grid and the second interlayer dielectric layer, the shape of second gate insulation layer is identical as the shape of the second grid, institute It states the second active layer, second gate insulation layer and the second grid to be sequentially overlapped, second interlayer dielectric layer covers institute State the partial region of the upper surface of the second gate insulation layer, the second grid and second active layer, second active layer Upper surface in not by second interlayer dielectric layer cover region be for the first source electrode to be formed and first drain The step surface of overlapped step structure.
10. a kind of display device, which is characterized in that the display device includes display base plate as claimed in claim 9.
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