CN109728001A - A kind of array substrate and preparation method thereof, display panel - Google Patents
A kind of array substrate and preparation method thereof, display panel Download PDFInfo
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- CN109728001A CN109728001A CN201910002739.9A CN201910002739A CN109728001A CN 109728001 A CN109728001 A CN 109728001A CN 201910002739 A CN201910002739 A CN 201910002739A CN 109728001 A CN109728001 A CN 109728001A
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Abstract
The embodiment of the present invention provides a kind of array substrate and preparation method thereof, display panel, is related to field of display technology, can reduce the preparation flow of array substrate, saves the preparation cost of array substrate.A kind of array substrate, including substrate, the light-shielding pattern that thin film transistor (TFT), grid line and data line over the substrate is arranged and is set between the thin film transistor (TFT) and the substrate；The thin film transistor (TFT) includes first grid, source electrode and drain electrode, and the first grid, the source electrode, the drain electrode and the same material of data line same layer；The drain electrode is electrically connected with the data line；The grid line and the same material of light-shielding pattern same layer, the grid line are electrically connected with the first grid.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and preparation method thereof, display panel.
Background technique
With the development of display technology, display panel is just becoming one of the direction of mainstream development, whether LCD display
Plate or organic electroluminescent display panel (Organic Light-Emitting Diode, abbreviation OLED) include array base
Plate is provided with thin film transistor (TFT) in array substrate, and thin film transistor (TFT) includes active layer.
However, active layer is when illuminated, it is easy to influence thin film transistor (TFT) (Thin Film Transistor, abbreviation
TFT) performance.
In order to realize more stable TFT performance generally light shield layer can be arranged close to one side of substrate in active layer in the prior art,
To shut out the light.But increases by one layer of light shield layer, while will increase the preparation flow of array substrate, increase being prepared into for array substrate
This.
Summary of the invention
The embodiment of the present invention provides a kind of array substrate and preparation method thereof, display panel, can reduce array substrate
Preparation flow saves the preparation cost of array substrate.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
In a first aspect, a kind of array substrate is provided, including substrate, thin film transistor (TFT), the grid line of setting over the substrate
And data line and the light-shielding pattern being set between the thin film transistor (TFT) and the substrate；The thin film transistor (TFT) includes
First grid, source electrode and drain electrode, and the first grid, the source electrode, the drain electrode and the same material of data line same layer；Institute
Drain electrode is stated to be electrically connected with the data line；The grid line and the same material of light-shielding pattern same layer, the grid line and described first
Grid electrical connection.
It optionally, further include the buffer layer being set between the light-shielding pattern and the thin film transistor (TFT)；Described first
Grid is electrically connected by the first via hole on the buffer layer with the grid line.
Optionally, the thin film transistor (TFT) further includes second grid, and the second grid and the grid line are same layer setting
Integral structure；The first grid is electrically connected with the second grid.
Optionally, the thin film transistor (TFT) further includes the active patterns and gate insulation being cascading over the substrate
Pattern, the active patterns and the gate insulation pattern are set between buffer layer and the first grid；Along the source electrode with
The spacing direction of the drain electrode, the active patterns exceed the gate insulation pattern, and the source electrode and the drain electrode have with described
Source pattern directly contacts.
Further alternative, the source electrode is electrically connected by the second via hole on buffer layer with the light-shielding pattern.
Optionally, the active patterns include channel region, the source area positioned at the channel region two sides and drain region；It is described
The orthographic projection of channel region over the substrate is Chong Die with the orthographic projection of the gate insulation pattern over the substrate；The channel region
Including semiconductor material, the source area and the drain region after carrying out conductor to the semiconductor material by obtaining.
Second aspect provides a kind of display panel, including array substrate described in first aspect.
The third aspect provides a kind of preparation method of array substrate, comprising: is formed on the substrate by a patterning processes
Light-shielding pattern and grid line；Thin film transistor (TFT), the film are formed on the substrate for being formed with the light-shielding pattern and the grid line
Transistor includes first grid, source electrode and drain electrode, and the first grid, the source electrode, the drain electrode and data line pass through same
Secondary patterning processes are formed, and the drain electrode is electrically connected with the data line；Wherein, the first grid is electrically connected with the grid line.
Optionally, after forming light-shielding pattern and grid line, the method also includes: the light-shielding pattern with it is described thin
Form buffer layer between film transistor, the buffer layer includes the first via hole, the first grid by first via hole with
The grid line electrical connection；Wherein, the buffer layer, the active patterns and gate insulation pattern are formed, comprising: over the substrate
The first insulation film, active patterns, the second insulation film are sequentially formed, and deviates from the substrate one in second insulation film
Side forms photoresist；The photoresist is exposed using half-tone mask plate, forms the first photoetching agent pattern, institute after development
Stating the first photoetching agent pattern includes that part is fully retained in photoresist, photoresist half retains part and photoresist completely removes part；
The photoresist be fully retained part it is corresponding with the gate insulation pattern to be formed, the photoresist completely remove partially at least
Corresponding with first via hole to be formed, it is corresponding with other regions that the photoresist half retains part；To second insulation
The part exposed in film and first insulation film carries out first time etching, first insulation film after etching for the first time
The grid line is not leaked out；The photoresist is removed using cineration technics and partly retains part, forms the second photoetching agent pattern；To process
The part exposed in second insulation film and first insulation film of etching for the first time carries out second and etches, with shape
At the gate insulation pattern and the buffer layer；Remove second photoetching agent pattern.
It is further alternative, after forming the gate insulation pattern and the buffer layer, removing second photoresist
Before pattern, the method also includes: conductor processing is carried out to the part exposed in the active patterns.
The embodiment of the present invention provides a kind of array substrate and preparation method thereof, display panel, by making light-shielding pattern and grid
Line, which passes through, to be formed with a patterning processes, makes first grid and source electrode, drain electrode and data line by being formed with a patterning processes,
Simultaneously as grid line and the different layer of data line are arranged, it is therefore not necessary to as in the prior art first grid and source electrode, drain electrode and
Interlayer insulating film is formed between data line, to prevent data line to be electrically connected with grid line, that is, compared to the prior art, the present invention is real
Applying example reduces twice mask plate (mask), and the mask of light-shielding pattern is respectively prepared separately and prepares interlayer insulating film
Mask saves the preparation cost of array substrate to reduce the preparation flow of array substrate.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of schematic top plan view of array substrate provided in an embodiment of the present invention；
Fig. 2 be Fig. 1 in A-A1 to schematic cross-sectional view；
Fig. 3 be Fig. 1 in B-B1 to schematic cross-sectional view；
Fig. 4 is a kind of schematic top plan view of array substrate provided in an embodiment of the present invention；
Fig. 5 is a kind of schematic top plan view of array substrate provided in an embodiment of the present invention；
Fig. 6 is a kind of flow diagram for preparing array substrate provided in an embodiment of the present invention；
Fig. 7 is a kind of process schematic for preparing array substrate provided in an embodiment of the present invention；
Fig. 8 is a kind of process signal for preparing buffer layer, active patterns, gate insulation pattern provided in an embodiment of the present invention
Figure；
Fig. 9 is a kind of process signal for preparing buffer layer, active patterns, gate insulation pattern provided in an embodiment of the present invention
Figure；
Figure 10 is a kind of process signal for preparing buffer layer, active patterns, gate insulation pattern provided in an embodiment of the present invention
Figure；
Figure 11 is a kind of process signal for preparing buffer layer, active patterns, gate insulation pattern provided in an embodiment of the present invention
Figure；
Figure 12 is a kind of process signal for preparing buffer layer, active patterns, gate insulation pattern provided in an embodiment of the present invention
Figure.
Appended drawing reference:
10- substrate；111- light-shielding pattern；112- grid line；113- second grid；12- buffer layer；The first via hole of 121-；
The second via hole of 122-；The first insulation film of 123-；13- active patterns；14- gate insulation pattern；The second insulation film of 141-；151-
Drain electrode；152- source electrode；153- first grid；154- data line；16- pixel defining layer；17- electroluminescent device；171- anode；
172- light emitting functional layer；173- cathode；18- photoresist；The first photoetching agent pattern of 181-；The second photoetching agent pattern of 182-.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of array substrate, as shown in Figure 1-3, include substrate 10, be arranged on substrate 10
Thin film transistor (TFT), grid line 112 and data line 154 and the light-shielding pattern 111 being set between thin film transistor (TFT) and substrate 10；
Thin film transistor (TFT) includes first grid 153, source electrode 152 and drain 151, and first grid 153, source electrode 152,151 sum numbers of drain electrode
According to the same material of 154 same layer of line；Drain electrode 151 is electrically connected with data line 154；Grid line 112 and the same material of 111 same layer of light-shielding pattern, grid
Line 112 is electrically connected with first grid 153.
On this basis, thin film transistor (TFT) further includes active patterns 13.Light-shielding pattern 111 is located at TFT zone, and shading figure
Orthographic projection of the active pattern 13 on substrate 10 is completely covered in the orthographic projection on substrate 10 in case 111, is irradiated to avoid light
On active patterns 13, TFT performance is influenced.
It should be noted that first, first grid 153, source electrode 152, drain electrode 151 and the same material of 154 same layer of data line, tool
Body, first grid 153, source electrode 152, drain electrode 151 and data line 154 with a patterning processes by being prepared.
Second, first grid 153, source electrode 152, drain electrode 151 and the material of data line 154 include conductive material, not to institute
The specific material for stating conductive material is defined, exemplary, first grid 153, source electrode 152, drain electrode 151 and data line 154
Material may include the metal materials such as molybdenum (Mo), copper (Cu), aluminium (Al), also may include tin indium oxide (indium tin
Oxide, abbreviation ITO), the transparent conductive materials such as indium-zinc oxide (Indium zinc oxide, abbreviation IZO).
Third, grid line 112 and the same material of 111 same layer of light-shielding pattern, specifically, grid line 112 and light-shielding pattern 111 pass through together
One time patterning processes are prepared.
4th, grid line 112 and the material of light-shielding pattern 111 should have the function of shading and conduction, therefore, grid line simultaneously
112 for example can be the metal materials such as copper, aluminium with the material of light-shielding pattern 111.
5th, the array substrate can be display array substrate, and it is aobvious that the array substrate can be used for electroluminescent
Show panel, can be used for liquid crystal display panel (Liquid Crystal Display, abbreviation LCD) display panel.Wherein, electric
Photoluminescence display panel is OLED display panel, alternatively, electroluminescence display panel is inorganic EL display panel.
Wherein, when the array substrate is used for electroluminescence display panel, as shown in figure 4, the electroluminance display
Panel further includes electroluminescent device 17 and the pixel defining layer 16 between adjacent electroluminescent device 17, electroluminescent cell
Part 17 includes anode 171, light emitting functional layer 172 and the cathode 173 being cascading, and anode 171 is electrically connected with source electrode 152；
Wherein, electroluminescent device 17 can be top light emitting structure, be also possible to bottom light emitting structure, alternatively, can also be anode 171,
The double-side structure of the equal light-permeable of cathode 173.
The preferred electroluminescent device 17 of the embodiment of the present invention is bottom light emitting structure, alternatively, anode 171, cathode 173 can be saturating
The double-side structure of light, so, light-shielding pattern 111 and grid line 112 are also used as defining the sub-pixel of array substrate
The black matrix in region.
On this basis, when electroluminescent device 17 is bottom light emitting structure or double-side structure, due to light-shielding pattern
111 are located at TFT zone, it will be appreciated by those skilled in the art that, the region where thin film transistor (TFT) cannot be such that light penetrates, because
This, light-shielding pattern 111 will not influence display and use up through array substrate.
6th, as shown in Figure 1-3, thin film transistor (TFT) can be top gate type；As shown in figure 5, thin film transistor (TFT) is also possible to
Double grid type.Wherein, top gate type thin film transistor on-state current with higher (Ion), higher aperture opening ratio and preferably steady
It is qualitative.
Herein, when thin film transistor (TFT) is double grid type, as shown in figure 5, thin film transistor (TFT) further includes second grid 113, it is excellent
It selects second grid 113 and grid line 112 is the integral structure of same layer setting, first grid 153 is electrically connected with second grid 113.
The embodiment of the present invention provides a kind of array substrate, by passing through light-shielding pattern 111 and grid line 112 with a composition
Technique forms, makes first grid 153 with source electrode 152, drain electrode 151 and data line 154 by being formed with a patterning processes, together
When, since grid line 112 and the different layer of data line 154 are arranged, it is therefore not necessary to as in the prior art in first grid 153 and source electrode
152, interlayer insulating film is formed between drain electrode 151 and data line 154, to prevent data line 154 to be electrically connected with grid line 112, that is, phase
Compared with the prior art, the embodiment of the present invention reduces twice mask plate (mask), and light-shielding pattern 111 is respectively prepared separately
The mask and mask for preparing interlayer insulating film saves the preparation of array substrate to reduce the preparation flow of array substrate
Cost.
Optionally, as shown in Fig. 2, array substrate further includes being set to delaying between light-shielding pattern 111 and thin film transistor (TFT)
Rush layer 12；First grid 153 is electrically connected by the first via hole 121 on buffer layer 12 with grid line 112.
Wherein, the material of buffer layer 12 can be silica (SiO2) or organosilicon.
In the embodiment of the present invention, by making first grid 153 only by the first via hole 121 and grid line on buffer layer 12
112 electrical connections are electrically connected by the hole on gate insulation pattern 14 and buffer layer 12 with grid line 112 compared to first grid 153, can
Reduce the complexity and cost of preparation array substrate.
Optionally, as shown in figure 5, thin film transistor (TFT) further includes second grid 113, second grid 113 and grid line 112 are same
The integral structure of layer setting；First grid 153 is electrically connected with second grid 113.
In the embodiment of the present invention, thin film transistor (TFT) can also be double grid type, and on this basis, second grid 113 can be with
Grid line 112 and light-shielding pattern 111 avoid increasing preparation cost by being formed with a patterning processes.
Optionally, as shown in figure 3, thin film transistor (TFT) further includes 13 He of active patterns being cascading on substrate 10
Gate insulation pattern 14, active patterns 13 and gate insulation pattern 14 are set between buffer layer 12 and first grid 153；Along source electrode
152 exceed gate insulation pattern 14 with the spacing direction of drain electrode 151, active patterns 13, source electrode 152 and drain 151 and active patterns
13 directly contact.
It should be noted that the spacing direction of source electrode 152 and drain electrode 151, refers to: source electrode 152 is directed toward the side of drain electrode 151
To.
In the embodiment of the present invention, due to the spacing direction along source electrode 152 and drain electrode 151, active patterns 13 exceed gate insulation
Pattern 14, therefore, source electrode 152 and drain electrode 151 can directly be contacted with active patterns 13, without being connected by via hole.
After light-shielding pattern 111 is set between substrate 10 and buffer layer 12, it is easy to cause first grid 153 and hides
Parasitic capacitance is formed between light pattern 111, to influence the working efficiency of array substrate.
It is further alternative based on this, as shown in figure 3, source electrode 152 is by the second via hole 122 on buffer layer 12 and hides
Light pattern 111 is electrically connected.
Herein, the second via hole 122 on buffer layer 12 can pass through with the first via hole 121 on buffer layer 12 with a structure
Figure technique is formed, and so, not will increase process costs.
In the embodiment of the present invention, by making source electrode 152 pass through the second via hole 122 and light-shielding pattern 111 on buffer layer 12
Electrical connection can avoid forming parasitic electricity between first grid 153 and light-shielding pattern 111 on the basis of not increasing process costs
Hold, to influence the working efficiency of array substrate.
Optionally, active patterns 13 include channel region, the source area positioned at channel region two sides and drain region；Channel region is serving as a contrast
Orthographic projection on bottom 10 is Chong Die with orthographic projection of the gate insulation pattern 14 on substrate 10；Channel region includes semiconductor material, source electrode
Area and drain region after carrying out conductor to semiconductor material by obtaining.
Herein, in order to improve the Ohmic contact between source electrode 152 and drain electrode 151 and active patterns 13, make top gate type thin film
Transistor and double gate type thin film transistors have preferable switching characteristic, and the source area and drain region in active patterns 13 are through leading
Body obtains.
It should be noted that first, orthographic projection of the channel region on substrate 10 can served as a contrast with gate insulation pattern 14 just
Orthographic projection on bottom 10 is completely overlapped；On this basis, orthographic projection of the channel region on substrate 10 can also exceed gate insulation figure
Case 14 is in the region where the orthographic projection on substrate 10.
Second, the specific material of semiconductor material is not defined, as long as by carrying out conductor to semiconductive thin film
After processing, available conductive source area and drain region.
Exemplary, the specific material of semiconductor material may include metal oxide, such as indium gallium zinc (indium
Gallium zinc oxide, abbreviation IGZO), indium tin zinc oxide (indium tin oxide zinc, abbreviation ITZO), nitrogen oxygen
At least one of zinc (ZnON).
The specific material of third, semiconductor material is different, and the mode of conductor is different.
Exemplary, the specific material of semiconductor material is metal oxide, can use chemical vapour deposition technique
(Chemical Vapor Deposition, abbreviation CVD), using the gas comprising H atom to being located at source area and drain region
Semiconductor material carries out conductor processing comprising the gas of H atom can be hydrogen (H2) or ammonia (NH3), H atom
(or ion) can carry out ion bombardment to metal oxide, by the O ion remaval in metal oxide；Alternatively, can use
Dry etching (dry etching) carries out conductor processing to the semiconductor material of source area and drain region, due to dry etching
To metal oxide without corrasion, the atom pair metal oxide for including in gas when using dry etching is banged
It hits, the chemical bond between the metal and oxygen in metal oxide is interrupted, so that object oxygen loss is oxidized metal, used in dry etching
Gas can be helium, the atom bombarded to metal oxide is helium atom.
In the embodiment of the present invention, by elder generation, forming material is the semiconductive thin film of semiconductor material on substrate 10, later
Conductor processing is carried out to the semiconductor material for being located at source area and drain region, active patterns 13 can be formed by same one-time process
Channel region and source area and drain region, simplify array substrate preparation process；On this basis, buffer layer 12 can will also be formed
With the second photoetching agent pattern of gate insulation pattern 14, the photoetching agent pattern for making that conductor is carried out to source area and drain region is shared,
To reduce the quantity of mask plate.
The embodiment of the present invention also provides a kind of display panel, including array substrate described in aforementioned any embodiment.
Herein, the display panel can be LCD display panel, be also possible to electroluminescence display panel.Electroluminescent
Display panel is OLED display panel, alternatively, electroluminescence display panel is inorganic EL display panel.
When display panel be LCD display panel when, backlight be supplied to display panel for display light source.Display panel
Including array substrate, to box substrate and the liquid crystal layer being disposed there between, array substrate further includes and thin film transistor (TFT)
The pixel electrode that source electrode 152 is electrically connected；It further can also include public electrode.It may include black matrix and coloured silk to box substrate
Film.Herein, color film can be set on to box substrate, may also be arranged in array substrate；Public electrode can be set in array
On substrate, it may also be arranged in counter substrate.
When display panel is electroluminescence display panel, since electroluminescence display panel is provided to itself for showing
The light source shown.Electroluminescence display panel includes array substrate and package substrate.Wherein, as shown in figure 4, array substrate can be with
Including the protective layer (PVX) between electroluminescent device 17 and electroluminescent device 17 and thin film transistor (TFT), electroluminescent device
17 include anode 171, cathode 173 and the organic material functional layer 152 between anode 171 and cathode 173, and film is brilliant
The source electrode 152 of body pipe is electrically connected with anode 171.On this basis, array substrate further includes being located at adjacent electroluminescent device 17
Between pixel defining layer 16.
The embodiment of the present invention provides a kind of display panel, including the array substrate, by making light-shielding pattern 111 and grid line
112 with a patterning processes by forming, passing through first grid 153 and source electrode 152, drain electrode 151 and data line 154 with primary
Patterning processes are formed, simultaneously as grid line 112 and the different layer of data line 154 are arranged, it is therefore not necessary to as in the prior art the
Interlayer insulating film is formed between one grid 153 and source electrode 152, drain electrode 151 and data line 154, to prevent data line 154 and grid line
112 electrical connections, that is, compared to the prior art, the embodiment of the present invention reduces twice mask, and light-shielding pattern is respectively prepared separately
The 111 mask and mask for preparing interlayer insulating film saves array substrate to reduce the preparation flow of array substrate
Preparation cost.
The embodiment of the present invention also provides a kind of preparation method of array substrate, as shown in fig. 6, specifically can be as follows
It realizes:
S11, as shown in fig. 7, forming light-shielding pattern 111 and grid line 112 on substrate 10 by a patterning processes.
Herein, metallic film can be formed on substrate 10, and forms photoresist on metallic film, and photoresist is exposed
Light, development form photoetching agent pattern；And then metallic film is performed etching, form light-shielding pattern 111 and grid line 112；Most
Afterwards, stripping photoresist pattern.
It should be noted that the material of grid line 112 and light-shielding pattern 111 should have the function of shading and conduction simultaneously, because
This, the material of grid line 112 and light-shielding pattern 111 for example can be the metal materials such as copper, aluminium.
S12, as shown in Figures 2 and 3, form film crystal on the substrate 10 for being formed with light-shielding pattern 111 and grid line 112
Pipe, thin film transistor (TFT) include first grid 153, source electrode 152 and drain electrode 151, first grid 153, source electrode 152,151 sum numbers of drain electrode
According to line 154 by being formed with a patterning processes, drain electrode 151 is electrically connected with data line 154；Wherein, first grid 153 and grid line
112 electrical connections.
It should be noted that first, first grid 153, source electrode 152, drain electrode 151 and data line 154 material include leading
Electric material is not defined the specific material of the conductive material, exemplary, first grid 153, source electrode 152, drain electrode 151
Material with data line 154 may include the metal materials such as molybdenum, copper, aluminium, also may include the transparent conductive materials such as ITO, IZO.
Second, thin film transistor (TFT) can be top gate type；As shown in figure 5, thin film transistor (TFT) is also possible to double grid type.Wherein,
Top gate type thin film transistor on-state current with higher (Ion), higher aperture opening ratio and better stability.
Herein, when thin film transistor (TFT) is double grid type, as shown in figure 5, thin film transistor (TFT) further includes second grid 113, it is excellent
It selects second grid 113 and grid line 112 is the integral structure of same layer setting, first grid 153 is electrically connected with second grid 113.
The embodiment of the present invention provides a kind of preparation method of array substrate, imitates with aforementioned array substrate technology having the same
Fruit, details are not described herein.
Optionally, after forming light-shielding pattern 111 and grid line 112, the method also includes: light-shielding pattern 111 with
Buffer layer 12 is formed between thin film transistor (TFT), buffer layer 12 includes the first via hole 121, and first grid 153 passes through the first via hole 121
It is electrically connected with grid line 112.
It wherein, specifically can be by such as shown in figure 8, forming the buffer layer 12, active patterns 13 and gate insulation pattern 14
Lower step is realized:
S21, as shown in figure 9, sequentially formed on substrate 10 first insulation film 123, active patterns 13, second insulation it is thin
Film 141, and photoresist 18 is formed away from 10 side of substrate in the second insulation film 141.
It should be noted that the material of the first, the first insulation film 123 can be with the material phase of the second insulation film 141
It together, can not also be identical.Exemplary, the material of the first insulation film 123 can be silica or organosilicon, and the second insulation is thin
The material of film 141 can be silica.
Second, photoresist 18 can be positive photoresist, be also possible to negtive photoresist.
S22, as shown in Figure 10, photoresist 18 is exposed using half-tone mask plate, forms the first photoetching after development
Glue pattern 181, part, half reservation of photoresist is fully retained partially including photoresist for the first photoetching agent pattern 181 and photoresist is complete
Full removal part；Photoresist be fully retained part it is corresponding with gate insulation pattern 14 to be formed, photoresist completely remove partially extremely
Few corresponding with the first via hole 121 to be formed, it is corresponding with other regions that photoresist half retains part.
On this basis, as shown in figure 4, if source electrode 152 passes through the second via hole 122 and light-shielding pattern in buffer layer 12
111 electrical connections, then it is corresponding with the first via hole 121 and the second via hole 122 to be formed to completely remove part for photoresist.
Certainly, be also possible that other via holes in buffer layer 12, photoresist completely remove part can also and with the first mistake
The via hole that hole 121 is formed simultaneously is corresponding.
S23, as shown in figure 11, the part progress first to exposing in the second insulation film 141 and the first insulation film 123
Secondary etching, the first insulation film 123 does not leak out grid line 112 after etching for the first time.
It should be noted that first, the part exposed in the second insulation film 141 and the first insulation film 123 is carried out
It etches, refers to: corresponding to part is completely removed with photoresist in the second insulation film 141 and the first insulation film 123 for the first time
Part carry out first time etching.
Second, during etching first time, portion only can be completely removed with photoresist in the second insulation film 141
Divide corresponding part to perform etching, can also be gone completely in the second insulation film 141 and the first insulation film 123 with photoresist
Except the corresponding part in part performs etching, as long as the first insulation film 123 does not leak out grid line 112 after etching for the first time, this
Sample one plays a protective role to grid line 112 before can etching completing second.
Wherein, it only performs etching to completely removing the corresponding part in part in the second insulation film 141 with photoresist, wraps
It includes: it is complete that the corresponding partial etching in part will be completely removed in the second insulation film 141 with photoresist, alternatively, by the second insulation
The corresponding a part of thickness of partial etching in part is completely removed with photoresist in film 141.
S24, as shown in figure 12, partly retains part using cineration technics removal photoresist, forms the second photoetching agent pattern
182。
Herein, such as oxygen (O can be used2) be ashed.
S25, to by the part exposed in the second insulation film 141 and the first insulation film 123 of etching for the first time into
Second of etching of row, to form gate insulation pattern 14 and buffer layer 12.
Wherein, second is carried out to the part by exposing in the second insulation film 141 of etching for the first time to etch, formed
Gate insulation pattern 14；Second is carried out to the part by exposing in the first insulation film 123 of etching for the first time to etch, and is formed
Buffer layer 12.
S26, the second photoetching agent pattern 182 of removing.
In the embodiment of the present invention, gate insulation pattern 14 and buffer layer 12 are formed by half-exposure mask process, can be reduced
The quantity of mask reduces process costs.
Optionally, after forming gate insulation pattern 14 and buffer layer 12, before the second photoetching agent pattern 182 of removing, institute
State method further include: conductor processing is carried out to the part exposed in active patterns 13, that is, source area to active patterns 13 and
Drain region carries out conductor processing.
Herein, in order to improve the Ohmic contact between source electrode 152 and drain electrode 151 and active patterns 13, make top gate type thin film
Transistor and double gate type thin film transistors have preferable switching characteristic, and the source area and drain region in active patterns 13 are through leading
Body obtains, and active patterns 13 further include the channel region between source area and drain region, and the material of channel region is semiconductor material,
Source area and drain region, which are passed through, obtains semiconductor material progress conductor.
It should be noted that first, the specific material of semiconductor material is not defined, as long as by semiconductor film
After film carries out conductor processing, available conductive source area and drain region.
Exemplary, the specific material of semiconductor material may include in metal oxide, such as IGZO, ITZO, ZnON
It is at least one.
Second, the specific material of semiconductor material is different, and the mode of conductor is different.
Exemplary, the specific material of semiconductor material is metal oxide, can use CVD technique, using including H atom
Gas conductor processing is carried out to the semiconductor material for being located at source area and drain region comprising the gas of H atom can be with
Hydrogen or ammonia, H atom (or ion) can carry out ion bombardment to metal oxide, by the O in metal oxide from
Son removal；Conductor processing is carried out to the semiconductor material of source area and drain region alternatively, can use dry etching, due to dry
Method etching to metal oxide without corrasion, the atom pair metal oxide that includes in gas when using dry etching into
Row bombardment, the chemical bond between the metal and oxygen in metal oxide is interrupted, to oxidize metal object oxygen loss, dry etching
Gas used can be helium, and the atom bombarded metal oxide is helium atom.
In the embodiment of the present invention, by elder generation, forming material is the semiconductive thin film of semiconductor material on substrate 10, later
Conductor processing is carried out to the semiconductor material for being located at source area and drain region, active patterns can be formed by same one-time process
Channel region and source area and drain region simplify the preparation process of array substrate；On this basis, 12 He of buffer layer can will also be formed
Second photoetching agent pattern of gate insulation pattern 14 shares the photoetching agent pattern for making that conductor is carried out to source area and drain region, with
Reduce the quantity of mask plate.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of array substrate, which is characterized in that including substrate, setting thin film transistor (TFT) over the substrate, grid line sum number
According to line and the light-shielding pattern being set between the thin film transistor (TFT) and the substrate；
The thin film transistor (TFT) includes first grid, source electrode and drain electrode, and the first grid, the source electrode, the drain electrode and
The same material of data line same layer；The drain electrode is electrically connected with the data line；
The grid line and the same material of light-shielding pattern same layer, the grid line are electrically connected with the first grid.
2. array substrate according to claim 1, which is characterized in that further include be set to the light-shielding pattern with it is described thin
Buffer layer between film transistor；
The first grid is electrically connected by the first via hole on the buffer layer with the grid line.
3. array substrate according to claim 1, which is characterized in that the thin film transistor (TFT) further includes second grid, institute
It states second grid and the grid line is the integral structure of same layer setting；
The first grid is electrically connected with the second grid.
4. array substrate according to claim 1-3, which is characterized in that the thin film transistor (TFT) further includes successively
Active patterns and gate insulation pattern over the substrate are stacked, the active patterns and the gate insulation pattern are set to
Between buffer layer and the first grid；
Along the spacing direction of the source electrode and the drain electrode, the active patterns exceed the gate insulation pattern, the source electrode and
The drain electrode is directly contacted with the active patterns.
5. array substrate according to claim 4, which is characterized in that the source electrode by the second via hole on buffer layer with
The light-shielding pattern electrical connection.
6. array substrate according to claim 4, which is characterized in that the active patterns include channel region, positioned at described
The source area of channel region two sides and drain region；
The orthographic projection of the channel region over the substrate is Chong Die with the orthographic projection of the gate insulation pattern over the substrate；
The channel region includes semiconductor material, and the source area and the drain region are by leading the semiconductor material
It is obtained after body.
7. a kind of display panel, which is characterized in that including array substrate described in any one of claims 1-6.
8. a kind of preparation method of array substrate characterized by comprising
Light-shielding pattern and grid line is formed on the substrate by a patterning processes；
Form thin film transistor (TFT) on the substrate for being formed with the light-shielding pattern and the grid line, the thin film transistor (TFT) includes the
One grid, source electrode and drain electrode, the first grid, the source electrode, the drain electrode and data line pass through with a patterning processes shape
At the drain electrode is electrically connected with the data line；
Wherein, the first grid is electrically connected with the grid line.
9. the preparation method of array substrate according to claim 8, which is characterized in that formed light-shielding pattern and grid line it
Afterwards, the method also includes:
Buffer layer is formed between the light-shielding pattern and the thin film transistor (TFT), the buffer layer includes the first via hole, described
First grid is electrically connected by first via hole with the grid line；
Wherein, the buffer layer, the active patterns and gate insulation pattern are formed, comprising:
The first insulation film, active patterns, the second insulation film are sequentially formed over the substrate, and thin in second insulation
Film forms photoresist away from the one side of substrate；
The photoresist is exposed using half-tone mask plate, forms the first photoetching agent pattern, first light after development
Photoresist pattern includes that part is fully retained in photoresist, photoresist half retains part and photoresist completely removes part；The photoetching
Glue be fully retained part it is corresponding with the gate insulation pattern to be formed, the photoresist completely remove partially at least with it is to be formed
First via hole it is corresponding, it is corresponding with other regions that the photoresist half retains part；
First time etching is carried out to the part exposed in second insulation film and first insulation film, is etched for the first time
First insulation film does not leak out the grid line afterwards；
The photoresist is removed using cineration technics and partly retains part, forms the second photoetching agent pattern；
Second is carried out to the part by exposing in second insulation film and first insulation film of etching for the first time
Secondary etching, to form the gate insulation pattern and the buffer layer；
Remove second photoetching agent pattern.
10. the preparation method of array substrate according to claim 9, which is characterized in that forming the gate insulation pattern
With after the buffer layer, before removing second photoetching agent pattern, the method also includes:
Conductor processing is carried out to the part exposed in the active patterns.
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| CN112289841A (en) * | 2020-10-30 | 2021-01-29 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
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Application publication date: 20190507 |