CN110993610A - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
- Publication number
- CN110993610A CN110993610A CN201911170179.4A CN201911170179A CN110993610A CN 110993610 A CN110993610 A CN 110993610A CN 201911170179 A CN201911170179 A CN 201911170179A CN 110993610 A CN110993610 A CN 110993610A
- Authority
- CN
- China
- Prior art keywords
- layer
- region
- amorphous oxide
- passivation layer
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 70
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 98
- 238000002161 passivation Methods 0.000 claims abstract description 64
- 239000004020 conductor Substances 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 4
- 229910001887 tin oxide Inorganic materials 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 7
- 239000001257 hydrogen Substances 0.000 abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000005300 metallic glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate, a preparation method thereof and a display panel, wherein the array substrate comprises a substrate, a grid insulating layer, an amorphous oxide semiconductor layer, an etching barrier layer and a source drain metal layer, the source drain metal layer comprises a source electrode and a drain electrode, the amorphous oxide semiconductor layer comprises a semiconductor region and a conductor region which is made of a conductor, the conductor region is positioned on at least one side of the semiconductor region, at least one of the source electrode and the drain electrode is connected with the conductor region, and the orthographic projection of the conductor region on the substrate is partially overlapped with the grid; the hydrogen-rich passivation layer is prepared on the etching barrier layer, and after thermal annealing treatment, hydrogen in the passivation layer is diffused into the semiconductor layer, so that the conductivity of the semiconductor layer is changed, and the uniformity is good; a grid electrode with a narrower width can be prepared, so that an overlapping area does not exist between the grid electrode and the source electrode/drain electrode, thereby reducing parasitic capacitance and improving display effect; in addition, a double-channel TFT structure can be prepared, and the manufacturing process is simple.
Description
Technical Field
The application relates to the technical field of display panels, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
The core component of the array substrate driving circuit is a Thin-film transistor (TFT) device with a switching function, wherein a semiconductor layer is a key film layer, the semiconductor layer needs to be in contact with a source/drain of the TFT, and an amorphous metal oxide is used as a material for manufacturing the semiconductor layer, so that the semiconductor layer has many excellent performances such as mobility, low sub-threshold, low leakage current and low-temperature manufacturing, and is thus well focused by the display panel industry.
However, since the amorphous oxide semiconductor layer is subjected to Plasma (Plasma) treatment before the formation of the source/drain electrodes, and becomes a conductor, the conductivity of the amorphous oxide semiconductor layer after the Plasma treatment exists only in a part of the surface of the amorphous oxide semiconductor layer, a longer gate electrode is still required to be prepared to collect carriers in the amorphous oxide semiconductor layer, and thus the source/drain electrodes are turned on; in this case, a certain overlap region exists between the gate and the source/drain located thereon, which may generate a large parasitic capacitance, seriously affect the electrical performance of the TFT, and easily cause poor electrical uniformity of the TFT for a large-sized display screen, thereby generating display non-uniformity and other anomalies.
In summary, it is desirable to provide a new array substrate, a method for manufacturing the same, and a display panel, so as to solve the above technical problems.
Disclosure of Invention
The invention provides an array substrate, a preparation method thereof and a display panel, and solves the technical problems that in the array substrate in the prior art, an overlapping area exists between a grid electrode and a source electrode/drain electrode, a large parasitic capacitance is generated, and uneven display is easily caused.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
an embodiment of the present invention provides an array substrate, including:
a substrate base plate;
the grid is arranged on the substrate base plate;
the grid insulating layer is arranged on the grid and the substrate base plate;
an amorphous oxide semiconductor layer disposed on the gate insulating layer;
the etching barrier layer is arranged on the amorphous oxide semiconductor layer; and
the source and drain metal layer is arranged on the grid insulating layer and the etching barrier layer and comprises a source electrode and a drain electrode;
wherein the amorphous oxide semiconductor layer includes a semiconductor region and a conductive region that is made conductive, the conductive region being located on at least one side of the semiconductor region, at least one of the source and the drain being connected to the conductive region, and an orthographic projection of the conductive region on the substrate overlaps with the gate portion.
According to the array substrate provided by the embodiment of the invention, the array substrate further comprises a passivation layer, the passivation layer is arranged on the etching barrier layer and is arranged corresponding to the conductor region, and the passivation layer contains hydrogen atoms.
According to the array substrate provided by the embodiment of the invention, the conductor region comprises a first conductor region and a second conductor region, and the first conductor region and the second conductor region are respectively positioned on two sides of the semiconductor region; the passivation layer and the etching barrier layer are provided with first through holes, the passivation layer and the etching barrier layer are provided with second through holes, the source electrode is connected with the first conductor region through the first through holes, and the drain electrode is connected with the second conductor region through the second through holes.
According to the array substrate provided by the embodiment of the invention, the conductor region further includes at least one third conductor region which is made of a conductor, the third conductor region divides the semiconductor region into at least a first semiconductor region and a second semiconductor region, and the first conductor region, the first semiconductor region, the third conductor region, the second semiconductor region and the second conductor region are arranged at intervals.
According to the array substrate provided by the embodiment of the invention, the passivation layer is a silicon nitride layer containing hydrogen atoms.
According to the array substrate provided by the embodiment of the invention, the material of the amorphous oxide semiconductor layer is one of indium gallium zinc oxide and indium gallium tin oxide.
An embodiment of the invention provides a display panel, which includes the array substrate.
The embodiment of the invention provides a preparation method of an array substrate, which comprises the following steps:
step S10: sequentially forming a grid electrode, a grid electrode insulating layer, an amorphous oxide semiconductor layer and an etching barrier layer on a substrate, wherein the grid electrode is positioned in the orthographic projection of the amorphous oxide semiconductor layer on the substrate;
step S20: depositing a passivation layer on the etching barrier layer, wherein the passivation layer contains hydrogen atoms;
step S30: performing a yellow light process on the passivation layer to enable the passivation layer subjected to patterning treatment to be arranged corresponding to a region to be conducted by the amorphous oxide semiconductor layer;
step S40: performing thermal annealing treatment on the amorphous oxide semiconductor layer, wherein hydrogen atoms in the passivation layer are diffused into the amorphous oxide semiconductor layer, and the amorphous oxide semiconductor layer forms a semiconductor region and a conductor region which is made of conductor and is positioned on at least one side of the semiconductor region;
step S50: forming holes in the etching barrier layer and the passivation layer; and
step S60: and depositing a source drain metal layer on the gate insulating layer and the etching barrier layer, and performing a yellow light process on the source drain metal layer to form a source electrode and a drain electrode, wherein at least one of the source electrode and the drain electrode is connected with the conductor region.
According to the preparation method of the array substrate provided by the embodiment of the invention, in the step S20, ammonia gas is introduced when the passivation layer is deposited on the etching barrier layer, so that the passivation layer contains hydrogen atoms.
According to the preparation method of the array substrate provided by the embodiment of the invention, the passivation layer is a silicon nitride layer containing hydrogen atoms.
The invention has the beneficial effects that: according to the array substrate, the preparation method thereof and the display panel, the hydrogen-rich passivation layer is prepared on the etching barrier layer, and after thermal annealing treatment, hydrogen in the passivation layer is diffused into the semiconductor layer, so that the conductivity of the semiconductor layer is changed, and the uniformity is good; a grid electrode with a narrower width can be prepared, so that an overlapping area does not exist between the grid electrode and the source electrode/drain electrode, thereby reducing parasitic capacitance and improving display effect; in addition, a double-channel TFT structure can be prepared, and the manufacturing process is simple.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of another array substrate according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 4 to 9 are schematic views illustrating a method for manufacturing an array substrate according to an embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Aiming at the problem that in the array substrate in the prior art, an overlapped area exists between a grid electrode and a source electrode/drain electrode, a large parasitic capacitance is generated, uneven display is easily caused, and the defect can be solved by the embodiment.
As shown in fig. 1, the array substrate provided in the embodiment of the present invention includes a substrate 11, and a gate 12, a gate insulating layer 13, an amorphous oxide semiconductor layer 14, an etching blocking layer 15, and a source/drain metal layer, which are sequentially stacked on the substrate 11.
Specifically, the substrate 11 may be a glass substrate, the gate 12 is located on the substrate 11, the gate insulating layer 13 covers the gate 12 and the substrate 11, the amorphous oxide semiconductor layer 14 covers the gate insulating layer 13, the etching blocking layer 15 covers the amorphous oxide semiconductor layer 14, the source and drain metal layer covers the gate insulating layer 13 and the etching blocking layer 15, the source and drain metal layer includes a source 17 and a drain 18, and a channel is formed between the source 17 and the drain 18.
A partial region of the amorphous oxide semiconductor layer 14 is made conductive so that the amorphous oxide semiconductor layer 14 is divided into a semiconductor region 141 and a conductive region 142 according to a conductive region and a non-conductive region, the conductive region 142 is located on at least one side of the semiconductor region 141, at least one of the source electrode 17 and the drain electrode 18 is connected to the conductive region 142, and an orthographic projection of the conductive region 142 on the substrate 11 partially overlaps with the gate electrode 12; it is understood that the contact resistance between the conductor region 142 and the source electrode 17 or the drain electrode 18 is greatly reduced, thereby ensuring good electrical performance of the TFT, and the width of the gate electrode 12 is reduced compared to the prior art, so that the area of the overlapping region between the gate electrode 12 and the source electrode 17 or the drain electrode 18 is reduced, thereby reducing the generation of parasitic capacitance.
Further, in the embodiment of the present invention, the conductor region 142 may be formed by diffusing hydrogen atoms into a region of the amorphous oxide semiconductor layer 14 to be conducted with a conductor, for example, the array substrate further includes a passivation layer 16, the passivation layer 16 contains a large amount of hydrogen atoms, and the passivation layer 16 covers the etch stop layer 15; since the diffusion of hydrogen atoms is isotropic during the subsequent thermal treatment, the passivation layer 16 is disposed corresponding to the region to be conducted with a conductor (i.e., the conductor region 142), so that the hydrogen atoms in the passivation layer 16 can be uniformly diffused into the amorphous oxide semiconductor layer 14, and the formed conductor region 142 has good electrical uniformity.
In one embodiment, the conductor regions 142 may be located on two opposite sides of the semiconductor region 141, and the array substrate is a single-channel TFT structure.
Specifically, the conductor region 142 includes a first conductor region 1421 and a second conductor region 1422, and the first conductor region 1421 and the second conductor region 1422 are respectively located on two sides of the semiconductor region 141; a first via hole 19 is formed in the passivation layer 16 and the corresponding etching barrier layer 15, and a second via hole 20 is formed in the passivation layer 16 and the corresponding etching barrier layer 15, wherein the source electrode 17 is connected to the first conductor region 1421 through the first via hole 19, and the drain electrode 18 is connected to the second conductor region 1422 through the second via hole 20; in this embodiment, the source electrode 17 and the drain electrode 18 are connected to the corresponding conductive regions 142, respectively, as compared with the case where the conductive regions 142 are located on one side of the semiconductor region 141, so that the contact resistance can be further reduced, and the width of the gate electrode 12 can be further reduced, thereby further reducing the generation of parasitic capacitance.
Further, in another embodiment, as shown in fig. 2, the conductive region 142 further includes at least one third conductive region 1423 formed by a conductor, the third conductive region 1423 is located in the semiconductor region 141, and the semiconductor region 141 can be divided into at least a first semiconductor region 1411 and a second semiconductor region 1412, in this embodiment of the invention, there is one third conductive region 1423, and the first conductive region 1421, the first semiconductor region 1411, the third conductive region 1423, the second semiconductor region 1412 and the second conductive region 1422 are disposed at intervals; at this time, the array substrate is of a double-channel TFT structure, so that the charging capability of the TFT can be improved, and the double-channel TFT structure is of a series TFT structure.
Specifically, the passivation layer 16 is a silicon nitride (SiNx) layer containing hydrogen atoms.
Specifically, the material of the amorphous oxide semiconductor layer 14 is one of indium gallium zinc oxide and indium gallium tin oxide.
As shown in fig. 3, an embodiment of the present invention further provides a method for manufacturing an array substrate, including the following steps:
step S10: a gate electrode 12, a gate insulating layer 13, an amorphous oxide semiconductor layer 14 and an etching barrier layer 15 are sequentially formed on a substrate 11, wherein the gate electrode is positioned in the orthographic projection of the amorphous oxide semiconductor layer 14 on the substrate 10.
Specifically, as shown in fig. 4, the gate electrode 12 is formed on the substrate 11, the gate insulating layer 13 is formed on the gate electrode 12 and the substrate 11, the amorphous oxide semiconductor layer 14 is formed on the gate insulating layer 13, and the etch stop layer 15 is formed on the amorphous oxide semiconductor layer 14, where it is noted that the width of the formed gate electrode 12 may be smaller than the width of the amorphous oxide semiconductor layer 14; the gate 12 may be made of one of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti), and the amorphous oxide semiconductor layer 14 may be one of Indium Gallium Zinc Oxide (IGZO) and Indium Gallium Tin Oxide (IGTO).
Step S20: and depositing a passivation layer 16 on the etching barrier layer 15, wherein hydrogen atoms are contained in the passivation layer 16.
Specifically, as shown in fig. 5, the passivation layer 16 may be deposited on the etch stop layer 15 by using a chemical vapor deposition method, and since the amorphous oxide semiconductor layer 14 is sensitive to hydrogen and is prone to become conductive, in an embodiment of the present invention, the passivation layer 16 may be a silicon nitride layer formed by reacting a silane material with introduced ammonia gas, so that hydrogen atoms are contained in the passivation layer 16.
Step S30: a yellow light process is performed on the passivation layer 16, so that the patterned passivation layer 16 is disposed corresponding to the region to be conducted of the amorphous oxide semiconductor layer 14.
Specifically, as shown in fig. 6, a layer of photoresist is coated on the passivation layer 16, the photoresist is exposed, developed and etched, and the remaining photoresist is stripped after the etching is completed, so that the remaining passivation layer 16 and the region of the amorphous oxide semiconductor layer 14, which needs to be made conductive, are arranged correspondingly, wherein if the region of the amorphous oxide semiconductor layer 14, which needs to be made conductive, is located at two ends of the amorphous oxide semiconductor layer 14, the array substrate finally prepared is in a single-channel TFT structure; if the regions of the amorphous oxide semiconductor layer 14 that need to be made into conductors are located at the two ends and the middle region of the amorphous oxide semiconductor layer 14, the remaining passivation layer 16 covers the etching blocking layer 15 corresponding to the middle region, and the array substrate finally prepared is of a double-channel TFT structure.
In order to clearly explain the technical solution of the present invention, the embodiment of the present invention is described by taking the finally prepared single-channel TFT structure of the array substrate as an example.
Step S40: the passivation layer 16 is subjected to a thermal annealing process, hydrogen atoms in the passivation layer 16 diffuse into the amorphous oxide semiconductor layer 14, the amorphous oxide semiconductor layer 14 forms a semiconductor region 141 and a conductive conductor region 142, and the conductor region 142 is located on at least one side of the semiconductor region 141.
Specifically, as shown in fig. 7, the passivation layer 16 is subjected to a thermal annealing process, so that hydrogen atoms in the passivation layer 16 diffuse into a partial region of the amorphous oxide semiconductor layer 14 corresponding to the passivation layer 16, and the oxygen content of the region is redistributed to increase free charges thereof, so that the region becomes conductive to form the conductive region 142; the conductive region 142 includes a first conductive region 1421 and a second conductive region 1422, and the first conductive region 1421 and the second conductive region 1422 are respectively located on two sides of the semiconductor region 141. Since the hydrogen atoms are isotropic in diffusion during the subsequent thermal annealing treatment, the formed conductor region 142 has good electrical uniformity and the conductive state thereof is not easily changed; in the embodiment of the invention, the thermal annealing treatment can be carried out in the environment of compressed dry air or nitrogen, the thermal treatment temperature can be 280-320 ℃, and meanwhile, the hydrogen atoms can be ensured to be fully diffused by properly increasing the temperature or the treatment time.
Since the passivation layer 16 is made of an inorganic material, in the embodiment of the present invention, after the conductor region is formed, the passivation layer does not need to be removed, so that the water and oxygen resistance of the amorphous oxide semiconductor layer 14 can be further improved.
Step S50: openings are made in the etch stop layer 15 and the passivation layer 16.
As shown in fig. 8, holes are opened in the etching stop layer 15 and the passivation layer 16 corresponding to the conductor region 142, specifically, a first via hole 19 is opened in the passivation layer 16 and the corresponding etching stop layer 15, and a second via hole 20 is opened in the passivation layer 16 and the corresponding etching stop layer 15.
Step S60: depositing a source and drain metal layer on the gate insulating layer 13 and the etching barrier layer 15, and performing a yellow light process on the source and drain metal layer to form a source electrode 17 and a drain electrode 18, wherein at least one of the source electrode 17 and the drain electrode 18 is connected to the conductor region 142.
Specifically, as shown in fig. 9, a physical vapor deposition method may be adopted to deposit the source and drain metal layers on the gate insulating layer 13 and the etching blocking layer 15, coat a layer of photoresist on the source and drain metal layers, perform exposure, development and etching processes on the photoresist, and strip off the remaining photoresist after the etching is completed to form the source 17 and the drain 18, where the source 17 is connected to the first conductor region 1421 through the first via hole 19, and the drain 18 is connected to the second conductor region 1422 through the second via hole 20.
It can be seen that the contact resistance between the source and drain electrodes 17 and 18 and the amorphous oxide semiconductor layer 14 can be greatly reduced, thereby enhancing the electrical performance of the TFT; meanwhile, the length of the gate 12 is greatly reduced compared with the prior art, so that the area of an overlapping region between the gate 12 and the source electrode 17 and the drain electrode 18 is reduced, the parasitic capacitance is reduced, and the display effect is improved.
The embodiment of the invention also provides a display panel, which comprises the array substrate, and the display panel can be a liquid crystal display panel and also can be an organic light emitting diode display panel.
The beneficial effects are that: according to the array substrate, the preparation method thereof and the display panel, the hydrogen-rich passivation layer is prepared on the etching barrier layer, and after thermal annealing treatment, hydrogen in the passivation layer is diffused into the semiconductor layer, so that the conductivity of the semiconductor layer is changed, and the uniformity is good; a grid electrode with a narrower width can be prepared, so that an overlapping area does not exist between the grid electrode and the source electrode/drain electrode, thereby reducing parasitic capacitance and improving display effect; in addition, a double-channel TFT structure can be prepared, and the manufacturing process is simple.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate base plate;
the grid is arranged on the substrate base plate;
the grid insulating layer is arranged on the grid and the substrate base plate;
an amorphous oxide semiconductor layer disposed on the gate insulating layer;
the etching barrier layer is arranged on the amorphous oxide semiconductor layer; and
the source and drain metal layer is arranged on the grid insulating layer and the etching barrier layer and comprises a source electrode and a drain electrode;
wherein the amorphous oxide semiconductor layer includes a semiconductor region and a conductive region that is made conductive, the conductive region being located on at least one side of the semiconductor region, at least one of the source and the drain being connected to the conductive region, and an orthographic projection of the conductive region on the substrate overlaps with the gate portion.
2. The array substrate of claim 1, further comprising a passivation layer disposed on the etch stop layer and corresponding to the conductor region, wherein hydrogen atoms are contained in the passivation layer.
3. The array substrate of claim 2, wherein the conductor region comprises a first conductor region and a second conductor region, the first conductor region and the second conductor region being respectively located on both sides of the semiconductor region; the passivation layer and the etching barrier layer are provided with first through holes, the passivation layer and the etching barrier layer are provided with second through holes, the source electrode is connected with the first conductor region through the first through holes, and the drain electrode is connected with the second conductor region through the second through holes.
4. The array substrate of claim 3, wherein the conductive region further comprises at least one third conductive region that is conductive, the third conductive region dividing the semiconductor region into at least a first semiconductor region and a second semiconductor region, the first conductive region, the first semiconductor region, the third conductive region, the second semiconductor region, and the second conductive region being spaced apart.
5. The array substrate of claim 2, wherein the passivation layer is a silicon nitride layer containing hydrogen atoms.
6. The array substrate of claim 1, wherein the amorphous oxide semiconductor layer is made of one of indium gallium zinc oxide and indium gallium tin oxide.
7. A display panel comprising the array substrate according to any one of claims 1 to 6.
8. The preparation method of the array substrate is characterized by comprising the following steps:
step S10: sequentially forming a grid electrode, a grid electrode insulating layer, an amorphous oxide semiconductor layer and an etching barrier layer on a substrate, wherein the grid electrode is positioned in the orthographic projection of the amorphous oxide semiconductor layer on the substrate;
step S20: depositing a passivation layer on the etching barrier layer, wherein the passivation layer contains hydrogen atoms;
step S30: performing a yellow light process on the passivation layer to enable the passivation layer subjected to patterning treatment to be arranged corresponding to a region to be conducted by the amorphous oxide semiconductor layer;
step S40: performing thermal annealing treatment on the amorphous oxide semiconductor layer, wherein hydrogen atoms in the passivation layer are diffused into the amorphous oxide semiconductor layer, and the amorphous oxide semiconductor layer forms a semiconductor region and a conductor region which is made of conductor and is positioned on at least one side of the semiconductor region;
step S50: forming holes in the etching barrier layer and the passivation layer; and
step S60: and depositing a source drain metal layer on the gate insulating layer and the etching barrier layer, and performing a yellow light process on the source drain metal layer to form a source electrode and a drain electrode, wherein at least one of the source electrode and the drain electrode is connected with the conductor region.
9. The method of claim 8, wherein ammonia gas is introduced during the step of depositing the passivation layer on the etching stop layer in step S20, so that hydrogen atoms are contained in the passivation layer.
10. The method of claim 9, wherein the passivation layer is a silicon nitride layer containing hydrogen atoms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911170179.4A CN110993610A (en) | 2019-11-26 | 2019-11-26 | Array substrate, preparation method thereof and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911170179.4A CN110993610A (en) | 2019-11-26 | 2019-11-26 | Array substrate, preparation method thereof and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110993610A true CN110993610A (en) | 2020-04-10 |
Family
ID=70086839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911170179.4A Pending CN110993610A (en) | 2019-11-26 | 2019-11-26 | Array substrate, preparation method thereof and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110993610A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987111A (en) * | 2020-08-12 | 2020-11-24 | Tcl华星光电技术有限公司 | Array substrate, array substrate manufacturing method and display panel |
| CN113097289A (en) * | 2021-03-30 | 2021-07-09 | 合肥维信诺科技有限公司 | Thin film transistor, preparation method thereof and array substrate |
| WO2023092554A1 (en) * | 2021-11-29 | 2023-06-01 | 京东方科技集团股份有限公司 | Thin-film transistor and method for preparing same, and array substrate and display panel |
| WO2023103004A1 (en) * | 2021-12-08 | 2023-06-15 | 深圳市华星光电半导体显示技术有限公司 | Driving substrate and preparation method therefor, and display panel |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102257621A (en) * | 2008-12-19 | 2011-11-23 | 株式会社半导体能源研究所 | Method for manufacturing transistor |
| CN102640292A (en) * | 2009-11-27 | 2012-08-15 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| KR20140070996A (en) * | 2012-12-03 | 2014-06-11 | 엘지디스플레이 주식회사 | Thin film transistor, display device including the same, and method for manufacturing thereof |
| CN106098784A (en) * | 2016-06-13 | 2016-11-09 | 武汉华星光电技术有限公司 | Coplanar type double grid electrode oxide thin film transistor and preparation method thereof |
| CN107195583A (en) * | 2017-05-02 | 2017-09-22 | 深圳市华星光电技术有限公司 | A kind of OLED display panel and preparation method thereof |
| CN107204309A (en) * | 2017-05-22 | 2017-09-26 | 深圳市华星光电技术有限公司 | The preparation method and its structure of dual gate metal oxide semiconductor TFT substrate |
| CN109698240A (en) * | 2017-10-24 | 2019-04-30 | 乐金显示有限公司 | Thin film transistor (TFT) including two-dimensional semiconductor and the display equipment including it |
-
2019
- 2019-11-26 CN CN201911170179.4A patent/CN110993610A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102257621A (en) * | 2008-12-19 | 2011-11-23 | 株式会社半导体能源研究所 | Method for manufacturing transistor |
| CN102640292A (en) * | 2009-11-27 | 2012-08-15 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| KR20140070996A (en) * | 2012-12-03 | 2014-06-11 | 엘지디스플레이 주식회사 | Thin film transistor, display device including the same, and method for manufacturing thereof |
| CN106098784A (en) * | 2016-06-13 | 2016-11-09 | 武汉华星光电技术有限公司 | Coplanar type double grid electrode oxide thin film transistor and preparation method thereof |
| CN107195583A (en) * | 2017-05-02 | 2017-09-22 | 深圳市华星光电技术有限公司 | A kind of OLED display panel and preparation method thereof |
| CN107204309A (en) * | 2017-05-22 | 2017-09-26 | 深圳市华星光电技术有限公司 | The preparation method and its structure of dual gate metal oxide semiconductor TFT substrate |
| CN109698240A (en) * | 2017-10-24 | 2019-04-30 | 乐金显示有限公司 | Thin film transistor (TFT) including two-dimensional semiconductor and the display equipment including it |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987111A (en) * | 2020-08-12 | 2020-11-24 | Tcl华星光电技术有限公司 | Array substrate, array substrate manufacturing method and display panel |
| CN111987111B (en) * | 2020-08-12 | 2023-09-05 | Tcl华星光电技术有限公司 | Array substrate, array substrate manufacturing method and display panel |
| CN113097289A (en) * | 2021-03-30 | 2021-07-09 | 合肥维信诺科技有限公司 | Thin film transistor, preparation method thereof and array substrate |
| WO2023092554A1 (en) * | 2021-11-29 | 2023-06-01 | 京东方科技集团股份有限公司 | Thin-film transistor and method for preparing same, and array substrate and display panel |
| WO2023103004A1 (en) * | 2021-12-08 | 2023-06-15 | 深圳市华星光电半导体显示技术有限公司 | Driving substrate and preparation method therefor, and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110993610A (en) | Array substrate, preparation method thereof and display panel | |
| US10236388B2 (en) | Dual gate oxide thin-film transistor and manufacturing method for the same | |
| CN105702744B (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN109037150B (en) | Metal oxide semiconductor thin film transistor array substrate and manufacturing method thereof | |
| US9842915B2 (en) | Array substrate for liquid crystal display device and method of manufacturing the same | |
| CN106098784A (en) | Coplanar type double grid electrode oxide thin film transistor and preparation method thereof | |
| CN108417580B (en) | Array substrate, manufacturing method thereof and display panel | |
| CN107316874B (en) | Array substrate, manufacturing method thereof and display device | |
| WO2018176784A1 (en) | Thin film transistor, manufacturing method therefor, array substrate and display device | |
| CN109686794B (en) | Thin film transistor, manufacturing method thereof and display device | |
| WO2020062483A1 (en) | Thin film transistor array substrate, fabrication method therefor and display panel | |
| CN108565247B (en) | Manufacturing method of LTPS TFT substrate and LTPS TFT substrate | |
| CN109166802A (en) | LTPS array substrate and its manufacturing method, display panel | |
| KR20200078621A (en) | TFT substrate and manufacturing method thereof | |
| KR20200003143A (en) | OLED display panel and its manufacturing method | |
| KR102148957B1 (en) | Display substrate and method of manufacturing a display substrate | |
| US10957713B2 (en) | LTPS TFT substrate and manufacturing method thereof | |
| KR20160017867A (en) | Display device and method of fabricating the same | |
| KR100272272B1 (en) | Thin film transistor and method of manufacturing the same | |
| CN107833893A (en) | Array base palte and preparation method thereof, display panel | |
| CN109742031B (en) | Thin film transistor, preparation method thereof, array substrate and display device | |
| WO2022148260A1 (en) | Thin-film transistor array substrate and preparation method therefor, and display panel | |
| KR20120067108A (en) | Array substrate and method of fabricating the same | |
| US10249763B2 (en) | Array substrate, and display device, and fabrication methods | |
| CN108231869A (en) | Transistor, display base plate, display device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200410 |