KR20120067108A - Array substrate and method of fabricating the same - Google Patents

Array substrate and method of fabricating the same Download PDF

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KR20120067108A
KR20120067108A KR1020100128544A KR20100128544A KR20120067108A KR 20120067108 A KR20120067108 A KR 20120067108A KR 1020100128544 A KR1020100128544 A KR 1020100128544A KR 20100128544 A KR20100128544 A KR 20100128544A KR 20120067108 A KR20120067108 A KR 20120067108A
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South Korea
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layer
gate
forming
amorphous silicon
active
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KR1020100128544A
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Korean (ko)
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박미경
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엘지디스플레이 주식회사
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Publication of KR20120067108A publication Critical patent/KR20120067108A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention includes forming a gate metal layer on a substrate on which a pixel region including an element region is defined; Forming a gate insulating film and an active layer of pure polysilicon in an island form sequentially stacked on the gate metal layer in the device region; A gate wiring having a multi-layer structure by forming a first metal layer over the active layer of the pure polysilicon and patterning the first metal layer and the gate metal layer, and connected to the gate wiring under the gate insulating layer in the device region. Forming a gate electrode; Depositing and patterning an insulating material over the gate wiring and the active layer to form an interlayer insulating film having active contact holes that expose the active layer to both sides of the active layer; Source and drain electrodes are sequentially stacked on the interlayer insulating layer and are spaced apart from the first and second buffer patterns and the ohmic contact layer in contact with the active layer and spaced apart from each other through the active contact hole. And simultaneously forming a data line connected to the source electrode and crossing the gate line at a boundary of the pixel area over the interlayer insulating film; Forming a protective layer having a drain contact hole exposing the drain electrode over the data line and a source and drain electrode; And forming a pixel electrode in contact with the drain electrode in each pixel region by depositing and patterning a transparent conductive material on the entire surface over the protective layer.

Description

Array substrate and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and particularly to an array substrate having a thin film transistor having an active layer excellent in mobility characteristics and having an improved off current characteristic. It is about.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling the voltage on / off of each pixel, realizes resolution and video. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each pixel area on / off.

FIG. 1 is a cross-sectional view of a pixel area including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting display device.

As illustrated, the gate electrode 15 is disposed in the switching region TrA in the plurality of pixel regions P defined by the plurality of gate lines (not shown) and the data lines 33 intersecting on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26. The thickness difference t1? T2 of the active layer 22 is due to a manufacturing method, and the characteristic difference of the thin film transistor Tr occurs due to the thickness difference t1? T2 of the active layer 22. Doing.

2A through 2E are cross-sectional views illustrating a process of forming a semiconductor layer, a source, and a drain electrode during a manufacturing process of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

First, as shown in FIG. 2A, the pure amorphous silicon layer 20 is formed on the substrate 11, and the impurity amorphous silicon layer 24 and the metal layer 30 are sequentially formed thereon. Thereafter, a photoresist is formed on the metal layer 30 to form a photoresist layer (not shown), and the photoresist is exposed using an exposure mask, and subsequently developed to correspond to a portion where the source and drain electrodes are to be formed. A first photoresist pattern 91 having a thickness is formed, and at the same time, a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed to correspond to the spaced area between the source and drain electrodes. .

Next, as shown in FIG. 2B, the metal layer (30 of FIG. 2A) exposed to the outside of the first and second photoresist patterns 91 and 92, an impurity and a pure amorphous silicon layer below it (of FIG. 2A) 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top, and an impurity amorphous silicon pattern 25 and an active layer 22 below.

Next, as shown in FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by ashing. In this case, the first photoresist pattern (91 in FIG. 2B) having the third thickness forms the third photoresist pattern 93 while the thickness thereof is reduced, and remains on the source drain pattern 31.

Next, as illustrated in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching by removing the source drain pattern 31 of FIG. 2C exposed to the outside of the third photoresist pattern 93. To form. In this case, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the source and drain electrodes are dry-etched on the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the separation region between the source and drain electrodes 36 and 38. (36, 38) An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside of the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (Fig. Even a portion of the active layer 22 disposed below 25) of 2d may have a predetermined thickness etched at a portion where the impurity amorphous silicon pattern (25 of FIG. 2d) is removed. Therefore, the thickness difference (t1? T2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (25 of FIG. 2D) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22. This is to prevent this.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer (20 in FIG. 2A) forming the active layer 22 is sufficiently thick in consideration of the thickness of the active layer 22 that is etched and removed during the dry etching process for forming the ohmic contact layer 26. It should be deposited thick enough to have a thickness of 1000Å or more, which results in increased deposition time and reduced productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier at 0.1 cm2 / V? S? 1.0 cm2 / V? S is low, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the fabrication of the array substrate 51 including the thin film transistor Tr, which is used as 55), the n + region 55b including high concentration of impurities in both sides of the first region 55a in the semiconductor layer 55 made of polysilicon. Or p + region (not shown). Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching, thereby preventing damage to the surface thereof, thereby improving characteristics of the thin film transistor. .

Furthermore, another object of the present invention is to provide a method of manufacturing an array substrate having a thin film transistor having an active layer formed of polysilicon, without requiring a doping process, improving mobility characteristics, and improving off current characteristics. .

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming a gate metal layer on a substrate on which a pixel region including an element region is defined; Forming a gate insulating film and an active layer of pure polysilicon in an island form sequentially stacked on the gate metal layer in the device region; A gate wiring having a multi-layer structure by forming a first metal layer over the active layer of the pure polysilicon and patterning the first metal layer and the gate metal layer, and connected to the gate wiring under the gate insulating layer in the device region. Forming a gate electrode; Depositing and patterning an insulating material over the gate wiring and the active layer to form an interlayer insulating film having active contact holes that expose the active layer to both sides of the active layer; Source and drain electrodes are sequentially stacked on the interlayer insulating layer and are spaced apart from the first and second buffer patterns and the ohmic contact layer in contact with the active layer and spaced apart from each other through the active contact hole. And simultaneously forming a data line connected to the source electrode and crossing the gate line at a boundary of the pixel area over the interlayer insulating film; Forming a protective layer having a drain contact hole exposing the drain electrode over the data line and a source and drain electrode; And forming a pixel electrode in contact with the drain electrode in each pixel area by depositing and patterning a transparent conductive material over the protective layer on the entire surface.

In this case, the forming of the source and drain electrodes spaced apart from the first and second buffer patterns, the ohmic contact layer, and the data line may include a microcrystalline silicon layer and an impurity having a first concentration on the interlayer insulating layer. Forming a second impurity amorphous silicon layer comprising a first impurity amorphous silicon layer and an impurity having a second concentration greater than the first concentration; Forming a second metal layer over the second impurity amorphous silicon layer; Forming the source and drain electrodes spaced apart from the data line formed of the second metal layer by patterning the second metal layer and the second and first impurity amorphous silicon layers and microcrystalline silicon layers thereunder, the source And forming an ohmic contact layer made of the second impurity amorphous silicon layer and the second buffer pattern made of the first impurity amorphous silicon layer and the first buffer pattern made of the microphone crystalline silicon layer under each drain electrode. Steps.

The forming of the second impurity amorphous silicon layer including the first impurity amorphous silicon layer including the microcrystalline silicon layer and the impurity having a first concentration and the impurity having a second concentration greater than the first concentration may include: Positioning the substrate on which the interlayer insulating film is formed in the vacuum chamber of the plasma chemical vapor deposition apparatus; Forming the microcrystalline silicon layer on the interlayer insulating film by performing plasma chemical vapor deposition after making the inside of the vacuum chamber into a first mixed gas atmosphere; Forming the first impurity amorphous silicon layer on the microcrystalline silicon layer by subjecting the inside of the vacuum chamber to a second mixed gas atmosphere and performing plasma chemical vapor deposition; And forming the second impurity amorphous silicon layer on the first impurity amorphous silicon layer by subjecting the inside of the vacuum chamber to a third mixed gas atmosphere and performing plasma chemical vapor deposition.

In addition, the first mixed gas atmosphere is a mixed gas atmosphere of hydrogen (H 2 ) and silane gas (SiH 4 ), the flow rate of the hydrogen (H 2 ) in the vacuum chamber is 950sccm to 1050sccm, the silane gas ( The flow rate of the SiH 4 ) in the vacuum chamber is 9.5sccm to 10.5sccm.

The second mixed gas atmosphere is a mixed gas atmosphere of hydrogen (H 2 ), silane gas (SiH 4 ), and phosphine gas (PH 3), and the injected flow rate of the hydrogen (H 2 ) in the vacuum chamber is 145 sccm to 155 sccm, the flow rate of the silane gas (SiH 4 ) in the vacuum chamber is 37sccm to 43sccm, and the flow rate of the phosphine gas (PH3) in the vacuum chamber is 0.28sccm to 0.32sccm.

The third mixed gas atmosphere is a mixed gas atmosphere of hydrogen (H 2 ), silane gas (SiH 4 ), and phosphine gas (PH 3), and the injected flow rate of the hydrogen (H 2 ) in the vacuum chamber is 145 sccm to 155 sccm, the flow rate of the silane gas (SiH 4 ) in the vacuum chamber is 37sccm to 43sccm, and the flow rate of the phosphine gas (PH3) in the vacuum chamber is 0.37sccm to 0.83sccm.

In addition, phosphorus (P) as an impurity in the first impurity amorphous silicon layer has a concentration less than 1%, and phosphorus (P) as an impurity in the second impurity amorphous silicon layer has a concentration of 1% to 2%. It is characteristic.

The forming of a gate insulating layer and an active layer of pure polysilicon in an island form sequentially stacked on the device region over the gate metal layer may include sequentially forming a first insulating layer and a pure amorphous silicon layer on the entire surface of the gate metal layer. Forming; Performing a crystallization process to crystallize the pure amorphous silicon layer into a pure polysilicon layer; Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness over the pure polysilicon layer; Forming the gate insulating layer and the pure polysilicon pattern sequentially in an island form on the gate metal layer by removing the pure polysilicon layer and the first insulating layer exposed outside the first and second photoresist patterns; Exposing one surface of the pure polysilicon pattern by ashing to remove the second photoresist pattern of the second thickness; Forming an active layer of pure polysilicon on the gate insulating film by removing the pure polysilicon pattern exposed to the outside of the second photoresist pattern; Removing the second photoresist pattern.

The gate metal layer may be formed of a metal material having a high melting point of 800 ° C. or higher. In this case, the metal material having a high melting point may include molybdenum (Mo) and molybdenum (MoTi) alloys. , Copper (Cu), copper alloy (Cu Alloy) is characterized by any one.

The first and second buffer patterns and the ohmic contact layer may be exposed through the active contact hole before forming the source and drain electrodes spaced apart from each other. And performing a BOE (Buffered Oxide Etchant) cleaning to remove the native oxide film formed on the surface of the active layer.

In addition, the gate line may be formed such that an end thereof is in contact with the gate insulating layer.

The method may also include forming a buffer layer on the entire surface of the substrate before forming the gate metal layer on the substrate.

An array substrate according to an embodiment of the present invention includes a gate electrode formed in the device region on a substrate on which a pixel region including an device region is defined; A gate insulating film formed in an island shape on the gate electrode; An active layer of pure polysilicon formed while exposing an edge of the gate insulating film over the gate insulating film; A gate wiring formed on a boundary between the pixel region and the double layer structure having a lower layer made of a same material and a top layer made of a metal material in contact with the gate electrode on the substrate and forming the gate electrode; An interlayer insulating film formed over the gate wiring and the active layer and having an active contact hole exposing the active layer on both sides of a center portion of the active layer; First and second buffer patterns and ohmic contact layers sequentially contacting the active layers and spaced apart from each other through the active contact holes on the interlayer insulating layer; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other; A data line connected to the source electrode on the interlayer insulating layer, the data line being defined to cross the gate line to define the pixel area; A protective layer formed over the source and drain electrodes and the data line and having a drain contact hole exposing the drain electrode; And a pixel electrode formed in the pixel area in contact with the drain electrode over the passivation layer.

In this case, the first buffer pattern is made of micro crystalline silicon, the second buffer pattern is made of first impurity amorphous silicon containing impurities of a first concentration, and the ohmic contact layer is made of a first larger than the first concentration. It is made of a second impurity amorphous silicon containing a second concentration of impurities, wherein the first concentration is less than 1%, the second concentration is characterized in that 1% to 2%.

In addition, the first buffer pattern has a thickness of 50 kPa to 300 kPa, and the second buffer pattern and the ohmic contact layer has a thickness of 50 kPa to 100 kPa, respectively.

In addition, the gate line is characterized in that the end is formed so as to be in contact with the gate insulating film.

By the method of manufacturing the array substrate according to the present invention, the active layer is not exposed to dry etching, and thus, surface damage does not occur, thereby preventing the thin film transistor characteristic from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

The array substrate manufactured by the manufacturing method according to the present invention comprises a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the mobility characteristics by several tens to several hundred times compared to one array substrate.

Since the active layer of polysilicon is used as the semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In addition, an off current characteristic is improved by providing a first silicon pattern microcrystallized and an amorphous silicon pattern lightly doped with impurities between an active layer of polysilicon and an ohmic contact layer made of amorphous silicon heavily doped with impurities.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.
2A through 2E are cross-sectional views illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;
3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor including polysilicon as a semiconductor layer.
4A to 4L are cross-sectional views illustrating manufacturing processes of one pixel region, a gate pad portion, and a data pad portion including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

4A through 4O are cross-sectional views illustrating manufacturing processes of a pixel area, a gate pad part, and a data pad part including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention. In this case, for convenience of description, the device region TrA and the gate pad electrode are formed in the portion where the thin film transistor Tr is formed in each pixel region P, and the gate pad portion GPA and the data pad electrode are formed. The part to be defined is defined as a data pad part DPA.

First, as shown in FIG. 4A, a thickness of about 1000 kV to 3000 kPa is obtained by depositing an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiNx) on a transparent insulating substrate 101, for example, a glass substrate. A buffer layer 102 is formed.

According to a feature of the present invention, a solid phase crystallization (SPC) process is performed in a subsequent process, and the solid phase crystallization (SPC) process requires a high temperature of 600 ° C to 800 ° C. In this case, when the substrate 101 is exposed to a high temperature atmosphere, alkali ions may be eluted from the surface of the substrate 101 to degrade the characteristics of the component made of polysilicon. Thus, the buffer layer 102 may be removed to prevent such a problem. To form.

Next, a metal material having a high melting point of 800 ° C. or higher on the buffer layer 102, for example, molybdenum alloy (Mo alloy) including molybdenum (Mo) and molybdenum titanium (MoTi), copper (Cu), and copper alloy (Cu Alloy). ) To form a gate metal layer 104 having a thickness of about 100 ~ 1000Å.

Molybdenum (Mo) and molybdenum alloys (MoTi), copper (Cu), and copper alloys containing them have higher resistance values per unit area than low-resistance metal materials, but within a temperature range above the crystallization temperature and below the melting point, The experiment showed that the degree was very small, voids did not occur inside, and the degree of expansion and contraction was relatively small with respect to a sudden change in temperature.

Thereafter, the first insulating layer 108 and the pure amorphous silicon layer 111 are formed by sequentially depositing or applying an insulating material and pure amorphous silicon on the gate metal layer 104 sequentially.

In this case, the pure amorphous silicon layer 111 is formed to a thickness of 1000 kPa or more in consideration of the conventional etching to be exposed to dry etching proceeds to form an ohmic contact layer spaced apart from each other to remove some thickness from the surface. In the case of the present invention, the region in which the channel of the active layer (115 of FIG. 4O) of pure polysilicon finally formed through the pure amorphous silicon layer 111 is formed is subjected to dry etching to form a semiconductor layer contact hole (FIG. In the step of forming 125a and 125b) of 4o, an interlayer insulating film (123 of FIG. 4o) serving as an etch stopper is provided, thereby not being exposed to dry etching.

Therefore, the dry etching does not cause a problem such that the thickness of the portion in which the channel is formed in the active layer (115 in FIG. 4O) becomes thin. Therefore, the dry etching may be performed at a thickness of 300 kPa to 1000 kPa, which may serve as an active layer. It is characterized by.

In this case, the first insulating layer 108 is made of an insulating material, for example, silicon oxide (SiO 2 ) or silicon nitride (SiNx), which is an inorganic insulating material, and has a thickness of 500 kPa to 4000 kPa.

Next, as shown in FIG. 4B, the pure amorphous silicon layer (111 in FIG. 4A) is crystallized by performing a crystallization process to improve the mobility characteristics and the like of the pure amorphous silicon layer (111 in FIG. 4A). The polysilicon layer 113 is formed.

In this case, it is preferable that the crystallization process is a crystallization process using solid phase crystallization (SPC) or a laser.

The solid phase crystallization (SPC) process, for example, thermal crystallization (Thermal Crystallization) through heat treatment in an atmosphere of 600 ℃ to 800 ℃ or alternating magnetic field crystallization (Alternating Magnetic in a temperature atmosphere of 600 ℃ to 700 ℃ using an alternating magnetic field crystallization device It is preferable that the field crystallization process, and crystallization using a laser is preferably Excimer Laser Annealing (ELA).

Next, as shown in FIG. 4C, a photoresist is applied onto the pure polysilicon 112 to form a photoresist layer (not shown), and the light transmitting region and blocking of the photoresist layer (not shown). The light transmittance is smaller than the transmission area (not shown) and larger than the blocking area (not shown) by adjusting the amount of light passing through the area (not shown) and the slit form, or further comprising a plurality of coating films. Diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a transmission area (not shown).

Subsequently, by developing the exposed photoresist layer (not shown), a portion of the portion where the gate insulating layer 109 of FIG. 4L should be formed on the pure polysilicon layer 112 corresponding to the device region TrA (to be formed later) The first photoresist pattern 191a having the first thickness is formed to correspond to the active layer of the pure polysilicon (the portion not overlapping with 115 of FIG. 4L), and the gate insulating layer 109 of FIG. 4O is formed. The second photoresist pattern 191b having a second thickness that is thicker than the first thickness is formed to correspond to the portion where the active layer (115 in FIG. 4O) is to be formed.

Accordingly, the second photoresist pattern 191b having the second thickness is formed on the pure polysilicon layer 112 to correspond to the central portion of the device region TrA. 191b) first photoresist patterns 191a having the first thickness are formed at both sides. Thus, forming the first photoresist pattern 191a having the first thickness and the second photoresist pattern 191b having the second thickness may be performed by forming a gate insulating film on both sides of the active layer (115 in FIG. 4L) of pure polysilicon. (109 in FIG. 4L) is exposed.

Next, as shown in FIG. 4D, the pure polysilicon layer 112 shown in FIG. 4C and the first inorganic insulating layer below it are exposed to the outside of the first and second photoresist patterns 191a and 191b. 108c of 4c is sequentially etched to form a gate insulating layer 109 and a pure polysilicon pattern 113 sequentially stacked in an island form on the gate metal layer 104 in the device region TrA.

In this case, the pure polysilicon layer (112 in FIG. 4C) and the first inorganic insulating layer (108 in FIG. 4C) are included in regions other than the device region TrA including the gate and data pad portions GPA and DPA. All of these are removed, and the gate metal layer 104 is exposed.

Next, as shown in FIG. 4E, the first photoresist pattern having the first thickness is ashed by ashing the substrate 101 on which the gate insulating layer 109 and the pure polysilicon pattern 113 are formed. By removing 191a of FIG. 4D, both surfaces of the pure polysilicon pattern 113 are exposed to the outside of the second photoresist pattern 191b in the device region TrA. At this time, the thickness of the second photoresist pattern 191b is also reduced by ashing, but still remains on the pure polysilicon pattern 113.

Next, as illustrated in FIG. 4F, the pure polysilicon pattern (113 of FIG. 4E) exposed to the outside of the second photoresist pattern 191b is etched and removed to the lower portion of the second photoresist pattern 191b. An active layer 115 of pure polysilicon is formed, and at the same time, the gate insulating layer 109 is exposed to both sides of the active layer 115 of pure polysilicon.

Next, as shown in FIG. 4G, the pure polysilicon is removed by performing a strip to remove the second photoresist pattern (191b of FIG. 4F) remaining on the active layer 115 of the pure polysilicon. The active layer 115 is exposed.

Next, as shown in FIG. 4H, a first metal material such as aluminum (Al), aluminum alloy (AlNd), and copper (Cu) is exposed on the exposed active layer 115 and the gate metal layer 104 of pure polysilicon. ), Copper alloy, molybdenum (Mo) and chromium (Cr) any one or two or more of the continuous deposition to form a first metal layer 117.

In this case, when the first metal layer 117 forms a single layer, each of the first metal materials may form one single layer. In addition, when the first metal layer 117 forms a binary layer, for example, aluminum (Al) / molybdenum (Mo), aluminum alloy (AlNd) / molybdenum (Mo), copper (Cu) / molybdenum (Mo), copper alloy It may have a configuration of / molybdenum (Mo). In addition, when the first metal layer forms a triple layer, for example, molybdenum (Mo) / aluminum alloy (AlNd) / molybdenum (Mo), molybdenum (Mo) / aluminum / molybdenum (Mo), molybdenum (Mo) / copper (Cu ) And molybdenum (Mo).

In the drawings, for the sake of convenience, the first metal layer 117 is formed as a single layer structure as an example.

Subsequently, a photoresist is applied on the first metal layer 117 to form a second photoresist layer (not shown), and exposure and development are performed on the first metal layer 117, thereby forming a gate wiring at the boundary of each pixel region P (FIG. 4L). A third photoresist pattern 193 corresponding to a portion where the gate 120 and the gate and the data pad electrodes GPA and DPA are to be formed and corresponding to a portion where the gate and data pad electrodes 121 and 122 of FIG. 4L are to be formed. do.

Next, as illustrated in FIG. 4I, the first metal layer 117 of FIG. 4H and the gate metal layer 104 below it, which are exposed to the outside of the third photoresist pattern 193, are etched and removed. A gate electrode 106 made of a metal material having a common melting point is formed in the device region TrA on the buffer layer 102.

At the same time, a gate wiring 120 is formed on the buffer layer 102 at the boundary of the pixel region P and in contact with the gate electrode 106. In this case, the gate wiring 120 has a double layer structure including a lower layer 107 made of a metal material having a high melting point and an upper layer 118 made of a first metal material in an area except the device region TrA. When the upper layer 118 made of one metal material is formed of two or more metal materials of the first metal material, the upper layer 118 may have a substantially multilayer structure.

In addition, in the gate and data pad parts GPA and DPA, the gate and data pad electrodes 121 having a double layer structure made of a material including the gate metal pad 107 and the first metal pad 119 on the buffer layer 102. 122). In this case, the gate pad electrode 121 may be connected to one end of the gate line 120, and the data pad electrode 122 may have an island shape in the data pad part DPA.

Meanwhile, in the device region TrA, the gate wiring 120 is formed of only the upper layer 118 made of the first metal material, and the gate wiring 120 made of only the upper layer 118 is made of the metal having the high melting point. The gate electrode 106 may be formed in contact with the gate electrode 106 made of a material, and an end thereof may overlap the gate insulating layer 109 formed on the gate electrode 106.

Next, as shown in FIG. 4J, the third photoresist pattern remaining on the gate line 120 and the gate and data pad electrodes 121 and 122 is removed by performing a strip.

Thereafter, an inorganic insulating material, for example, silicon oxide (SiO 2 ) or silicon nitride (SiNx) is deposited on the gate line 120 and the gate and data pad electrodes 121 and 122 to form a second inorganic layer having a single layer structure. A second inorganic insulating layer (not shown) having a double layer structure is formed by forming an insulating layer (not shown) or by depositing the two inorganic insulating materials in succession.

Thereafter, the second inorganic insulating layer (not shown) formed on the entire surface of the substrate 101 is coated with a photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, etc. The mask process is performed by patterning.

By the patterning of the second inorganic insulating layer (not shown), in each device region TrA, the active layer 115 of polysilicon is moved to both sides thereof based on the center of the active layer 115 of pure polysilicon. Exposed first and second active contact holes 125a and 125b are formed. In this case, the second inorganic insulating layer (not shown) provided with the first and second active contact holes 125a and 125b forms an interlayer insulating layer 123.

On the other hand, the interlayer insulating film 123 formed to have the shape as described above corresponds to the central portion (channel region) of the active layer 115 of the pure polysilicon to cover the active layer 115 of the pure polysilicon. It serves as a function, and serves as an insulating layer corresponding to other areas.

In addition, the formation of the first and second active contact holes 125a and 125b in the interlayer insulating layer 123 is mainly performed by dry etching. In this case, when the dry etching of the interlayer insulating layer 123 is performed, the active layer 115 of the pure polysilicon may also be used to dry etching for forming the first and second active contact holes 125a and 125b in the interlayer insulating layer 123. Exposed.

However, both etching gases (eg, silicon oxide and silicon nitride CF 4 , CF 3 , CF 2 ) used for dry etching inorganic insulating materials and etching gases (amorphous silicon and polysilicon) used for dry etching semiconductor materials Cl 2 or BCl 3 ) are very different and have little effect on each other between these two materials.

Accordingly, the active layer 115 of pure polysilicon has little change in thickness even if it is exposed to dry etching for forming the first and second active contact holes 125a and 125b in the interlayer insulating layer 123. It does not matter.

Meanwhile, even if a predetermined thickness change occurs in the active layer 115 of pure polysilicon by the dry etching, a portion of the first and second active contact holes 125a and 125b is substantially formed in the channel. It does not matter because it is not.

Next, as shown in FIG. 4K, the active layer 115 has first and second active contact holes 125a and 125b corresponding to the active layer 115 of the pure polysilicon and exposes the active layer 115 of the pure polysilicon. In the central portion of 115, a substrate having the interlayer insulating film 123 serving as an etch stopper is positioned inside the vacuum chamber of the plasma enhanced chemical vapor deposition (PECVD).

Thereafter, amorphous silicon including micro-crystallized silicon and an impurity having a first concentration and an amorphous silicon including an impurity having a second concentration greater than the first concentration are disposed on the entire surface of the substrate 101 on the interlayer insulating layer 123. By sequentially and sequentially depositing, the microcrystalline silicon layer 127a, the first impurity amorphous silicon layer 127b, and the second impurity amorphous silicon layer 127c are formed on the interlayer insulating layer 123.

At this time, since the three material layers 127a, 127b, and 127c are all semiconductor materials, all of these semiconductor materials are the same one vacuum through plasma enhanced chemical vapor deposition (CVD) equipment (not shown). By changing only the reaction gas and the input flow rate in the chamber 195 can be formed continuously without exposure to the atmosphere.

The microcrystalline silicon layer 127a may be formed by making the inside of the vacuum chamber 195 in a mixed gas atmosphere of hydrogen (H 2 ) and silane gas (SiH 4 ), and then performing plasma chemical vapor deposition. In this case, the input flow rate of the hydrogen (H 2 ) in the vacuum chamber 195 is 950sccm to 1050sccm, and the input flow rate of the silane gas (SiH 4 ) in the vacuum chamber is 9.5sccm to 10.5sccm.

In addition, the first impurity amorphous silicon layer 127b makes the inside of the vacuum chamber 195 a mixed gas atmosphere of hydrogen (H 2 ), silane gas (SiH 4 ), and phosphine gas (PH 3), and then plasma chemistry. It can form by performing vapor deposition. In this case, the input flow rate of the hydrogen (H 2 ) in the vacuum chamber 195 is 145sccm to 155sccm, and the input flow rate of the silane gas (SiH 4 ) in the vacuum chamber is 37sccm to 43sccm, and the phosphine gas forms impurity. The input flow rate in the vacuum chamber of (PH3) is characterized in that 0.28sccm to 0.32sccm. The first impurity amorphous silicon layer formed by the mixed gas atmosphere having such an input flow rate is characterized in that the phosphorus (P) as an impurity has a doping concentration of less than 1%.

In addition, the second impurity amorphous silicon layer 127c may be formed by changing only the flow rate of the phosphine gas PH3 in the same mixed gas atmosphere in which the first impurity amorphous silicon layer 127b is formed. That is, the phosphine may be supplied with the hydrogen (H 2 ) and silane gas (SiH 4 ) in the vacuum chamber 195 while maintaining the same level as that of the first impurity amorphous silicon layer 127b. The second impurity amorphous silicon layer 127c may be formed by changing the flow rate of the gas PH3 into the vacuum chamber 195 from 0.37 sccm to 0.83 sccm. In the second impurity amorphous silicon layer 127c formed by the mixed gas atmosphere having such an input flow rate, phosphorus (P), which is an impurity, has a doping concentration of 1% to 2%.

In this case, the microcrystalline silicon layer 127a may have a thickness of about 50 GPa to 300 GPa, and the first impurity amorphous silicon layer 127b and the second impurity amorphous silicon layer 127c may each have a thickness of about 50 GPa to 100 GPa. It is preferable to form so that it may have.

Meanwhile, buffered oxide etchant (BOE) cleaning may be performed before the microcrystalline silicon layer 127a is formed on the interlayer insulating layer 123. This is to completely remove the natural oxide film (not shown) that may be formed by exposing the surface of the active layer 115 of pure polysilicon exposed through the first and second active contact holes 125a and 125b to air. to be.

Next, as shown in FIG. 4L, the second metal layer 170 is deposited by depositing either a second metal material, for example, molybdenum (Mo) or molybdenum (MoTi), on the second impurity amorphous silicon layer 127c. ).

Next, as shown in FIG. 4M, the second metal layer (170 in FIG. 4L), the second impurity amorphous silicon layer (127c in FIG. 4L) and the first impurity amorphous silicon layer (127c in FIG. 4L) located below it. And patterning the micro crystalline silicon layer (127a of FIG. 4L) by performing a mask process so as to cross the gate line 120 at the boundary of each pixel region P on the interlayer insulating layer 123 to cross the pixel region P. The data line 130 is defined.

In this case, as described above, the second impurity amorphous silicon layer (127c in FIG. 4L), the first impurity amorphous silicon layer (127c in FIG. 4L), and the microcrystalline silicon layer may be formed under the data line 130. The first, second, and third dummy patterns 171a, 171b, and 171c made of the same material forming 127a of FIG. 4L are formed.

At the same time, in the device region TrA, source and drain electrodes 133 and 136 spaced apart from each other are formed on the interlayer insulating layer 123, and a lower portion of each of the source and drain electrodes 133 and 136 is formed. An ohmic contact layer 129 made of impurity amorphous silicon, a first buffer pattern 128a made of first impurity amorphous silicon, and a second buffer pattern 128b made of micro crystalline silicon are formed below.

In this case, the second buffer pattern 128b is in contact with the active layer 115 of pure polysilicon through the first and second active contact holes 125a and 125b, respectively.

The source electrode 133 and the data line 130 formed in the device region TrA are connected to each other. In this case, the ohmic contact layer 128 and the first and second buffer patterns 128a and 128b formed under each of the source and drain electrodes 133 and 136 spaced apart from each other may be disposed in the source and drain electrodes 133 and 136. ) Are completely overlapped and formed with the same planar shape and planar area.

Meanwhile, in the array substrate according to the exemplary embodiment of the present invention, the data line 130, the source and drain electrodes 133 and 136, the ohmic contact layer 129, and the first and second buffer patterns 128a and 128b are provided. The interlayer insulating film 123 serving as an etch stopper is formed to correspond to the central portion of the active layer 115 of pure polysilicon in which the channel is formed in the on state of the thin film transistor Tr in the process of forming the film. Therefore, after the source and drain electrodes 133 and 136 are formed, the active layer 115 of the pure polysilicon is not affected at all during dry etching for patterning the ohmic contact layer 129.

Therefore, it can be seen that the surface damage of the active layer in the portion where the channel is formed by the dry etching process for ohmic contact layer patterning, which is a problem mentioned in the related art, does not occur.

On the other hand, the gate electrode 106 of the impurity polysilicon, the gate insulating film 109, the active layer 115 of pure polysilicon, and the like are sequentially stacked on the device region TrA by the above-described process. The interlayer insulating film 123, the second buffer pattern 128b of microcrystalline silicon, the first buffer pattern 128a of the first impurity amorphous silicon, the ohmic contact layer 129 of the second impurity amorphous silicon, and a source The drain electrodes 133 and 136 form a thin film transistor Tr.

The thin film transistor Tr having such a structure includes a second buffer pattern 128b of microcrystalline silicon between the impurity amorphous ohmic contact layer 129 having the first concentration and the active layer 115 of pure polysilicon. And the first buffer pattern 128a of the first impurity amorphous silicon can improve the off current (I off ) characteristic, that is, reduce the off current magnitude.

When the active layer 115 of polysilicon and the ohmic contact layer 129 made of the second impurity amorphous silicon are in direct contact with each other, the contact resistance at the junction is relatively low, resulting in a relatively large electric field, which causes leakage current at the interface. By increasing, the magnitude of the off current I off increases.

However, in the array substrate 101 according to the embodiment of the present invention, the microcrystalline second buffer pattern 128b having lower conductivity than the active layer 115 of the polysilicon between the active layers 115 of the polysilicon. ) And a first buffer pattern 128a of first impurity amorphous silicon having a lower conductivity than that of the ohmic contact layer 129 and having a lower conductivity. Therefore, the off current can be reduced by reducing the electric field size at the boundary by having a relatively large contact resistance at the junction of each component.

On the other hand, although not shown in the drawings, when the above-described array substrate 101 is manufactured as an array substrate for an organic light emitting device, the data on the same layer on which the data wiring 130 is formed in parallel with the data wiring 130 The power supply wiring (not shown) may be further spaced apart from the wiring 130 by a predetermined distance, and the thin film transistor Tr connected to the data wiring 130 and the gate wiring 120 may be formed in each pixel region P. In addition to the switching thin film transistor, it has the same structure and may further form a driving thin film transistor (not shown) connected to the power line (not shown) and the switching thin film transistor (Tr).

Next, as shown in FIG. 4N, the substrate 101 on which the data line 130, the source and drain electrodes 133 and 136, the ohmic contact layer 129, and the first and second buffer patterns 128a and 128b are formed. For example, an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiNx) is deposited on the source and drain electrodes 133 and 136 as an insulating material, or benzocyclobutene (BCB) or photoacryl ( The protective layer 140 is formed on the entire surface of the substrate 101 by coating an organic insulating material such as photo acryl).

Subsequently, a mask process is performed on the protective layer 140 and the interlayer insulating layer 123 disposed below the drain layer to expose the drain electrode 136 of the thin film transistor Tr by patterning it. To form.

In this case, when the protective layer 140 is patterned, the gate pad electrode 121 may be patterned together with the interlayer insulating layer 123 in the gate and data pad parts GPA and DPA in addition to the drain contact hole 143. Of the gate pad contact hole 144 exposing the gate pad contact hole 144, the data pad contact hole 145 exposing both ends of the data pad electrode 121, and the auxiliary data pad contact hole 146 and the data line 130. A data line contact hole 147 exposing one end is formed.

Next, as shown in FIG. 4O, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the protective layer 140 or a metal. For example, a conductive material layer (not shown) is formed by depositing a molybdenum alloy (MoTi) such as molybdenum (MoTi), and a mask process is performed on the drain contact hole 143 in each pixel region P. The pixel electrode 150 in contact with the drain electrode 136 is formed through the. In this case, the pixel electrode 150 is formed to overlap the gate wiring 120 of the front end with the interlayer insulating film 123 and the protective layer 140 interposed therebetween, so that the overlapping front end gate wiring 120 and the interlayer overlap with each other. The insulating layer 123, the protective layer 140, and the pixel electrode 150 form a storage capacitor StgC.

At the same time, in the gate pad part GPA, a gate auxiliary pad electrode 152 is formed on the passivation layer 140 to contact the gate pad electrode 121 through the gate pad contact hole 145. In the data pad part DPA, a data auxiliary pad electrode 154 is formed on the protective layer 140 to contact the data pad electrode 122 through the data pad contact hole 146. The data pad electrode 122 and the data through the auxiliary data pad contact hole 146 exposing the data pad electrode 122 and the data wire contact hole 147 exposing one end of the data line 130. The array substrate 101 according to the exemplary embodiment of the present invention is completed by forming the data connection pattern 156 that is in contact with the wiring 130.

Meanwhile, in the first exemplary embodiment of the present invention, the data pad electrode 122 and the data line 130 are dualized and formed on different layers, respectively, and the data electrically connecting these two components 122 and 130. Although the connection pattern 156 is formed, as a modification, the data pad electrode 122 is formed to be connected to the data line 130 in the step of forming the data line 130. 156 may be omitted.

Although not shown in the drawings, when a driving thin film transistor (not shown) is formed in each of the pixel regions P, the thin film transistor Tr (which forms a switching thin film transistor) formed in the device region TrA is formed. The drain electrode 136 does not contact the pixel electrode 150, but instead, the drain electrode 136 of the driving thin film transistor (not shown) contacts the pixel electrode 150 to be electrically connected to the drain electrode 136.

When a thin film transistor Tr (which forms a switching thin film transistor) connected to the gate and data lines 120 and 130 and a driving thin film transistor (not shown) are formed in the pixel region P in the device region TrA, An array substrate having such a configuration forms an array substrate for an organic light emitting device.

In addition, when manufactured as an array substrate for an organic light emitting diode, although not shown in the drawing, an organic insulating material is coated on the pixel electrode 150 and the thin film transistor Tr to form an organic insulating layer (not shown), The mask process may be patterned to further form a bank (not shown) overlapping the edge of the pixel electrode 150 along the boundary of each pixel region P. FIG.

101: substrate
102: buffer layer
105: gate electrode
106: bottom layer (of gate wiring)
107: metal pad at the melting point (of the gate and data pad electrodes)
109: gate insulating film
115: active layer of pure polysilicon
118: top layer (of gate wiring)
119: first metal pad (of gate and data pad electrodes)
120: gate wiring
121: gate pad electrode
122: data pad electrode
123: interlayer insulating film
125a and 125b: first and second active contact holes
127a: microcrystalline silicon layer
127b: first impurity amorphous silicon layer
127c: second impurity amorphous silicon layer
DPA: Data Pad
GPA: Gate Pad
P: pixel area
TrA: device area

Claims (17)

Forming a gate metal layer on the substrate on which the pixel region including the device region is defined;
Forming a gate insulating film and an active layer of pure polysilicon in an island form sequentially stacked on the gate metal layer in the device region;
A gate wiring having a multi-layer structure by forming a first metal layer over the active layer of the pure polysilicon and patterning the first metal layer and the gate metal layer, and connected to the gate wiring under the gate insulating layer in the device region. Forming a gate electrode;
Depositing and patterning an insulating material over the gate wiring and the active layer to form an interlayer insulating film having active contact holes that expose the active layer to both sides of the active layer;
Source and drain electrodes are sequentially stacked on the interlayer insulating layer and are spaced apart from the first and second buffer patterns and the ohmic contact layer in contact with the active layer and spaced apart from each other through the active contact hole. And simultaneously forming a data line connected to the source electrode and crossing the gate line at a boundary of the pixel area over the interlayer insulating film;
Forming a protective layer having a drain contact hole exposing the drain electrode over the data line and a source and drain electrode;
Forming a pixel electrode in contact with the drain electrode in each pixel region by depositing and patterning a transparent conductive material on the entire surface over the protective layer;
Method of manufacturing an array substrate comprising a.
The method of claim 1,
Forming the first and second buffer patterns and the ohmic contact layer and the source and drain electrodes spaced apart from each other and the data line,
Forming a first impurity amorphous silicon layer including a micro crystalline silicon layer and an impurity having a first concentration and a second impurity amorphous silicon layer including an impurity having a second concentration greater than the first concentration above the interlayer insulating layer; Wow;
Forming a second metal layer over the second impurity amorphous silicon layer;
Forming the source and drain electrodes spaced apart from the data line formed of the second metal layer by patterning the second metal layer and the second and first impurity amorphous silicon layers and microcrystalline silicon layers thereunder, the source And forming an ohmic contact layer made of the second impurity amorphous silicon layer and the second buffer pattern made of the first impurity amorphous silicon layer and the first buffer pattern made of the microphone crystalline silicon layer under each drain electrode. step
Method of manufacturing an array substrate comprising a.
The method of claim 2,
Forming a second impurity amorphous silicon layer comprising a first impurity amorphous silicon layer comprising an impurity having a first concentration and the micro crystalline silicon layer and an impurity having a second concentration greater than the first concentration,
Placing the substrate on which the interlayer dielectric film is formed in a vacuum chamber of a plasma chemical vapor deposition apparatus;
Forming the microcrystalline silicon layer on the interlayer insulating film by performing plasma chemical vapor deposition after making the inside of the vacuum chamber into a first mixed gas atmosphere;
Forming the first impurity amorphous silicon layer on the microcrystalline silicon layer by subjecting the inside of the vacuum chamber to a second mixed gas atmosphere and performing plasma chemical vapor deposition;
Forming the second impurity amorphous silicon layer on the first impurity amorphous silicon layer by subjecting the inside of the vacuum chamber to a third mixed gas atmosphere and performing plasma chemical vapor deposition.
Method of manufacturing an array substrate comprising a.
The method of claim 3, wherein
The first mixed gas atmosphere is a mixed gas atmosphere of hydrogen (H 2 ) and silane gas (SiH 4 ),
The flow rate of the hydrogen (H 2 ) in the vacuum chamber is 950sccm to 1050sccm,
The flow rate of the silane gas (SiH 4 ) in the vacuum chamber is a manufacturing method of the array substrate, characterized in that 9.5sccm to 10.5sccm.
The method of claim 4, wherein
The second mixed gas atmosphere is
Mixed gas atmosphere of hydrogen (H 2 ), silane gas (SiH 4 ), and phosphine gas (PH3),
The flow rate of the hydrogen (H 2 ) in the vacuum chamber is 145sccm to 155sccm,
The injected flow rate of the silane gas (SiH 4 ) in the vacuum chamber is 37sccm to 43sccm,
And a flow rate of the phosphine gas (PH3) in the vacuum chamber is 0.28 sccm to 0.32 sccm.
The method of claim 5, wherein
The third mixed gas atmosphere is
Mixed gas atmosphere of hydrogen (H 2 ), silane gas (SiH 4 ), and phosphine gas (PH3),
The flow rate of the hydrogen (H 2 ) in the vacuum chamber is 145sccm to 155sccm,
The injected flow rate of the silane gas (SiH 4 ) in the vacuum chamber is 37sccm to 43sccm,
And a flow rate of the phosphine gas (PH3) in the vacuum chamber is 0.37 sccm to 0.83 sccm.
The method according to claim 6,
Phosphorus (P) as an impurity in the first impurity amorphous silicon layer has a concentration less than 1%, and phosphorus (P) as an impurity in the second impurity amorphous silicon layer has a concentration of 1% to 2%. Method of manufacturing an array substrate.
The method of claim 1,
Forming a gate insulating film and an active layer of pure polysilicon in an island form sequentially stacked on the device region over the gate metal layer,
Sequentially forming a first insulating layer and a pure amorphous silicon layer on the entire surface of the gate metal layer;
Performing a crystallization process to crystallize the pure amorphous silicon layer into a pure polysilicon layer;
Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness over the pure polysilicon layer;
Forming the gate insulating layer and the pure polysilicon pattern sequentially in an island form on the gate metal layer by removing the pure polysilicon layer and the first insulating layer exposed outside the first and second photoresist patterns;
Exposing one surface of the pure polysilicon pattern by ashing to remove the second photoresist pattern of the second thickness;
Forming an active layer of pure polysilicon on the gate insulating film by removing the pure polysilicon pattern exposed to the outside of the second photoresist pattern;
Removing the second photoresist pattern
Method of manufacturing an array substrate comprising a.
The method of claim 1,
And the gate metal layer is formed of a metal material having a high melting point of 800 ° C. or higher.
The method of claim 9,
The metal material having a high melting point is any one of molybdenum alloy (Mo), including molybdenum (MoTi), molybdenum (MoTi), copper (Cu), copper alloy (Cu Alloy) Way.
The method of claim 1,
The active exposed through the active contact hole prior to forming source and drain electrodes spaced apart from the first and second buffer patterns and the ohmic contact layer in contact with the active layer and spaced apart from each other on the interlayer insulating layer; A method of manufacturing an array substrate, comprising performing a BOE (Buffered Oxide Etchant) cleaning to remove the native oxide film formed on the surface of the layer.
The method of claim 1,
And the gate line is formed such that an end thereof is in contact with the gate insulating layer and positioned above the gate insulating layer.
The method of claim 1,
Forming a buffer layer over the entire surface of the substrate prior to forming the gate metal layer on the substrate.
A gate electrode formed in the device region on the substrate on which the pixel region including the device region is defined;
A gate insulating film formed in an island shape on the gate electrode;
An active layer of pure polysilicon formed while exposing an edge of the gate insulating film over the gate insulating film;
A gate wiring formed on a boundary between the pixel region and the double layer structure having a lower layer made of a same material and a top layer made of a metal material in contact with the gate electrode on the substrate and forming the gate electrode;
An interlayer insulating film formed over the gate wiring and the active layer and having an active contact hole exposing the active layer on both sides of a center portion of the active layer;
First and second buffer patterns and ohmic contact layers sequentially contacting the active layers and spaced apart from each other through the active contact holes on the interlayer insulating layer;
Source and drain electrodes formed on the ohmic contact layers spaced apart from each other;
A data line connected to the source electrode on the interlayer insulating layer, the data line being defined to cross the gate line to define the pixel area;
A protective layer formed over the source and drain electrodes and the data line and having a drain contact hole exposing the drain electrode;
A pixel electrode formed in the pixel area in contact with the drain electrode on the passivation layer
Array substrate comprising a.
15. The method of claim 14,
The first buffer pattern is made of micro crystalline silicon,
The second buffer pattern is made of a first impurity amorphous silicon containing impurities of a first concentration,
The ohmic contact layer is made of a second impurity amorphous silicon containing impurities of a second concentration greater than the first concentration,
Wherein said first concentration is less than 1% and said second concentration is between 1% and 2%.
15. The method of claim 14,
The first buffer pattern has a thickness of 50 Å to 300 Å,
And the second buffer pattern and the ohmic contact layer each have a thickness of 50 ns to 100 ns.
15. The method of claim 14,
And the gate line is formed such that an end thereof is in contact with the gate insulating layer and positioned above the gate insulating layer.
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KR20170045423A (en) * 2015-10-16 2017-04-27 삼성디스플레이 주식회사 Thin film transistor array panel and method for manufacturing the same
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CN110690226A (en) * 2019-09-03 2020-01-14 武汉华星光电半导体显示技术有限公司 Array substrate and display panel

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KR20170045423A (en) * 2015-10-16 2017-04-27 삼성디스플레이 주식회사 Thin film transistor array panel and method for manufacturing the same
CN107342294A (en) * 2016-04-29 2017-11-10 三星显示有限公司 Transistor display panel and manufacturing method thereof
CN107342294B (en) * 2016-04-29 2024-03-08 三星显示有限公司 Transistor array panel
CN110690226A (en) * 2019-09-03 2020-01-14 武汉华星光电半导体显示技术有限公司 Array substrate and display panel
WO2021042606A1 (en) * 2019-09-03 2021-03-11 武汉华星光电半导体显示技术有限公司 Array substrate and display panel

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