KR20110058355A - Array substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate and manufacturing method thereof are provided to increase the property of a thin film transistor and to increase the movement property without a doping process when forming an active layer into a poly silicon. CONSTITUTION: A buffer layer forms a first impurity amorphous silicone layer(123) and a first inorganic insulating layer. The first impurity amorphous silicon layer crystallizes each impurity poly silicon layer in a solidification crystallization process. The first metal layer is formed on an active layer. The first metal layer forms a gate line by patterning the impurity poly silicon layer.

Description

Array substrate and method of manufacturing the same

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling the voltage on / off of each pixel, realizes resolution and video. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each pixel area on / off.

FIG. 1 is a cross-sectional view of a pixel area including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting display device.

As illustrated, the gate electrode 15 is disposed in the switching region TrA in the plurality of pixel regions P defined by the plurality of gate lines (not shown) and the data lines 33 intersecting on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. In addition, a pixel electrode 50 that is independent of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45 is formed on the passivation layer 42. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26. The thickness difference t1? T2 of the active layer 22 is due to a manufacturing method, and the characteristic difference of the thin film transistor Tr occurs due to the thickness difference t1? T2 of the active layer 22. Doing.

2A through 2E are cross-sectional views illustrating a process of forming a semiconductor layer, a source, and a drain electrode during a manufacturing process of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

First, as shown in FIG. 2A, the pure amorphous silicon layer 20 is formed on the substrate 11, and the impurity amorphous silicon layer 24 and the metal layer 30 are sequentially formed thereon. Thereafter, a photoresist is formed on the metal layer 30 to form a photoresist layer (not shown), and the photoresist is exposed using an exposure mask, and subsequently developed to correspond to a portion where the source and drain electrodes are to be formed. A first photoresist pattern 91 having a thickness is formed, and at the same time, a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed to correspond to the separation region between the source and drain electrodes. .

Next, as shown in FIG. 2B, the metal layer (30 of FIG. 2A) exposed to the outside of the first and second photoresist patterns 91 and 92, an impurity and a pure amorphous silicon layer below it (of FIG. 2A) 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top, and an impurity amorphous silicon pattern 25 and an active layer 22 below.

Next, as shown in FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by ashing. In this case, the first photoresist pattern (91 in FIG. 2B) having the third thickness forms the third photoresist pattern 93 while the thickness thereof is reduced, and remains on the source drain pattern 31.

Next, as illustrated in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching by removing the source drain pattern 31 of FIG. 2C exposed to the outside of the third photoresist pattern 93. To form. In this case, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the source and drain electrodes are dry-etched on the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the separation region between the source and drain electrodes 36 and 38. (36, 38) An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside of the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (Fig. Even a portion of the active layer 22 disposed below 25) of 2d may have a predetermined thickness etched at a portion where the impurity amorphous silicon pattern (25 of FIG. 2d) is removed. Therefore, the thickness difference (t1? T2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (25 of FIG. 2D) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22. This is to prevent this.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer (20 in FIG. 2A) forming the active layer 22 is sufficiently thick in consideration of the thickness of the active layer 22 that is etched and removed during the dry etching process for forming the ohmic contact layer 26. It should be deposited thick enough to have a thickness of 1000Å or more, which results in increased deposition time and reduced productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier is low at 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the fabrication of the array substrate 51 including the thin film transistor Tr, which is used as 55), the n + region 55b including high concentration of impurities in both sides of the first region 55a in the semiconductor layer 55 made of polysilicon. Or p + region (not shown). Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching, thereby preventing damage to the surface thereof, thereby improving characteristics of the thin film transistor. .

Furthermore, another object of the present invention is to provide a method of manufacturing an array substrate having a thin film transistor capable of improving a mobility property without forming a doping process while forming an active layer made of polysilicon.

Another object of the present invention is to provide a manufacturing method capable of manufacturing an array substrate having a thin film transistor having an active layer of polysilicon by a five-mask process.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, including: a buffer layer made of an inorganic insulating material, a first impurity amorphous silicon layer, and a first impurity on a substrate on which a pixel region including an element region is defined; Forming an inorganic insulating layer and a pure amorphous silicon layer; Performing a solid phase crystallization process to crystallize the first impurity amorphous silicon layer and the pure amorphous silicon layer into an impurity polysilicon layer and a pure polysilicon layer, respectively; Patterning the first inorganic insulating layer and the pure polysilicon layer over the impurity polysilicon layer to form an active layer in the device region exposing a gate insulating layer and both surfaces of the gate insulating layer as islands; A first metal layer is formed on the entire surface of the active layer, and the first metal layer and the impurity polysilicon layer are patterned to form a gate wiring at the boundary of the pixel region. Forming a gate electrode of impurity polysilicon in contact with the wiring; Depositing and patterning an inorganic insulating material over the gate wiring and the active layer to form an interlayer insulating film having active contact holes exposing the active layer to both sides of the active layer center; Forming an ohmic contact layer of impurity amorphous silicon and a source and drain electrode spaced apart from each other on the ohmic contact layer, the impurity amorphous silicon being in contact with the active layer and spaced apart from each other through the active contact hole, and simultaneously being disposed on the interlayer insulating film. Forming a data line connected to a source electrode and crossing the gate line at a boundary of the pixel region; And forming a pixel electrode in contact with one end of the drain electrode in each pixel region by depositing and patterning a transparent conductive material over the data line and the source and drain low electrodes.

Patterning the first inorganic insulating layer and the pure polysilicon layer over the impurity polysilicon layer to form an active layer exposing both surfaces of the gate insulating layer and the gate insulating layer in an island form in the device region, wherein the pure poly A first photoresist pattern having a first thickness is formed on the silicon layer to correspond to a portion where the active layer is formed, and corresponding to both edges of the gate insulating layer exposed to the outside of the active layer. Forming a second photoresist pattern having a second thickness less than one thickness; Sequentially removing the pure polysilicon layer and the inorganic insulating layer exposed to the outside of the first and second photoresist patterns to form the gate insulating layer and the pure polysilicon pattern in a stacked manner in the device region; Exposing both edges of the pure polysilicon pattern by ashing to remove the second photoresist pattern; Removing the polysilicon pattern exposed to the outside of the first photoresist pattern to form an active layer of pure polysilicon on the gate insulating film, the active layer of which is completely overlapped and exposes both edges of the gate insulating film; Removing the first photoresist pattern.

In addition, the solid state crystallization (SPC) process is characterized in that the alternating magnetic field crystallization using a thermal crystallization (Alternating Magnetic Field Crystallization) device or (Thermal Crystallization) through heat treatment.

In addition, the amorphous contact layer may be formed of pure amorphous silicon under the ohmic contact layer on the interlayer insulating layer having the active contact hole, and may have a thickness of 50 μs to 300 μm, and may be in contact with the active layer through the active contact hole and spaced apart from each other. Forming a barrier pattern.

In addition, before forming the ohmic contact layer, performing a BOE (Buffered Oxide Etchant) cleaning to remove the natural oxide film formed on the surface of the active layer exposed through the active contact hole.

The forming of the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring and an island-shaped data pad electrode. The forming of the interlayer insulating layer may include forming the gate pad electrode. Forming a gate pad contact hole exposing the gate pad contact hole and exposing the data pad electrode, wherein the forming of the pixel electrode is in contact with the gate pad electrode through the gate pad contact hole. And forming an auxiliary gate pad electrode and an auxiliary data pad electrode contacting the data pad electrode through the data pad contact hole and simultaneously contacting one end of the data line.

In addition, the gate line is formed so that the side end thereof is in contact with the gate insulating film is located above.

An array substrate according to the present invention includes a buffer layer formed on a substrate on which a pixel region including an element region is defined; A gate electrode of impurity polysilicon formed in the device region over the buffer layer; A gate insulating film formed in an island shape on the gate electrode; An active layer of pure polysilicon formed by exposing both edges of the gate insulating film over the gate insulating film; A gate wiring formed on a boundary of the pixel region with a double layer structure having a lower layer made of the same material forming the gate electrode and an upper layer made of a metal material in contact with the gate electrode over the buffer layer; An interlayer insulating film formed over the gate wiring and the active layer and having an active contact hole on both sides of the active layer to expose the active layer; An ohmic contact layer of impurity amorphous silicon that is in contact with the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other; A data line connected to the source electrode on the interlayer insulating layer, the data line being defined to cross the gate line to define the pixel area; And a pixel electrode formed in the pixel area in contact with one end of the drain electrode on the interlayer insulating layer.

In this case, the gate line is formed so that the side end thereof is in contact with the gate insulating film and positioned above.

In addition, a dummy pattern formed of the same material forming the ohmic contact layer and having the same shape as the data line is formed under the data line.

In addition, a gate pad electrode connected to one end of the gate line, an island type data pad electrode is formed on the buffer layer, and the interlayer insulating layer may include a gate pad contact hole exposing the gate pad electrode and the data pad electrode. A data pad contact hole for exposing, an auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole made of the same material as the pixel electrode, and the data pad contact hole on the interlayer insulating layer; The auxiliary data pad electrode is formed in contact with the data pad electrode and at the same time in contact with one end of the data line. In this case, the gate and data pad electrodes each have a double layer structure of a lower layer of impurity polysilicon made of the same material constituting the gate electrode and an upper layer made of the same material constituting the gate wiring.

In addition, the ohmic contact layer may be formed of pure amorphous silicon, and have a thickness of 50 μs to 300 μs, and include a barrier pattern contacting the active layer and spaced apart from each other through the active contact hole.

In addition, the pixel electrode is formed to overlap the gate wiring of the front end, so that the pixel electrode, the interlayer insulating film, and the gate wiring of the front end overlap each other to form a storage capacitor.

By the method of manufacturing the array substrate according to the present invention, the active layer is not exposed to dry etching, and thus, surface damage does not occur, thereby preventing the thin film transistor characteristic from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

The array substrate manufactured by the manufacturing method according to the present invention comprises a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the mobility characteristics by several tens to several hundred times compared to one array substrate.

Since the active layer of polysilicon is used as the semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In addition, by fabricating an array substrate including a thin film transistor having an active layer of polysilicon through a total of five mask processes, a conventional active layer of polysilicon that requires eight to nine mask processes including a doping process is prepared. Simplify the process compared to the manufacturing of the array substrate having, thereby reducing the manufacturing cost and improve the productivity.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

4A to 4L are cross-sectional views illustrating manufacturing processes of one pixel area including a thin film transistor, a gate pad part, and a data pad part of an array substrate according to an exemplary embodiment of the present invention. In this case, for convenience of description, the device region TrA and the gate pad electrode are formed in the portion where the thin film transistor Tr is formed in each pixel region P, and the gate pad portion GPA and the data pad electrode are formed. The part to be defined is defined as a data pad part DPA.

First, as shown in FIG. 4A, a thickness of about 1000 kV to 3000 kPa is obtained by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on a transparent insulating substrate 101, for example, a glass substrate. A buffer layer 102 is formed.

According to a feature of the present invention, a solid phase crystallization (SPC) process is performed in a subsequent process, and the solid phase crystallization (SPC) process requires a high temperature of 600 ° C to 800 ° C. In this case, when the substrate 101 is exposed to a high temperature atmosphere, alkali ions may be eluted from the surface of the substrate 101 to degrade the characteristics of the component made of polysilicon. Thus, the buffer layer 102 may be removed to prevent such a problem. To form.

Next, the impurity amorphous silicon is deposited on the buffer layer 102 to form a first impurity amorphous silicon layer 103 having a thickness of about 500 mW to about 1000 mW. Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) is deposited on the first impurity amorphous silicon layer 103 to form a first inorganic insulating layer 108 having a thickness of about 500 kPa to about 4000 kPa. Pure amorphous silicon is deposited on the first inorganic insulating layer 108 to form a pure amorphous silicon layer 111 having a thickness of about 300 mW to about 1000 mW.

The pure amorphous silicon layer 111 was formed to have a thickness of 1000 kPa or more, considering that some of the pure amorphous silicon layer 111 is etched by being exposed to dry etching proceeding to form an ohmic contact layer spaced apart from each other, and some thickness is removed from the surface thereof. However, in the exemplary embodiment of the present invention, the active layer of polysilicon (115 of FIG. 4L) finally implemented through the pure amorphous silicon layer 111 is not exposed to dry etching, and thus its thickness is thin by dry etching. There is no problem such as losing. Therefore, the pure amorphous silicon layer 111 may be formed to have a thickness of 300 mW to 1000 mW, which may serve as an active layer. In this case, the material cost and unit process time may be reduced.

On the other hand, the four material layers 102, 103, 108, and 111 are all semiconductor materials (the first impurity amorphous silicon layer 103 and the pure amorphous silicon layer 111) or the inorganic insulating material (buffer layer 102 and the first material). 1 inorganic insulating layer 108), these semiconductor and inorganic insulating materials are all changed only in the same vacuum chamber 195 through chemical vapor deposition (CVD) equipment (not shown) It can be formed continuously without exposure in the air by zooming.

Next, as shown in FIG. 4B, the pure amorphous silicon layer (111 of FIG. 4A) is subjected to a solid phase crystallization (SPC) process in order to improve mobility characteristics of the pure amorphous silicon layer (111 of FIG. 4A). The crystallization is performed to form the pure polysilicon layer 112. In this case, the solid phase crystallization (SPC) process is, for example, a thermal crystallization process through heat treatment in an atmosphere of 600 ℃ to 800 ℃, or alternating in a temperature atmosphere of 600 ℃ to 700 ℃ using an alternating magnetic field crystallization device It is preferable that the magnetic field crystallization (Alternating Magnetic Field Crystallization) process.

At this time, as a result of the solid state crystallization (SPC) process, not only the pure amorphous silicon layer (111 in FIG. 4A) but also the first impurity amorphous silicon layer (103 in FIG. 4A) are also crystallized to form the impurity polysilicon layer 104. By doing so, the conductivity is improved.

Next, as shown in FIG. 4C, a photoresist is applied onto the pure polysilicon 112 to form a photoresist layer (not shown), and the light transmitting region and blocking of the photoresist layer (not shown). The light transmittance is smaller than the transmission area (not shown) and larger than the blocking area (not shown) by adjusting the amount of light passing through the area (not shown) and the slit form, or further comprising a plurality of coating films. Diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a transmission area (not shown).

Subsequently, by developing the exposed photoresist layer (not shown), a portion of the portion where the gate insulating layer 109 of FIG. 4L should be formed on the pure polysilicon layer 112 corresponding to the device region TrA (to be formed later) The first photoresist pattern 191a having the first thickness is formed to correspond to the active layer of the pure polysilicon (the portion not overlapping with 115 of FIG. 4L), and the gate insulating layer 109 of FIG. 4L is formed. The second photoresist pattern 191b having a second thickness that is thicker than the first thickness is formed to correspond to the portion where the active layer (115 of FIG. 4L) is to be formed.

Accordingly, the second photoresist pattern 191b having the second thickness is formed on the pure polysilicon layer 112 to correspond to the central portion of the device region TrA. 191b) first photoresist patterns 191a having the first thickness are formed at both sides. Thus, forming the first photoresist pattern 191a having the first thickness and the second photoresist pattern 191b having the second thickness may later be gated on both sides of the active layer of pure polysilicon (115 in FIG. 4L). This is to expose the insulating film (109 in Fig. 4L).

Next, as shown in FIG. 4D, the pure polysilicon layer 112 shown in FIG. 4C and the first inorganic insulating layer below it are exposed to the outside of the first and second photoresist patterns 191a and 191b. 108c of 4c is sequentially etched to form a gate insulating film 109 and a pure polysilicon pattern 113 sequentially stacked in an island form on the impurity polysilicon layer 104 in the device region TrA.

In this case, the pure polysilicon layer (112 in FIG. 4C) and the first inorganic insulating layer (108 in FIG. 4C) are included in regions other than the device region TrA including the gate and data pad portions GPA and DPA. All of these are removed and the impurity polysilicon layer 104 is exposed.

Next, as shown in FIG. 4E, the first photoresist pattern having the first thickness is ashed by ashing the substrate 101 on which the gate insulating layer 109 and the pure polysilicon pattern 113 are formed. By removing 191a of FIG. 4D, both surfaces of the pure polysilicon pattern 113 are exposed to the outside of the second photoresist pattern 191b in the device region TrA. At this time, the thickness of the second photoresist pattern 191b is also reduced by ashing, but still remains on the pure polysilicon pattern 113.

 Next, as shown in FIG. 4F, the pure polysilicon pattern (113 of FIG. 4E) exposed to the outside of the second photoresist pattern 191b is etched and removed to the lower portion of the second photoresist pattern 191b. An active layer 115 of pure polysilicon is formed, and at the same time, the gate insulating layer 109 is exposed to both sides of the active layer 115 of pure polysilicon.

Next, as shown in FIG. 4G, the pure polysilicon is removed by performing a strip to remove the second photoresist pattern (191b of FIG. 4F) remaining on the active layer 115 of the pure polysilicon. The active layer 115 is exposed.

Next, as shown in FIG. 4H, a first metal material such as aluminum (Al), aluminum alloy (AlNd), and copper is disposed on the exposed active layer 115 of the pure polysilicon and the impurity polysilicon layer 104. One or two or more of (Cu), copper alloy, molybdenum (Mo), and chromium (Cr) are continuously deposited to form the first metal layer 117.

Subsequently, a photoresist is applied on the first metal layer 117 to form a second photoresist layer (not shown), and exposure and development are performed on the first metal layer 117, thereby forming a gate wiring at the boundary of each pixel region P (FIG. 4L). A third photoresist pattern 193 corresponding to a portion where the gate 120 and the gate and the data pad electrodes GPA and DPA are to be formed and corresponding to a portion where the gate and data pad electrodes 121 and 122 of FIG. 4L are to be formed. do.

Next, as shown in FIG. 4I, the first metal layer 117 of FIG. 4H and the impurity polysilicon layer (104 of FIG. 4H) exposed to the outside of the third photoresist pattern 193 are etched. By removing, the gate electrode 105 made of the impurity polysilicon is formed in the device region TrA on the buffer layer 102, and at the same time, the impurity poly is formed at the boundary of the pixel region P on the buffer layer 102. A gate wiring 120 is formed in contact with the gate electrode 105 of silicon and extending in one direction. In this case, the gate wiring 120 has a double layer structure including a lower layer 106 of impurity polysilicon and an upper layer 118 of a first metal material in a region other than the device region TrA, and the first metal material. When the upper layer 118 is formed of two or more metal materials of the first metal material, the upper layer 118 may have a substantially multilayer structure.

In addition, in the gate and data pad parts GPA and DPA, a double layer gate and data pad electrode 121 made of a material including the impurity polysilicon pad 107 and the first metal pad 119 over the buffer layer 102. , 122). In this case, the gate pad electrode 121 may be connected to one end of the gate line 120, and the data pad electrode 122 may have an island shape in the data pad part DPA.

Meanwhile, in the device region TrA, the gate wiring 120 is formed of only the upper layer 118 made of the first metal material, and the gate wiring 120 made of only the upper layer 118 is formed of the impurity polysilicon. It is characterized in that it is formed in contact with the gate electrode 105 and the side end thereof overlaps with the gate insulating film 109 formed on the gate electrode 105.

Meanwhile, in the embodiment of the present invention, forming the gate electrode 105 with impurity polysilicon rather than a metal material may include forming the active layer 115 of the pure polysilicon disposed on the gate electrode 105. This is to solve the problem that occurs when In the case of forming a thin film transistor having a bottom gate structure, a gate electrode is formed of a metal material on a substrate, and a pure amorphous silicon layer is formed on the substrate through a gate insulating film to form a semiconductor layer. The solid phase crystallization from the polysilicon layer requires a relatively high temperature of 600 ° C or higher. Accordingly, during the solid phase crystallization process requiring a relatively high temperature, the gate electrode made of a metal material may be deformed or may have spikes that come into contact with the crystallized pure polysilicon layer through the gate insulating layer. Causes

Accordingly, in the embodiment of the present invention, in order to solve the problem occurring during the crystallization process by forming the gate electrode of the metal material, the gate electrode 105 is formed using impurity polysilicon that does not cause the above-described problem even when exposed to such a high temperature atmosphere. ) Is formed.

On the other hand, in the case of the gate electrode 105 made of impurity polysilicon, although the conductivity is lower than that of the metal material, when the thickness of the gate electrode 105 of the impurity polysilicon is 500 mW to 1000 mW, the resistance value per unit area is 150 mW / sq ( □) to 230 mW / sq (□), which is similar to that of indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material. Therefore, even if the gate electrode 105 is formed of impurity polysilicon, it does not matter to sufficiently serve as the gate electrode.

Next, as shown in FIG. 4J, the third photoresist pattern remaining on the gate line 120 and the gate and data pad electrodes 121 and 122 is removed by performing a strip.

Thereafter, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate line 120 and the gate and data pad electrodes 121 and 122 to form a second inorganic layer having a single layer structure. A second inorganic insulating layer (not shown) having a double layer structure is formed by forming an insulating layer (not shown) or depositing the two inorganic insulating materials in succession.

Thereafter, the second inorganic insulating layer (not shown) formed on the entire surface of the substrate 101 is coated with a photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, etc. By patterning by performing a mask process including a first in each device region (TrA) to expose the active layer 115 of the polysilicon on both sides thereof based on the central portion of the active layer 115 of pure polysilicon And second active contact holes 125a and 125b, a gate pad contact hole 126 exposing the gate pad electrode 121 in the gate pad part GPA, and the data pad part DPA. ), An interlayer insulating film 123 having a data pad contact hole 127 exposing the data pad electrode 122 is formed.

On the other hand, the interlayer insulating film 123 formed to have the shape described above covers the active layer 115 of pure polysilicon so as to correspond to the central portion (channel region) of the active layer 115 of pure polysilicon. It serves as a stopper, and serves as an insulating layer in correspondence with other areas.

In addition, the formation of the first and second active contact holes 123a and 123b in the interlayer insulating layer 123 is mainly performed by dry etching, wherein the pure polysilicon during the dry etching of the interlayer insulating layer 123 is performed. Although the active layer 115 is exposed to dry etching for forming the first and second active contact holes 125a and 125b in the interlayer insulating film 123, an etching gas used for dry etching of an inorganic insulating material (for example, in the case of silicon oxide and silicon nitride _{CF 4, CF 3, CF 2} ) and the etching gas (the amorphous silicon and polysilicon both Cl ₂ or BCl ₃₎ to be used in dry etching of a semiconductor material are very different, so little from each other between these two materials Does not affect Accordingly, the active layer 115 of pure polysilicon has little change in thickness even if it is exposed to dry etching for forming the first and second active contact holes 125a and 125b in the interlayer insulating layer 123. It does not matter.

Meanwhile, even if a predetermined thickness change occurs in the active layer 115 of pure polysilicon by the dry etching, a portion of the first and second active contact holes 125a and 125b is substantially formed in the channel. It does not matter because it is not.

Next, as shown in FIG. 4K, the active layer 115 has first and second active contact holes 125a and 125b that correspond to and exposes the active layer 115 of pure polysilicon. An impurity amorphous silicon is deposited on the entire surface of the center portion 115 over the interlayer insulating layer 123 serving as an etch stopper, thereby forming a second impurity amorphous silicon layer (not shown) having a thickness of about 100 kPa to about 300 kPa.

In this case, buffered oxide etchant (BOE) cleaning may be performed before forming the second impurity amorphous silicon layer (not shown) on the interlayer insulating layer 123. This is to completely remove the natural oxide film (not shown) that may be formed by exposing the surface of the active layer 115 of pure polysilicon exposed through the first and second active contact holes 125a and 125b to air. to be.

Meanwhile, before forming the second impurity amorphous silicon layer (not shown) on the interlayer insulating layer 123 having the first and second active contact holes 125a and 125b, pure amorphous silicon is formed on the entire surface of the substrate 101. May be deposited first to further form a barrier layer (not shown) having a thickness of about 50 GPa to 300 GPa. In this case, the reason for forming a barrier layer (not shown) made of pure amorphous silicon is that the barrier layer (not shown) is formed between the active layer 115 of the pure polysilicon and the second impurity amorphous silicon layer (not shown). This is to improve the bonding force between the two layers 115 (not shown) by being interposed therebetween. That is, the bonding strength of the pure polysilicon with the active layer 115 is because pure amorphous silicon is more excellent than impurity amorphous silicon. However, the barrier layer (not shown) made of pure amorphous silicon is not necessarily formed and may be omitted.

Next, a second metal layer (not shown) is formed by depositing one of a second metal material, for example, molybdenum (Mo) and molybdenum (MoTi), on the second impurity amorphous silicon layer (not shown).

Next, the second metal layer (not shown) and the second impurity amorphous silicon layer (not shown) disposed thereunder are patterned by performing a mask process so that the boundary between each pixel region P is disposed on the interlayer insulating layer 123. The data line 130 defining the pixel area P is formed to cross the gate line 120. In this case, a dummy pattern 129 made of impurity amorphous silicon is formed under the data line 130 by the above-described process.

At the same time, in the device region TrA, source and drain electrodes 133 and 136 spaced apart from each other are formed on the interlayer insulating film 123, and an impurity amorphous is formed below the source and drain electrodes 133 and 136. An ohmic contact layer 128 made of silicon is formed. In this case, the ohmic contact layer 128 is in contact with the active layer 115 of pure polysilicon through the first and second active contact holes 125a and 125b, respectively.

Although not shown in the drawings, when the barrier layer (not shown) made of pure amorphous silicon is formed, the ohmic contact is formed between the spaced apart ohmic contact layer 128 and the active layer 115 of pure polysilicon. The barrier pattern (not shown) is formed to have the same planar area as the layer 128 and to be completely overlapped.

  In addition, the source electrode 133 and the data line 130 formed in the device region TrA are formed to be connected to each other, and at this time, the source and drain electrodes 133 and 136 spaced apart from each other The ohmic contact layer 128 has the same planar shape and planar area as that of each of the source and drain electrodes 133 and 136 and is completely overlapped and formed.

 Meanwhile, in the exemplary embodiment of the present invention, a channel in the on state of the thin film transistor Tr in the process of forming the data line 130, the source and drain electrodes 133 and 136, and the ohmic contact layer 128. The interlayer insulating film 123 serving as an etch stopper is formed to correspond to the central portion of the active layer 115 of pure polysilicon, and thus the ohmic contact layer is formed after the source and drain electrodes 133 and 136 are formed. In the dry etching process for patterning 128, the active layer 115 of pure polysilicon is not affected at all.

Therefore, it can be seen that the surface damage of the active layer in the portion where the channel is formed by the dry etching process for ohmic contact layer patterning, which is a problem mentioned in the related art, does not occur.

Meanwhile, the gate electrode 105 of the impurity polysilicon, the gate insulating layer 109, the active layer 115 of pure polysilicon, and the like are sequentially stacked on the device region TrA by the above-described process. The interlayer insulating film 123, the ohmic contact layer 128 of impurity amorphous silicon, and the source and drain electrodes 133 and 136 form a thin film transistor Tr.

On the other hand, although not shown in the drawings, when the above-described array substrate 101 is manufactured as an array substrate for an organic light emitting device, the data on the same layer on which the data wiring 130 is formed in parallel with the data wiring 130 The power supply wiring (not shown) may be further spaced apart from the wiring 130 by a predetermined distance, and the thin film transistor Tr connected to the data wiring 130 and the gate wiring 120 may be formed in each pixel region P. In addition to the switching thin film transistor, it has the same structure and may further form a driving thin film transistor (not shown) connected to the power line (not shown) and the switching thin film transistor (Tr).

Next, as shown in FIG. 4L, the source and drain electrodes 133 and 136 of the substrate 101 having the data line 130, the source and drain electrodes 133 and 136, and the ohmic contact layer 128 are formed. ) And a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), are deposited on the entire surface of the data line 130 to form a transparent conductive material layer (not shown). Proceeding to pattern the pixel electrode 150 in contact with one end of the drain electrode 136 in the pixel region (P). In this case, the pixel electrode 150 is formed so as to overlap the gate wiring 120 and the interlayer insulating layer 123 therebetween so that the front gate gate 120 and the interlayer insulating layer 123 and the pixel electrode overlap each other. 150 forms a storage capacitor StgC.

At the same time, in the gate pad part GPA, a gate auxiliary pad electrode 153 is formed on the interlayer insulating layer 123 to contact the gate pad electrode 121 through the gate pad contact hole 126. In the data pad unit DPA, the data auxiliary pad electrode 156 is formed on the interlayer insulating layer 123 to contact the data pad electrode 122 through the data pad contact hole 127. The array substrate 101 according to this is completed. In this case, the data auxiliary pad electrode 156 also serves as a data link wire for electrically connecting the data pad electrode 122 and the data wire 130 by contacting one end of the data wire 130. It is characteristic.

In this case, the second metal material constituting the source and drain electrodes 133 and 136, for example, molybdenum (Mo) or molybdenum (MoTi) may be indium tin oxide (ITO) or indium zinc oxide, which is a transparent conductive material. (IZO) does not react to the etching solution for patterning, so that the source and drain electrodes 133 and 136 are etched and removed when the pixel electrode 150 and the gate and data auxiliary pad electrodes 153 and 156 are formed. The problem does not occur.

 Although not shown in the drawings, when a driving thin film transistor (not shown) is formed in each of the pixel regions P, the thin film transistor Tr (which forms a switching thin film transistor) formed in the device region TrA is formed. The drain electrode 136 does not contact the pixel electrode 150, but instead, the drain electrode 136 of the driving thin film transistor (not shown) contacts the pixel electrode 150 to be electrically connected to the drain electrode 136. When a thin film transistor Tr (which forms a switching thin film transistor) connected to the gate and data lines 120 and 130 and a driving thin film transistor (not shown) are formed in the pixel region P in the device region TrA, An array substrate having such a configuration forms an array substrate for an organic light emitting device.

In addition, when fabricating an array substrate for an organic light emitting device, an organic insulating material is coated on the pixel electrode 150 and the thin film transistor Tr to form an organic insulating layer (not shown), and a mask process is performed. By patterning, a process of forming a partition wall (not shown) along the boundary of each pixel area P may be further performed. In this case, the partition wall (not shown) is formed to completely cover the thin film transistor (Tr) and the data line 130 is characterized in that it serves as a protective layer.

The array substrate manufactured by the above-described manufacturing step is manufactured by a total of five mask processes without forming a protective layer, and thus three to four times compared to an array substrate having a thin film transistor having a conventional polysilicon as an active layer. The number of mask processes can be reduced.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.

2A through 2E are cross-sectional views illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;

3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor having a polysilicon semiconductor layer in the related art.

4A to 4L are cross-sectional views illustrating manufacturing processes of one pixel region, a gate pad portion, and a data pad portion including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101: substrate

102: buffer layer

105: gate electrode of impurity polysilicon

106: bottom layer (of gate wiring)

107 impurity polysilicon pads (of gate and data pad electrodes)

109: gate insulating film

115: active layer of pure polysilicon

118: top layer (of gate wiring)

119: first metal pad (of gate and data pad electrodes)

120: gate wiring

121: gate pad electrode

122: data pad electrode

123: interlayer insulating film

125a and 125b: first and second active contact holes

126: gate pad contact hole

127: data pad contact hole

128: ohmic contact layer (of impurity amorphous silicon)

129: dummy pattern

130: data wiring

133: source electrode

136: drain electrode

150 pixel electrode

153: auxiliary gate pad electrode

156: auxiliary data pad electrode

DPA: Data Pad

GPA: Gate Pad

P: pixel area

StgC: Storage Capacitors

Tr: Thin Film Transistor

TrA: device area

Claims (14)

Forming a buffer layer made of an inorganic insulating material, a first impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the substrate on which the pixel region including the device region is defined; Performing a solid phase crystallization process to crystallize the first impurity amorphous silicon layer and the pure amorphous silicon layer into an impurity polysilicon layer and a pure polysilicon layer, respectively; Patterning the first inorganic insulating layer and the pure polysilicon layer over the impurity polysilicon layer to form an active layer in the device region exposing a gate insulating layer and both surfaces of the gate insulating layer as islands; A first metal layer is formed on the entire surface of the active layer, and the first metal layer and the impurity polysilicon layer are patterned to form a gate wiring at the boundary of the pixel region. Forming a gate electrode of impurity polysilicon in contact with the wiring; Depositing and patterning an inorganic insulating material over the gate wiring and the active layer to form an interlayer insulating film having active contact holes exposing the active layer to both sides of the active layer center;  Forming an ohmic contact layer of impurity amorphous silicon and a source and drain electrode spaced apart from each other on the ohmic contact layer, the impurity amorphous silicon being in contact with the active layer and spaced apart from each other through the active contact hole, and simultaneously being disposed on the interlayer insulating film. Forming a data line connected to a source electrode and crossing the gate line at a boundary of the pixel region; Forming a pixel electrode in contact with one end of the drain electrode in each pixel region by depositing and patterning a transparent conductive material over the data line and the source and drain low electrodes; Method of manufacturing an array substrate comprising a. The method of claim 1, Patterning the first inorganic insulating layer and the pure polysilicon layer over the impurity polysilicon layer to form an active layer exposing a gate insulating film and both surfaces of the gate insulating film in an island form in the device region; A first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the device region, and may correspond to both side edges of the gate insulating layer exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; Sequentially removing the pure polysilicon layer and the inorganic insulating layer exposed to the outside of the first and second photoresist patterns to form the gate insulating layer and the pure polysilicon pattern in a stacked manner in the device region; Exposing both edges of the pure polysilicon pattern by ashing to remove the second photoresist pattern; Removing the polysilicon pattern exposed to the outside of the first photoresist pattern to form an active layer of pure polysilicon on the gate insulating film, the active layer of which is completely overlapped and exposes both edges of the gate insulating film; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. The method of claim 1, The solid state crystallization (SPC) process is an alternating magnetic field crystallization using a thermal crystallization or alternating magnetic field crystallization device through a heat treatment. The method of claim 1, A barrier pattern formed of pure amorphous silicon under the ohmic contact layer on the interlayer insulating layer having the active contact hole, and having a thickness of 50 μs to 300 μm, contacting the active layer through the active contact hole, and being spaced apart from each other. Forming the array substrate comprising the step of forming a. The method of claim 1, And performing a buffered oxide etchant (BOE) cleaning to remove a native oxide film formed on the surface of the active layer exposed through the active contact hole before forming the ohmic contact layer. The method of claim 1, The forming of the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring and an island-shaped data pad electrode. The forming of the interlayer insulating layer may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The forming of the pixel electrode may include an auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole, and contacting the data pad electrode through the data pad contact hole and simultaneously at one end of the data line. And forming an auxiliary data pad electrode in contact with the same. The method of claim 1, And the gate line is formed such that a side end thereof is in contact with the gate insulating layer and positioned above the gate insulating layer. A buffer layer formed on the substrate on which the pixel region including the element region is defined; A gate electrode of impurity polysilicon formed in the device region over the buffer layer; A gate insulating film formed in an island shape on the gate electrode; An active layer of pure polysilicon formed by exposing both edges of the gate insulating film over the gate insulating film; A gate wiring formed on a boundary of the pixel region with a double layer structure having a lower layer made of the same material forming the gate electrode and an upper layer made of a metal material in contact with the gate electrode over the buffer layer; An interlayer insulating film formed over the gate wiring and the active layer and having an active contact hole exposing the active layer on both sides of a center portion of the active layer; An ohmic contact layer of impurity amorphous silicon that is in contact with the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other; A data line connected to the source electrode on the interlayer insulating layer, the data line being defined to cross the gate line to define the pixel area; A pixel electrode formed in the pixel area in contact with one end of the drain electrode on the interlayer insulating film; Array substrate comprising a. The method of claim 8, And the gate line is formed such that a side end thereof is in contact with the gate insulating layer and positioned above the gate insulating layer. The method of claim 8, And a dummy pattern formed of the same material constituting the ohmic contact layer and having a same shape as that of the data line under the data line. The method of claim 8, A gate pad electrode connected to one end of the gate line and an island data pad electrode are formed on the buffer layer. The interlayer insulating layer includes a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. An auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole made of the same material as the pixel electrode on the interlayer insulating layer, and simultaneously contacting the data pad electrode through the data pad contact hole; And an auxiliary data pad electrode in contact with one end of the array substrate. The method of claim 11, And the gate and data pad electrodes each have a double layer structure of a lower layer of impurity polysilicon made of the same material constituting the gate electrode and an upper layer made of the same material constituting the gate wiring. The method of claim 8, And an barrier pattern formed of pure amorphous silicon under the ohmic contact layer, the barrier pattern having a thickness of 50 mW to 300 mW and contacting the active layer and spaced apart from each other through the active contact hole. The method of claim 8, And the pixel electrode is formed to overlap the gate wiring of the front end, so that the pixel electrode, the interlayer insulating film, and the gate wiring of the front end overlap each other to form a storage capacitor.

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