KR20110061774A - Array substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array panel and manufacturing method thereof are provided to prevent the degradation of the thin film transistor property without exposing an active layer to an etching process. CONSTITUTION: A gate electrode(107) is formed in an impurity poly-silicon into the island type in the switching domain of the top of the substrate. A gate insulating layer is formed in the gate electrode while having the same flat type as the gate electrode. An active layer of a poly-silicon exposes the edge part of the gate insulating layer. An inter-layer insulating is formed in a second active contact hole.

Description

Array substrate and method of manufacturing the same

The present invention relates to an array substrate, and in particular, an array substrate comprising a thin film transistor having an active layer excellent in mobility characteristics, which naturally inhibits the occurrence of surface damage of an active layer in a portion where a channel is formed by dry etching. It relates to a manufacturing method thereof.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of adjusting the on / off voltage of each pixel, has a resolution and a moving picture. Its outstanding implementation ability attracts the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each pixel area on / off.

FIG. 1 is a cross-sectional view of a pixel area including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting display device.

As illustrated, the gate electrode 15 is disposed in the switching region TrA in the plurality of pixel regions P defined by the plurality of gate lines (not shown) and the data lines 33 intersecting on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, and the characteristic difference of the thin film transistor (Tr) occurs due to the thickness difference (t1 ≠ t2) of the active layer 22. have.

2A through 2E are cross-sectional views illustrating a process of forming a semiconductor layer, a source, and a drain electrode during a manufacturing process of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

First, as shown in FIG. 2A, the pure amorphous silicon layer 20 is formed on the substrate 11, and the impurity amorphous silicon layer 24 and the metal layer 30 are sequentially formed thereon. Thereafter, a photoresist is formed on the metal layer 30 to form a photoresist layer (not shown), and the photoresist is exposed using an exposure mask, and subsequently developed to correspond to a portion where the source and drain electrodes are to be formed. A first photoresist pattern 91 having a thickness is formed, and at the same time, a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed to correspond to the spaced area between the source and drain electrodes. .

Next, as shown in FIG. 2B, the metal layer (30 of FIG. 2A) exposed to the outside of the first and second photoresist patterns 91 and 92, an impurity and a pure amorphous silicon layer below it (of FIG. 2A) 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top, and an impurity amorphous silicon pattern 25 and an active layer 22 below.

Next, as shown in FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by ashing. In this case, the first photoresist pattern (91 in FIG. 2B) having the third thickness forms the third photoresist pattern 93 while the thickness thereof is reduced, and remains on the source drain pattern 31.

Next, as illustrated in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching by removing the source drain pattern 31 of FIG. 2C exposed to the outside of the third photoresist pattern 93. To form. In this case, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the source and drain electrodes are dry-etched on the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the separation region between the source and drain electrodes 36 and 38. (36, 38) An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside of the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (Fig. Even a portion of the active layer 22 disposed below 25) of 2d may have a predetermined thickness etched at a portion where the impurity amorphous silicon pattern (25 of FIG. 2d) is removed. Therefore, a difference (t1 ≠ t2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (25 of FIG. 2D) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22. This is to prevent this.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer constituting the active layer 22 sufficiently thick to have a thickness greater than 1000 하여 considering the thickness of the active layer 22 that is etched and removed during the dry etching process for forming the ohmic contact layer 26. It is necessary to deposit 20 (FIG. 2A), which increases the deposition time, resulting in a decrease in productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier is low at 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the fabrication of the array substrate 51 including the thin film transistor (Tr) used as a 55, formation of an n + region 55b or a p + region (not shown) containing a high concentration of impurities in the polysilicon semiconductor layer 55 is performed. need. Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and thus, the active layer of the portion where the channel is formed is not exposed to dry etching, thereby preventing damage to the surface thereof, thereby providing a method of manufacturing an array substrate in which the characteristics of the thin film transistor are improved. It is for that purpose.

Furthermore, another object of the present invention is to provide a method of manufacturing an array substrate having a thin film transistor capable of improving a mobility property while forming a semiconductor layer using polysilicon, without requiring a doping process.

According to an aspect of the present invention, an array substrate includes: a gate electrode formed in an island shape with impurity polysilicon in the switching region on a substrate on which a pixel region and a switching region are defined; A gate insulating film formed on the gate electrode and having the same planar shape as the gate electrode; A pure poly formed in an H-shape having an edge portion of the gate insulating film over the gate insulating film, the center portion having a first width in plan view, and both sides thereof having a second width larger than the first width based on the center portion. An active layer of silicon; First and second active contact holes exposing portions having a second width of the active layer, respectively, and first holes exposing the gate insulating layer corresponding to the gate electrode located outside the active layer, An interlayer insulating film formed on the entire surface of the substrate; An ohmic contact layer of impurity amorphous silicon formed in the switching region in contact with the active layer through the first and second active contact holes and spaced apart from each other; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing the gate electrode to the inside of the first hole over the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the second passivation layer and corresponding to a central portion of the active layer having the first width; The spacing between the first and second active contact holes is constant.

In this case, the short axis of the first and second active contact holes has a curved shape, and the long axis has a straight shape, and the long axis of the first active contact hole and the second active contact hole are formed such that the long axes thereof face each other. to be.

  In addition, the center portion of the active layer having the first width is not formed in the separation region between the short axis of the first active contact hole having a curved shape and the short axis of the second active contact hole, and the first shape having the straight shape. And a separation region between the long axis of the active contact hole and the long axis of the second active contact hole.

In addition, the gate insulating layer is characterized in that the portion in which the first hole is formed has a thickness thinner than other regions.

In addition, between the active layer and each of the ohmic contact layer is made of pure amorphous silicon, and has the same planar shape as the ohmic contact layer, it is characterized in that the barrier pattern having a thickness of 50 ~ 300 완전 completely overlapped.

In addition, the gate insulating film is made of silicon oxide (SiO ₂ ).

According to an aspect of the present invention, there is provided a method of fabricating an array substrate, the method including: forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; A gate insulating film formed of a gate electrode and silicon oxide in an island shape in the switching region over the buffer layer, and an edge portion of the gate insulating film, the center portion having a first width in plan view, and both sides of the first portion with respect to the center portion; Forming an active layer of pure polysilicon to form an H shape with a second width greater than the width; Depositing and patterning an inorganic insulating material over the active layer on the entire surface to form an interlayer insulating film having first and second active contact holes spaced apart from each other to expose portions having a first width of the active layer; Forming an ohmic contact layer of impurity amorphous silicon that is in contact with the active layer and spaced apart from each other through the first and second active contact holes, and a source and drain electrode spaced apart from each other on the ohmic contact layer, Simultaneously forming a data line connected to the source electrode on a boundary of the pixel area over the interlayer insulating film; Forming a first passivation layer having a gate contact hole exposing the gate electrode over the data line and the source and drain electrodes; Forming a gate wiring on the boundary of the pixel area over the first passivation layer, the gate wiring contacting the gate electrode through the gate contact hole and crossing the data wiring; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area.

In this case, the forming of the interlayer insulating film having the first and second active contact holes may include forming a first hole exposing the gate insulating film outside the active layer, and before forming the ohmic contact layer. Performing a buffered oxide etchant (BOE) cleaning to remove an oxide layer on the surface of the active layer exposed through the first and second active contact holes and reduce a thickness of the gate insulating layer exposed through the first hole. The gate contact hole may be formed inside the first hole.

The forming of the first passivation layer having a gate contact hole exposing the gate electrode over the data line and the source and drain electrodes may include an inorganic insulating material over the data line and the source and drain electrodes. Depositing to form the first protective layer; And forming the gate contact hole by performing dry etching on the first passivation layer located inside the first hole and the gate insulating layer having a thin thickness thereunder.

In addition, a gate insulating film made of a gate electrode and silicon oxide in an island shape in the switching region over the buffer layer, and an edge portion of the gate insulating film are exposed, and a center portion thereof has a first width and both sides thereof are referred to as the center portion. Forming an active layer of pure polysilicon to have an H-shape having a second width greater than the first width may include sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer. Wow; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; A first photoresist pattern having a first thickness is formed on the pure polysilicon layer to correspond to a portion where the H-shaped active layer is formed in the switching region, and the gate electrode is exposed to the outside of the active layer. Forming a second photoresist pattern having a second thickness thinner than the first thickness corresponding to the edge portion; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a pure polysilicon pattern with a gate electrode and a gate insulating film of silicon; Exposing the edges of the pattern of the pure polysilicon outside the first photoresist pattern by ashing to remove the second photoresist pattern; Forming the H-shaped active layer by removing the pure polysilicon pattern exposed to the outside of the first photoresist pattern, and simultaneously exposing an edge of the gate insulating layer; Removing the first photoresist pattern.

In addition, the gate electrode made of impurity polysilicon is formed to have a thickness of about 500 kPa to 1000 kPa, and the active layer of the H-shaped pure polysilicon is formed to have a thickness of about 300 kPa to 1000 kPa.

In addition, the solid phase crystallization process is characterized in that the alternating magnetic field crystallization using the crystallization or alternating magnetic field crystallization (AMFC) device through a heat treatment of 600 ℃ to 800 ℃.

In addition, an ohmic contact layer of impurity amorphous silicon contacting the active layer and spaced apart from each other through the first and second active contact holes, respectively, is formed on the interlayer insulating layer, and source and drain electrodes are spaced apart from each other on the ohmic contact layer. At the same time, forming a data line connected to the source electrode at the boundary of the pixel region over the interlayer insulating layer may include forming the data line between the active layer and the ohmic contact layer inside each of the first and second active contact holes. And forming a barrier pattern made of pure amorphous silicon, having the same planar shape as the ohmic contact layer, completely overlapping, and having a thickness of 50 μs to 300 μs.

By the method of manufacturing the array substrate according to the present invention, the active layer in the region where the channel is formed is not exposed to dry etching, and thus, surface damage does not occur, thereby preventing the thin film transistor characteristic from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

The array substrate manufactured by the manufacturing method according to the present invention comprises a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the mobility characteristics by several tens to several hundred times compared to one array substrate.

Since the active layer of polysilicon is used as a semiconductor layer of the thin film transistor, doping of impurities is not required, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In forming the gate contact hole exposing the gate electrode, a first hole is formed in which the interlayer insulating film and the part of the gate insulating film are removed without increasing the process time in the previous step, and the gate contact hole is provided inside the first hole. In addition, the etching process may be performed only on the first insulating layer and the gate insulating layer and the gate electrode, the thickness of which is thin, thereby reducing the dry etching time.

In addition, both sides of the polysilicon active layer in contact with the source and drain electrodes have a relatively wide width in plan view, and a central portion where the channel is formed has a narrow width so that the channel length is constant so that the characteristics of the thin film transistor There is an effect of preventing a difference from occurring at each position.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

4A to 4O are cross-sectional views illustrating manufacturing processes of one pixel area including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention, and FIGS. 5A to 5O illustrate one of the array substrates according to an exemplary embodiment of the present invention. A plan view of manufacturing steps for a portion where a thin film transistor is formed in the pixel region of FIG. In this case, for convenience of description, a portion in which the thin film transistor Tr connected to the gate and the data line in each pixel region P is to be formed is defined as a switching region TrA.

First, as shown in FIGS. 4A and 5A, a buffer layer having a thickness of about 2000 Pa to 3000 Pa by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the transparent substrate 101. 103 is formed. Due to the characteristics of the present invention, a solid phase crystallization step is performed in a later step, and a high temperature atmosphere of 600 ° C to 800 ° C is required for this solid phase crystallization step. In this case, when the substrate 101 is exposed to a high temperature atmosphere, alkali ions may be eluted from the surface of the substrate, thereby degrading the properties of the component made of polysilicon, thereby forming the buffer layer 103 to prevent such a problem. .

Next, the impurity amorphous silicon is deposited on the buffer layer 103 to form a first impurity amorphous silicon layer 105 having a thickness of about 500 GPa to 1000 GPa. Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) is deposited on the first impurity amorphous silicon layer 105 in succession to form a first inorganic insulating layer 108 having a thickness of about 500 to 4000 Å. By depositing pure amorphous silicon on top, a pure amorphous silicon layer 111 having a thickness of about 300 kW to 1000 kW is formed.

In this case, the formation of the buffer layer 103, the first impurity amorphous silicon layer 105, the first inorganic insulating layer 108, and the pure amorphous silicon layer 111 may be performed by chemical vapor deposition (CVD). ) Through equipment (not shown). Thus, these four layers 103, 105, 108, 110 are characterized in that they are formed continuously by changing only the reaction gas injected into the chamber (not shown) of the chemical vapor deposition (CVD) equipment (not shown). In this case, the pure amorphous silicon layer 111 is formed to have a thickness greater than 1000 kV in consideration of etching to expose some dry etching and removing some thickness from the surface thereof.

However, in the exemplary embodiment of the present invention, the active layer of polysilicon (115 of FIG. 4O) finally implemented through the pure amorphous silicon layer 111 is not exposed to dry etching, and thus its thickness is thin by dry etching. There is no problem such as losing. Accordingly, the pure amorphous silicon layer 111 may be formed to have a thickness of 300 mW to 1000 mW, which may serve as an active layer. In this case, the material cost and unit process time may be reduced.

Next, as shown in FIGS. 4B and 5B, the pure amorphous silicon is subjected to a solid phase crystallization (SPC) process to improve mobility characteristics of the pure amorphous silicon layer (111 of FIG. 4A). The layer (111 in FIG. 4A) is crystallized to form pure polysilicon layer 112. At this time, the solid phase crystallization (SPC) is an alternating magnetic field in the temperature atmosphere of 600 ℃ to 700 ℃ using an crystallization or alternating magnetic field crystallization (AMFC) device by heat treatment in an atmosphere of 600 ℃ to 800 ℃, for example. It is preferred that it is crystallization.

Meanwhile, as a result of the solid phase crystallization process, not only the pure amorphous silicon layer (111 of FIG. 4A) but also the impurity amorphous silicon layer (105 of FIG. 4A) positioned below the first inorganic insulating layer (108 of FIG. 4A) may also be crystallized. As a result, the impurity polysilicon layer 106 is formed.

Next, as shown in FIGS. 4C and 5C, a photoresist is applied on the pure polysilicon 112 to form a photoresist layer (not shown), and light is transmitted to the photoresist layer (not shown). The light transmittance is smaller than the transmission area (not shown) and the blocking area (not shown) by adjusting the amount of light passing through the area, the blocking area (not shown), and the slit form, or further comprising a plurality of coating films. Rather, diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a large semi-transmissive region (not shown).

Subsequently, by developing the exposed photoresist layer (not shown), a part of the portion where the gate electrode (107 of FIG. 4O) of the impurity polysilicon should be formed on the pure polysilicon 112 corresponding to the switching region TrA. Corresponding to the active layer of the pure polysilicon formed later (not part of 115 of FIG. 4O), first and second photoresist patterns 191a and 191b having a first thickness are formed, and the gate electrode ( The third photoresist pattern 191c having a second thickness that is thicker than the first thickness is formed to correspond to the portion where the active layer 115 of FIG. 4O is to be formed among the portions where 107 of FIG. 4O is to be formed. .

Accordingly, the third photoresist pattern 191c having the second thickness corresponds to a portion of the portion where the gate electrode 107 of FIG. 4O is to be formed by overlapping with the active layer 115 of FIG. 4O by the above-described process. ) And regions in which the active layer (115 in FIG. 4O) is not formed among the portions where the gate electrode (107 in FIG. 4O) is to be formed are the first and second photoresist patterns 191a and 191b having the first thickness. ) Is formed, and the photoresist layer (not shown) is removed in all regions on the substrate 101 where the gate electrode 107 of FIG. 4O is not formed, thereby exposing the pure polysilicon layer 112. To achieve.

 In this case, the first and second photoresist patterns 191a and 191b may have different widths outside the third photoresist pattern 191c in the switching region TrA. This is because the gate electrode (107 in FIG. 4O), the gate insulating film (110 in FIG. 4O), and the edge of the active layer (115 in FIG. 4O) of pure polysilicon formed on the patterned impurity polysilicon are later formed. This prevents the interlayer insulating film 122 (FIG. 4O) formed thereafter from being cut off or lifted off, and further contacting the gate wiring (145 in FIG. 4O) formed later and the gate electrode (107 in FIG. 4O) of the impurity polysilicon. This is to secure an area for forming the gate contact hole (142 of FIG. 4O).

In addition, as a characteristic feature of the present invention, the third photoresist pattern 191c may have a “H” shape in plan view. The H-shaped third photoresist pattern 191c may be patterned later to form an active layer (115 of FIG. 4O) of pure polysilicon remaining under the third photoresist pattern 191c. The source and drain electrodes (133 and 136 of FIG. 4O) may have a wide width in contact with the drain electrodes (133 and 136 in FIG. 4O) and a small width in a region in which a channel serving as a carrier passage is formed. This is to make the channel length constant within the active layer (115 in FIG. 4O).

As described above, the widths of the portions in contact with the source and drain electrodes 133 and 136 in the active layer (115 in FIG. 4O) and the lengths of the channel regions serving as the paths through which the carriers move will be described in detail later.

Next, as shown in FIGS. 4D and 5D, the pure polysilicon layer 112 of FIG. 4C and the first inorganic exposed to the outside of the first, second and third photoresist patterns 191a, 191b, and 191c are exposed. Impurity poly sequentially stacked as an island form over the buffer layer 102 in the switching region TrA by sequentially etching and removing the insulating layer 108 of FIG. 4C and the first impurity polysilicon layer 104 of FIG. 4C. The gate electrode 107, the gate insulating layer 110, and the pure polysilicon pattern 113 of silicon are formed.

At this time, for the regions other than the switching region TrA, both the pure polysilicon layer (112 in FIG. 4D), the first inorganic insulating layer (108 in FIG. 4D), and the impurity polysilicon layer (104 in FIG. 4D) are all The buffer layer 103 is removed to expose the buffer layer 103.

Next, ashing is performed on the substrate 101 on which the gate electrode 107, the gate insulating layer 110, and the pure polysilicon pattern 113 of the impurity polysilicon are formed, as shown in FIGS. 4E and 5E. Proceed to remove the first and second photoresist patterns (191a, 191b of Figure 4d) having the first thickness by the pure polysilicon outside the third photoresist pattern 191c in the switching region (TrA) The edge portion of the pattern 113 is exposed. At this time, the thickness of the third photoresist pattern 191c also decreases as a result of ashing, but still remains on the pure polysilicon pattern 113.

 Next, as shown in FIGS. 4F and 5F, the edge of the gate insulating layer 110 is etched by removing the pure polysilicon pattern 113 of FIG. 4E exposed to the outside of the third photoresist pattern 191c. Expose wealth. In this case, the pure polysilicon pattern (113 of FIG. 4E) remaining without being etched by the third photoresist pattern 191c may have an “H” shape as a planar shape of the third photoresist pattern 191c. The active layer 115 of pure polysilicon is formed.

At this time, in the case of the embodiment according to the present invention, the gate insulating layer 110 and the gate electrode 107 of the impurity polysilicon disposed under the same may have the same planar shape and size and overlap with each other. to be.

In addition, one side of the gate insulating layer 110 exposed to the outside of the active layer 115 of the pure polysilicon having an “H” shape (the portion where the gate electrode is formed later) has the width of the other side (the gate electrode is It is characterized in that the first hole (124 in FIG. 4O) and the gate contact hole (142 in FIG. 4O) can be formed later by being formed wider than the width of the region other than the formed portion.

Next, as shown in FIGS. 4G and 5G, a strip is applied to the third photoresist pattern (191c of FIGS. 4F and 5F) remaining on the active layer 115 of the pure polysilicon. By removing, the active layer 115 of pure polysilicon having the "H" shape is exposed.

Next, as shown in FIGS. 4H and 5H, an inorganic insulating material such as silicon nitride (SiNx) is deposited on the active layer 115 of the pure polysilicon to form a second inorganic insulating layer 121.

In this case, the second inorganic insulating layer 121 is preferably formed to have a thickness equal to or greater than the sum of the thicknesses of the gate electrode 107 and the gate insulating layer 110 disposed thereon. This overlaps each other and suppresses the occurrence of breakage of the second inorganic insulating layer 121 due to the step formed with the buffer layer 103 at the ends of the gate electrode 107 and the gate insulating layer 110 formed in the same shape. To do this.

Subsequently, a photoresist layer (not shown) is formed by applying photoresist to the second inorganic insulating layer 121, and then the photoresist is exposed and exposed using an exposure mask to the photoresist layer (not shown). The phenomenon of the polysilicon active layer 115 of the active layer 115 has a wider width and corresponding to the gate electrode 107 of the impurity polysilicon outside the central portion of the formed portion and the active layer 115 of the pure polysilicon The fourth photoresist pattern 194 having a hole hl exposing the second inorganic insulating layer 121 is formed corresponding to the central portion thereof. In this case, the holes hl corresponding to the active layers 115 may be formed even in a rectangular shape in plan view. However, even when the photoresist layer (not shown) is exposed and developed to form a planar rectangular hole (hl) in a planar manner, it does not form a perfect rectangular shape and is curved in a single side portion as shown in the drawing. Will appear. This phenomenon appears particularly well in the process of forming negative type patterning, that is, holes hl and the like.

Next, as shown in FIGS. 4I and 5I, dry etching of the second inorganic insulating layer (121 of FIG. 4H) exposed between the fourth photoresist pattern 194 is performed to activate the pure polysilicon. The active contact hole 123 exposing surfaces on both sides of the center 115 of the layer 115 and the gate insulating layer 110 exposed outside the active layer 115 of pure polysilicon are exposed. An interlayer insulating film 122 having a first hole 124 is formed.

At this time, the interlayer insulating film 122 serves as an etch stopper to cover the active layer 115 of pure polysilicon to correspond to the central portion of the active layer 115 of pure polysilicon, and to correspond to other areas. It will play the role of.

Meanwhile, the first hole 124 exposing the gate insulating layer 110 positioned on the gate electrode 107 is formed in the interlayer insulating layer 122 so that the gate for later exposing the gate electrode 107 is formed. This is to form a contact hole (142 of FIG. 4O) in a shorter time.

Looking at the planar configuration of the active contact hole 123 formed in the interlayer insulating film 122 by the above-described process, it can be seen that the short side does not form a rectangular shape but a curved shape. The active contact hole 123 has a rectangular shape in its design, but in the step of forming the active contact hole 123, the active contact hole 123 does not have a planar perfect rectangular shape, and in particular, a single side is curved in a semicircle shape. Will be achieved.

FIG. 6 is a schematic view of a switching area of an array substrate having a rectangular active layer according to a comparative example, and FIG. 7 is a photograph of a switching area of an actual array substrate completed by a process based on the schematic diagram shown in FIG. 8 is an enlarged photograph of a portion in which an active contact hole is formed in FIG. 7. In this case, for the convenience of description, the same reference numerals are given to the same components as in the exemplary embodiment of the present invention.

As shown in the drawing, the active contact hole 223 exposing the active layer 215 has a rectangular shape. However, the active contact hole 223 has a straight side in the active contact hole 223. It can be seen that it does not have a semicircle and does not have a perfect rectangular shape.

When the active contact hole 223 is formed in this manner, the source and drain electrodes 233 and 236 pass through the active contact hole 223 through the active contact hole 223 through the active contact hole 223. In the case where the active layer 215 is formed in contact with each other, it can be seen that the channel length varies for each position of the active contact hole 223.

That is, as shown in the figure, the center portion of each active contact hole 223 has a first distance d1 between the active contact holes 223 while being curved toward the end of each of the active contact holes 223. Increasingly, the distance between the active contact holes 223 may be greater than the first distance d1 (d2: variable).

In this case, it can be seen that the channel length formed in the active layer 215 also varies with each position of the active contact hole 223. When the channel length is changed in this way, the resistance value in the active layer 215 is different, which causes distribution of device parameter values, thereby changing the characteristics of the thin film transistor having the component.

Therefore, in order to solve this problem, as shown in FIGS. 4I and 5I, in the array substrate and the manufacturing method thereof according to the present invention, the active layer 115 of pure polysilicon is formed to have an "H" shape. will be.

Although the short side of the active contact hole 123 exposing the active layer 115 of the pure polysilicon is formed in a curved shape, the source and drain electrodes to be formed by the subsequent process (FIGS. 4O and 5O 133 and 136). ) Contacts the active layer 115 through the active contact hole 123 via an ohmic contact layer (127 in FIG. 4O) to form a channel region in the active layer 115 that serves as a carrier passage. Even if the channel length in the channel region is characterized in that formed.

That is, by forming the active layer 115 of pure polysilicon so as to have an “H” shape in accordance with the manufacturing characteristics of the array substrate according to the exemplary embodiment of the present invention, the active contact holes 123 may correspond to portions formed in a curved shape. The active layer 115 does not exist between the active contact holes 123 spaced apart from each other, and the active layer 115 exists only corresponding to portions of the active contact holes 123 formed in a straight line facing each other. to be.

Therefore, even if the short side surface of the active contact hole 123 is formed to have a semi-circular curved shape in plan, the channel length of the channel region formed in the active layer 115 between the active contact holes 123 is constant. In this case, the device scattering problem caused by the change in the channel length for each location can be prevented at the source.

    Next, as shown in FIGS. 4J and 5J, the fourth photoresist pattern (194 of FIG. 4I) remaining on the interlayer insulating layer 122 having the active contact hole 123 and the first hole 124. The interlayer insulating film 122 is exposed by performing strip removal.

Subsequently, the substrate 101 on which the interlayer insulating film 122 having the active contact hole 123 and the first hole 124 is formed is cleaned using BOE (buffered oxide etchant) (hereinafter referred to as BOE cleaning). Silicon oxide (SiO) exposed through the first hole 124 is removed while an oxide film (not shown) naturally formed on the surface of the active layer 115 of the pure polysilicon exposed through the active contact hole 123 is removed. The thickness of the gate insulating layer 110 of the portion corresponding to the first hole 124 is reduced by etching the gate insulating layer 110 formed of ₂ ). That is, grooves are formed in the surface of the gate insulating layer 110.

The oxide film (not shown) may be removed from the surface of the active layer 115 of pure polysilicon, and the gate insulating film 110 may be etched together through the first hole. This is because it is formed of silicon oxide (SiO ₂ ).

The solid phase crystallization having a temperature atmosphere of 600 ° C. to 800 ° C. in a state in which no material layer is formed on the pure amorphous silicon layer (111 in FIG. 4A) prior to solid phase crystallization on the surface of the active layer 115 of pure polysilicon. An oxide film (not shown) is naturally formed by exposure to the (SPC) process, and the oxide film (not shown) is in contact with an active layer 115 of pure polysilicon and an ohmic contact layer (or barrier pattern) formed later. It acts as a factor in degrading ohmic properties. Accordingly, the oxide film (not shown) on the surface of the active layer 115 of the pure polysilicon exposed through the active contact hole 123 is preferably removed, and the BOE cleaning is performed to remove the oxide film.

Next, as shown in FIGS. 4K and 5K, after the BOE cleaning is completed, a second impurity amorphous silicon layer having a thickness of about 100 μs to 300 μs is deposited by depositing impurity amorphous silicon on the entire surface of the interlayer insulating layer 122 ( Not shown).

Thereafter, a first metal layer (not shown) is deposited on the second impurity amorphous silicon layer (not shown), for example, by depositing any one of molybdenum (Mo), chromium (Cr), and molybdenum (MoTi). To form.

On the other hand, prior to forming the second impurity amorphous silicon layer (not shown), a pure amorphous silicon is first deposited on the interlayer insulating film 122 to form a barrier layer (not shown) having a thickness of about 50 to 300 mW. It may be. The reason for forming a barrier layer (not shown) made of pure amorphous silicon is because the barrier layer (not shown) is interposed between the active layer 115 of the pure polysilicon and the impurity amorphous silicon layer (not shown). This is to improve the bonding force between the two layers 115 (not shown). This is because the bonding force of the pure polysilicon with the active layer 115 is superior to pure amorphous silicon rather than impurity amorphous silicon. However, the barrier layer (not shown) need not be formed and may be omitted as in the embodiment.

Next, the interlayer insulating film is patterned by patterning the first metal layer (not shown) and the second impurity amorphous silicon layer (not shown) (including the barrier layer in the case of forming the barrier layer) under the mask process. Source and drain electrodes 133 and 136 spaced apart from each other on the interlayer insulating layer 122 in the switching region TrA, and at the same time, a data line 130 is formed on the boundary of each pixel region P. ) And an ohmic contact layer 127 made of impurity amorphous silicon under the source and drain electrodes 133 and 136. In this case, when the barrier layer (not shown) is formed as in the modified example, a barrier pattern (not shown) of pure amorphous silicon is formed under the ohmic contact layer 127. In this case, the ohmic contact layer (or barrier pattern (not shown) when the barrier pattern is formed) is in contact with the active layer 115 of the pure polysilicon through the active contact hole 123, respectively.

In addition, the source electrode 133 and the data line 130 formed in the switching region TrA are formed to be connected to each other. In this case, the ohmic contact layer 127 formed under each of the source and drain electrodes 133 and 136 spaced apart from each other (or a barrier pattern (not shown) when a barrier pattern is formed) is formed in the source. And the same shape and area as that of each of the drain electrodes 133 and 136.

 In addition, when the first dummy pattern 128 made of impurity amorphous silicon and the barrier pattern (not shown) are formed under the data line 130 by the above-described process, the second dummy made of pure amorphous silicon. A pattern (not shown) is formed.

In the process of forming the data line 130, the source and drain electrodes 133 and 136, and the ohmic contact layer 127, the active layer of pure polysilicon has a small width forming a channel region. Since the interlayer insulating film 122 serving as an etch stopper is formed to correspond to the central portion of the 115, the etching for patterning of the ohmic contact layer 127 is more precise when the source and drain electrodes 133 and 136 are formed. For example, during the dry process, the active layer 115 of pure polysilicon is not affected at all.

Therefore, it can be seen that the surface damage of the active layer 115 due to the dry etching process, which is a problem mentioned in the related art, does not occur. That is, after the data line 130 and the source and drain electrodes 133 and 136 are formed by patterning the first metal layer (not shown), the data wire 130 and the source and drain electrodes 133, 136) The removal of the impurity amorphous silicon layer (not shown) and the pure amorphous silicon layer (when the barrier pattern is formed) below it is performed by dry etching. In this case, since the interlayer insulating film 122 is formed between the source and drain electrodes 133 and 136 in the switching region TrA, the active layer of pure polysilicon of the portion corresponding to the channel region by the dry etching. 115 is not affected at all.

Therefore, unlike conventional array substrate fabrication, a channel by dry etching when forming an ohmic contact layer 127 and a barrier pattern (not shown) by patterning an impurity amorphous silicon layer (not shown) and a pure amorphous silicon layer (not shown) The surface damage of the active layer 115 of pure polysilicon of the area forming the region does not occur.

In this case, the gate electrode 107 of the impurity polysilicon (or a specific metal material having a predetermined thickness), the gate insulating layer 110, and the “H” shape which are sequentially stacked in the switching region TrA are formed. The active layer 115 of pure polysilicon, the interlayer insulating film 122, the ohmic contact layer 127 of impurity amorphous silicon, and the source and drain electrodes 133 and 136 form a thin film transistor Tr. In the case of forming a barrier pattern (not shown) of pure amorphous silicon, this also becomes a component of the thin film transistor Tr.

Meanwhile, after the source and drain electrodes 133 and 136 are formed, the ohmic contact layer 127 is patterned, that is, the second impurity amorphous silicon layer (not shown) is removed by performing dry etching. The part where the one hole 124 is formed is also exposed to the dry etching.

In this case, since the gate insulating film 110 is not completely removed from the inside of the first hole 124 during the BOE cleaning, the gate electrode 107 is dried by the gate insulating film 110. It can be protected without being exposed to etching.

On the other hand, although not shown in the drawings, in the case where the above-described array substrate is used as the array substrate for the organic light emitting device, the data wiring 130 is formed on the same layer in which the data wiring 130 is formed in parallel with the data wiring 130. Power wirings (not shown) may be further formed to be spaced apart from each other, and in addition to the thin film transistors Tr connected to the data lines 130 and the gate lines 145 of FIG. A plurality of driving thin film transistors (not shown) having the same structure may be further formed.

Next, as shown in FIGS. 4L and 5L, the source and drain electrodes of the substrate 101 having the data line 130, the source and drain electrodes 133 and 136, and the ohmic contact layer 127 are formed. The first protective layer 140 is formed by depositing an inorganic insulating material, for example, silicon nitride (SiNx), on the 133 and 136 and the data line 130.

Subsequently, a mask process is performed to remove the gate electrode 107 having a relatively thin thickness from the first protective layer 140 corresponding to the first hole 124, thereby removing the active layer of pure amorphous silicon. The gate contact hole 142 exposing the gate electrode 107 exposed to the outside is formed. In this case, due to the characteristics of the present invention, the interlayer insulating film 122 is formed when the active contact hole 123 is formed at the same time as the first hole 124 is removed, and the gate insulating film 110 during BOE cleaning. Since the thickness is substantially reduced, the formation time of the gate contact hole 142 for exposing the gate electrode 107 is shortened.

When the gate contact hole 142 is formed without the first hole 124 formed, the first protective layer 140, the interlayer insulating layer 122, and the gate insulating layer 110 have the same thickness. Since the dry time has to be progressed for the inorganic material layer of, the dry etching time becomes relatively long, which may lower productivity per unit time.

However, in the manufacturing method according to the embodiment of the present invention, the upper portion of the gate electrode 107 exposed to the outside of the active layer 115 of pure polysilicon without increasing the process time at the same time when the active contact hole 123 is formed. The first hole 124 is formed by removing the interlayer insulating layer 122 positioned at the gate, and finally reduces the thickness of the gate insulating layer 110 exposed through the first hole 124 through BOE cleaning. When the contact hole 142 is formed, the process time is shortened by reducing the number and thickness of material layers to be removed through a dry time.

Meanwhile, the first contact hole 124 is formed outside the gate contact hole 142 exposing the gate electrode 107 by such a process characteristic, thereby forming a form in which a double hole is formed in plan view. .

Next, as shown in FIGS. 4M and 5M, a second metal material such as aluminum (Al), over the first protective layer 140 having the gate contact hole 142 into the first hole 124, Aluminum alloys (AlNd), copper (Cu), copper alloys, molybdenum (Mo) and chromium (Cr) are deposited to form a second metal layer (not shown), and patterned by a mask process to form the gate contact hole ( A gate line 145 is formed to contact the gate electrode 107 exposed through 142 and intersect the data line 130 at a boundary of each pixel area P. In this case, the gate wiring 145 may be formed of only one metal material of the above-described second metal material to form a single layer structure, or may form a double layer or triple layer structure by depositing two or more different second metal materials. It may be. For example, the double layer structure may be made of aluminum alloy (AlNd) / molybdenum (Mo), the triple layer may be made of molybdenum (Mo) / aluminum alloy (AlNd) / molybdenum (Mo). In the figure, the gate wiring 145 having a single layer structure is shown.

Next, as shown in FIGS. 4N and 5N, the second protection may be performed by depositing an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the entire surface of the substrate 101 over the gate wiring 145. Form layer 150. Subsequently, a drain process hole exposing the drain electrode 136 to each switching region TrA by patterning the second passivation layer 150 and the first passivation layer 140 under the mask process is performed. 152 is formed.

Next, as shown in FIGS. 4O and 5O, a transparent conductive material, such as indium-tin-oxide, is formed on the entire surface of the substrate 101 over the second protective layer 150 including the drain contact hole 152. (ITO) or indium-zinc-oxide (IZO) by depositing and patterning the same, and then masking the pixel to contact the drain electrode 136 through the drain contact hole 152 in the pixel region P By forming the electrode 170, the array substrate 101 according to the embodiment of the present invention is completed.

Although not shown in the drawings, when a driving thin film transistor (not shown) is formed in each pixel region P, the thin film transistor Tr formed in the switching region TrA is connected to the pixel electrode 170. Instead of contacting, a drain contact hole formed by exposing the drain electrode (not shown) of the pixel electrode 170 and the driving thin film transistor (not shown) instead of the drain electrode of the driving thin film transistor (not shown). It is formed to be electrically connected by contacting through (not shown). In this case, the thin film transistor Tr formed in the switching region TrA is completely covered by the first and second protective layers 140 and 150 without forming the drain contact hole 152. In addition, the thin film transistor Tr of the switching region TrA and the driving thin film transistor (not shown) are configured to be electrically connected to each other. In the case of an array substrate in which a thin film transistor Tr connected to the gate and data lines 145 and 130 and a driving thin film transistor (not shown) are formed in the pixel region P in the switching region TrA. The array substrate is formed.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.

2A through 2E are cross-sectional views illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;

3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor having a polysilicon semiconductor layer in the related art.

4A through 4O are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention.

5A through 5O are plan views of manufacturing steps for a portion in which a thin film transistor of an array substrate is formed according to an exemplary embodiment of the present invention.

6 is a schematic view of a switching area of an array substrate having an active layer of a rectangular shape according to a comparative example.

FIG. 7 is a photograph of a switching region of an actual array substrate completed by processing based on the schematic shown in FIG. 6. FIG.

FIG. 8 is an enlarged photograph of a portion where an active contact hole is formed in FIG. 7; FIG.

<Description of Symbols for Main Parts of Drawings>

101 substrate 107 gate electrode

115: active layer of pure polysilicon

123: active contact hole 124: first hole

133: source electrode 136: drain electrode

142: gate contact hole 150: second protective layer

152: drain contact hole

Claims (13)

A gate electrode formed of an impurity polysilicon in an island shape in the switching region on the substrate on which the pixel region and the switching region are defined; A gate insulating film formed on the gate electrode and having the same planar shape as the gate electrode; A pure poly formed in an H-shape having an edge portion of the gate insulating film over the gate insulating film, the center portion having a first width in plan view, and both sides thereof having a second width larger than the first width based on the center portion. An active layer of silicon; First and second active contact holes exposing portions having a second width of the active layer, respectively, and first holes exposing the gate insulating layer corresponding to the gate electrode located outside the active layer, An interlayer insulating film formed on the entire surface of the substrate;  An ohmic contact layer of impurity amorphous silicon formed in the switching region in contact with the active layer through the first and second active contact holes and spaced apart from each other; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing the gate electrode to the inside of the first hole over the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the second passivation layer; And an interval between the first and second active contact holes positioned at both sides of the active layer having a first width corresponding to a central portion of the active layer having a first width. The method of claim 1, The first and second active contact holes are short axis has a curved shape, the major axis is a straight line, characterized in that the long axis of the first active contact hole and the second active contact hole is formed so that the long axis is facing each other Board. The method of claim 1, The center portion of the active layer having the first width is not formed in the separation region between the short axis of the first active contact hole having a curved shape and the short axis of the second active contact hole, and the first active contact having the straight shape. And a separation region between the long axis of the hole and the long axis of the second active contact hole. The method of claim 1, And the gate insulating layer has a portion where the first hole is formed to have a thickness thinner than that of other regions. The method of claim 1, An array substrate comprising a barrier pattern formed of pure amorphous silicon between the active layer and each of the ohmic contact layers, having the same planar shape as that of the ohmic contact layer, completely overlapping, and having a thickness of 50 μs to 300 μs. The method of claim 1, And the gate insulating layer is formed of silicon oxide (SiO ₂ ). Forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; A gate insulating film formed of a gate electrode and silicon oxide in an island shape in the switching region over the buffer layer, and an edge portion of the gate insulating film, the center portion having a first width in plan view, and both sides of the first portion with respect to the center portion; Forming an active layer of pure polysilicon to form an H shape with a second width greater than the width; Depositing and patterning an inorganic insulating material over the active layer on the entire surface to form an interlayer insulating film having first and second active contact holes spaced apart from each other to expose portions having a first width of the active layer; Forming an ohmic contact layer of impurity amorphous silicon that is in contact with the active layer and spaced apart from each other through the first and second active contact holes, and a source and drain electrode spaced apart from each other on the ohmic contact layer, Simultaneously forming a data line connected to the source electrode on a boundary of the pixel area over the interlayer insulating film; Forming a first passivation layer having a gate contact hole exposing the gate electrode over the data line and the source and drain electrodes; Forming a gate wiring on the boundary of the pixel area over the first passivation layer, the gate wiring contacting the gate electrode through the gate contact hole and crossing the data wiring; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method of manufacturing an array substrate comprising a. The method of claim 7, wherein Forming an interlayer insulating film having the first and second active contact holes includes forming a first hole exposing the gate insulating film outside the active layer; Before forming the ohmic contact layer, a buffered oxide etchant is used to reduce oxide thickness on the surface of the active layer exposed through the first and second active contact holes and to reduce the thickness of the gate insulating layer exposed through the first hole. ) Performing a cleaning, And the gate contact hole is formed inside the first hole. The method of claim 8, Forming a first passivation layer having a gate contact hole exposing the gate electrode on the front surface over the data line and the source and drain electrodes, Depositing an inorganic insulating material over the data line and the source and drain electrodes to form the first protective layer; Forming the gate contact hole by performing dry etching on the first passivation layer located inside the first hole and the gate insulating layer thinned below Method of manufacturing an array substrate comprising a. The method of claim 7, wherein A gate insulating film formed of a gate electrode and silicon oxide in an island shape in the switching region over the buffer layer, and an edge portion of the gate insulating film, the center portion having a first width in plan view, and both sides of the first portion with respect to the center portion; Forming an active layer of pure polysilicon to have a second width greater than the width to form an H shape, Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; An edge of the gate electrode exposed to the outside of the active layer is formed by forming a first photoresist pattern having a first thickness corresponding to a portion where the H-shaped active layer is formed in the switching region over the pure polysilicon layer. Forming a second photoresist pattern having a second thickness thinner than the first thickness corresponding to the portion; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a pure polysilicon pattern with a gate electrode and a gate insulating film of silicon; Exposing the edges of the pattern of the pure polysilicon outside the first photoresist pattern by ashing to remove the second photoresist pattern; Forming the H-shaped active layer by removing the pure polysilicon pattern exposed to the outside of the first photoresist pattern, and simultaneously exposing an edge of the gate insulating layer; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. The method of claim 7, wherein The gate electrode made of impurity polysilicon is formed to have a thickness of about 500 kPa to 1000 kPa, and the active layer of the H-shaped pure polysilicon is formed to have a thickness of about 300 kPa to 1000 kPa. . The method of claim 7, wherein The solid phase crystallization process is characterized in that the crystallization or alternating magnetic field crystallization using alternating magnetic field crystallization (AMFC) device through a heat treatment of 600 ℃ to 800 ℃. The method of claim 7, wherein Forming an ohmic contact layer of impurity amorphous silicon that is in contact with the active layer and spaced apart from each other through the first and second active contact holes, and a source and drain electrode spaced apart from each other on the ohmic contact layer, At the same time, forming a data line connected to the source electrode on the boundary of the pixel area over the interlayer insulating film, A barrier formed of pure amorphous silicon between the active layer and the ohmic contact layer inside each of the first and second active contact holes, having the same planar shape as that of the ohmic contact layer, completely overlapping, and having a thickness of 50 s to 300 s A method of manufacturing an array substrate comprising forming a pattern.

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