KR20100122390A - Array substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate and a method of fabricating thereof are provided to prevent a damage of surface of an active layer. CONSTITUTION: An array substrate is prepared by a step of the followings. A pixel area, a gate electrode(107), a gate insulating layer(109) and an active layer(115) are formed. A gate line(118) is formed. An ohmic contact layer(127), source and drain electrodes(133,136) are formed. A data line(130) is formed. A protective layer is formed. A pixel electrode is formed. An etch stopper is formed to facing with the center of the active layer. In the etching for the patterning of the ohmic contact layer, the etching effect is prevented to the active layer.

Description

Array substrate and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and more particularly, to a thin film transistor array substrate having an active layer having excellent mobility characteristics and suppressing surface damage generation of the active layer by dry etching.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling the voltage on / off of each pixel, realizes resolution and video. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each pixel area on / off.

FIG. 1 is a cross-sectional view of a pixel area including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting display device.

As illustrated, the gate electrode 15 is disposed in the switching region TrA in the plurality of pixel regions P defined by the plurality of gate lines (not shown) and the data lines 33 intersecting on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, and the characteristic difference of the thin film transistor (Tr) occurs due to the thickness difference (t1 ≠ t2) of the active layer 22. have.

2A through 2E are cross-sectional views illustrating a process of forming a semiconductor layer, a source, and a drain electrode during a manufacturing process of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

First, as shown in FIG. 2A, the pure amorphous silicon layer 20 is formed on the substrate 11, and the impurity amorphous silicon layer 24 and the metal layer 30 are sequentially formed thereon. Thereafter, a photoresist is formed on the metal layer 30 to form a photoresist layer (not shown), and the photoresist is exposed using an exposure mask, and subsequently developed to correspond to a portion where the source and drain electrodes are to be formed. A first photoresist pattern 91 having a thickness is formed, and at the same time, a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed to correspond to the spaced area between the source and drain electrodes. .

Next, as shown in FIG. 2B, the metal layer (30 of FIG. 2A) exposed to the outside of the first and second photoresist patterns 91 and 92, an impurity and a pure amorphous silicon layer below it (of FIG. 2A) 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top, and an impurity amorphous silicon pattern 25 and an active layer 22 below.

Next, as shown in FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by ashing. In this case, the first photoresist pattern (91 in FIG. 2B) having the third thickness forms the third photoresist pattern 93 while the thickness thereof is reduced, and remains on the source drain pattern 31.

Next, as illustrated in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching by removing the source drain pattern 31 of FIG. 2C exposed to the outside of the third photoresist pattern 93. To form. In this case, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the source and drain electrodes are dry-etched on the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the separation region between the source and drain electrodes 36 and 38. (36, 38) An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside of the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (Fig. Even a portion of the active layer 22 disposed below 25) of 2d may have a predetermined thickness etched at a portion where the impurity amorphous silicon pattern (25 of FIG. 2d) is removed. Therefore, a difference (t1 ≠ t2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (25 of FIG. 2D) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22. This is to prevent this.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer (20 in FIG. 2A) forming the active layer 22 is sufficiently thick in consideration of the thickness of the active layer 22 that is etched and removed during the dry etching process for forming the ohmic contact layer 26. It must be deposited thick enough, resulting in increased deposition time and reduced productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier is low at 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the manufacturing of the array substrate 51 including the thin film transistor (Tr) used as a 55) of the n + region 55b or the p + region (not shown) containing a high concentration of impurities in the polysilicon semiconductor layer 55 Requires formation. Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching, thereby preventing damage to the surface thereof, thereby improving characteristics of the thin film transistor. .

Furthermore, another object of the present invention is to provide a method of manufacturing an array substrate having a thin film transistor capable of improving a mobility property while forming a semiconductor layer using polysilicon, without requiring a doping process.

According to an aspect of the present invention, there is provided a method of fabricating an array substrate, wherein a gate region of an impurity polysilicon and an gate of an impurity polysilicon are formed in an island form in a pixel region and the switching region on a substrate in which the switching region is defined in the pixel region. Forming a gate insulating film and an active layer of pure polysilicon sequentially stacked while exposing one side; Forming a gate wiring as a metal material and in contact with the gate electrode exposed to the outside of the active layer and extending in one direction at a boundary of the pixel region; Depositing and patterning an inorganic insulating material over the active layer and the gate wiring to form an interlayer insulating film covering the gate wiring, the active contact hole exposing and spaced apart from the active layer; Forming an ohmic contact layer of impurity amorphous silicon in contact with the active layer and spaced apart from the active layer through the active contact hole, and a source and a drain electrode spaced apart from each other over the ohmic contact layer, and simultaneously on the interlayer insulating layer Forming a data line connected to a source electrode and crossing the gate line to define the pixel area; Forming a protective layer having a drain contact hole exposing the drain electrode on a front surface of the data line and the source and drain electrodes; Forming a pixel electrode on the protective layer in contact with the drain electrode through the drain contact hole in the pixel region.

The step of forming a gate insulating film and an active layer of pure polysilicon sequentially stacked while exposing a gate electrode of impurity polysilicon and one side of the gate electrode in an island form in the switching region on the substrate may include an impurity amorphous layer over the substrate. Sequentially stacking a silicon layer, a second inorganic insulating layer, and a pure amorphous silicon layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; A first photoresist pattern having a first thickness is formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and the first to correspond to the gate electrode exposed to the outside of the active layer. Forming a second photoresist pattern having a second thickness thinner than the thickness; The pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the second inorganic insulating layer and the impurity polysilicon layer underneath are sequentially removed and sequentially stacked in the switching region on the substrate. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of the impurity polysilicon; Exposing the one side of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing one side of the gate electrode of the impurity polysilicon by removing the pure polysilicon pattern exposed to the outside of the first photoresist pattern and the inorganic insulating pattern thereunder; And removing the first photoresist pattern, wherein the solid phase crystallization process is alternating magnetic field crystallization using crystallization or alternating magnetic field crystallization (AMFC) device through heat treatment.

Forming a buffer layer over the substrate as an inorganic insulating material on the substrate before forming the gate electrode.

Forming a barrier layer formed of pure amorphous silicon under the ohmic contact layer having the active contact hole and having a thickness of 50 μs to 100 μm and contacting the active layer through the active contact hole. .

The barrier layer, the ohmic contact layer, and the source and drain electrodes are patterned and formed at the same time by performing the same mask process. The barrier layer, the ohmic contact layer, and the gate electrode of the impurity polysilicon are sequentially stacked in the same size. It has a thickness of about 1000 kPa, and the active layer of the pure polysilicon is characterized in that it is formed to have a thickness of about 400 kPa to 600 kPa.

 An array substrate according to the present invention includes a pixel region and a gate electrode of impurity polysilicon formed in an island shape in the switching region on a substrate on which a switching region is defined in the pixel region; An active layer of a gate insulating film and pure polysilicon formed sequentially stacked to expose one side of the gate electrode; A gate wiring made of a metal material and in contact with the gate electrode exposed to the outside of the active layer and formed at a boundary of the pixel region; An interlayer insulating layer having an active contact hole spaced apart from each other and exposing the active layer over the active layer and the gate line, and having an center portion of the active layer serving as an etch stopper; An ohmic contact layer of impurity amorphous silicon formed in the switching region and spaced apart from the active layer through the active contact hole, respectively, in the switching region; Source and drain electrodes spaced apart from each other on the ohmic contact layer in the switching region; A data line connected to the source electrode at a boundary of the pixel area over the interlayer insulating layer and defining the pixel area to cross the gate line; A protective layer having a drain contact hole exposing the drain electrode over the data line and the source and drain electrodes; And a pixel electrode formed on the protective layer and in contact with the drain electrode through the drain contact hole.

A barrier layer made of pure amorphous silicon and having a thickness of 50 GPa to 100 GPa between the active layer of the pure polysilicon and the ohmic contact layer of the impurity polysilicon, the front surface between the gate electrode of the impurity polysilicon and the substrate It includes a buffer layer made of an inorganic insulating material.

The gate electrode of impurity polysilicon has a thickness of 500 kPa to 1000 kPa, and the active layer of pure polysilicon has a thickness of 400 kPa to 600 kPa.

By the method of manufacturing the array substrate according to the present invention, the active layer is not exposed to dry etching, and thus, surface damage does not occur, thereby preventing the thin film transistor characteristic from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

The array substrate manufactured by the manufacturing method according to the present invention comprises a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the mobility characteristics by several tens to several hundred times compared to one array substrate.

Since the active layer of polysilicon is used as the semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In addition, by forming the gate electrode made of polysilicon containing impurities, problems such as deformation of the gate electrode generated during the crystallization process of the conventional array substrate in which the gate electrode of the metal material is formed or short circuit between the gate electrode and the semiconductor layer are eliminated. There is an effect to solve at the source.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

4A to 4L are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor connected to the gate and the data line in each pixel region P is to be formed is defined as a switching region TrA.

First, as shown in FIG. 4A, by depositing impurity amorphous silicon on the transparent substrate 101, a first impurity amorphous silicon layer 105 having a thickness of about 500 mW to 1000 mW is formed. Subsequently, an inorganic insulating material, such as silicon oxide (SiO ₂ ), is deposited on the first impurity amorphous silicon layer 105 in succession to form a first inorganic insulating layer 108 having a thickness of about 1000 to 4000 microns. By depositing pure amorphous silicon on top, a pure amorphous silicon layer 110 having a thickness of about 400 kPa to 600 kPa is formed.

In this case, the formation of the first impurity amorphous silicon layer 105, the first inorganic insulating layer 108, and the pure amorphous silicon layer 110 is performed by chemical vapor deposition (CVD) equipment (not shown). Through). Thus, these three layers 105, 108, 110 are characterized in that they are formed continuously by changing only the reaction gases injected into the chamber (not shown) of the chemical vapor deposition (CVD) equipment (not shown). In this case, the pure amorphous silicon layer 110 is formed in a thickness of about 800 kPa to 1000 kPa in consideration of the conventional etching to expose the dry etching to remove some of the thickness from the surface, but in the embodiment of the present invention, Since the active layer of polysilicon (115 of FIG. 4L) finally implemented through the pure amorphous silicon layer 110 is not exposed to dry etching, the pure amorphous silicon layer 110 may reduce the material cost and shorten the unit process time. It is preferable to form to have a relatively thin thickness of about 400 kPa to 600 kPa.

Although not shown in the drawings, an inorganic insulating material such as silicon oxide (SiO ₂ ) or nitride is preferentially formed on the substrate 101 prior to forming the first impurity amorphous silicon layer 105 on the substrate 101. A buffer layer (not shown) may be further formed by depositing silicon (SiNx). In this case, since the formation of the buffer layer (not shown) also uses the chemical vapor deposition (CVD) equipment, the first impurity amorphous silicon layer 105 and the first inorganic insulating layer 108 including the buffer layer (not shown) are included. ) And the pure amorphous silicon layer 110 may be sequentially stacked without exposure to air in the same chamber of chemical vapor deposition (CVD) equipment.

Next, as shown in FIG. 4B, the pure amorphous silicon layer (SPC) process is performed to improve the mobility characteristics of the pure amorphous silicon layer (110 of FIG. 4A) and the like. 110 of 4a is crystallized to form the pure polysilicon layer 111. In this case, the solid phase crystallization (SPC) is preferably an alternating magnetic field crystallization using an crystallization or alternating magnetic field crystallization (AMFC) device through heat treatment as an example.

On the other hand, as a result of the solid phase crystallization process, not only the pure amorphous silicon layer (110 of FIG. 4A) but also the impurity amorphous silicon layer (105 of FIG. 4A) disposed under the first inorganic insulating layer (108 of FIG. 4A) is also crystallized. As a result, the impurity polysilicon layer 106 is formed.

Next, as shown in FIG. 4C, a photoresist is applied onto the pure polysilicon layer 111 formed by crystallizing the pure amorphous silicon layer (110 of FIG. 4A) by the solid state crystallization (SPC) process. A layer (not shown) is formed, and a light transmitting region, a blocking region (not shown), and a slit form of the photoresist layer (not shown) or a plurality of coating layers are further provided to control the amount of light passing through. Thus, diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a semi-transmissive area (not shown) whose light transmittance is smaller than the transmission area (not shown) and larger than the blocking area (not shown). do.

Thereafter, by developing the exposed photoresist layer (not shown), a part of the portion where the gate electrode 107 of FIG. 4L should be formed on the pure polysilicon layer 111 corresponding to the switching region TrA (to be formed later) The first photoresist pattern 191a having a first thickness is formed to correspond to the active layer of the pure polysilicon (the portion not overlapping with 115 of FIG. 4L), and the gate electrode (107 of FIG. 4L) is formed. The second photoresist pattern 191b having a second thickness thicker than the first thickness is formed to correspond to the portion of the portion to be formed of the active layer of pure polysilicon (115 of FIG. 4L). Therefore, a second photoresist pattern 191b having a second thickness is formed to correspond to a portion of the portion where the gate electrode 107 of FIG. 4L is to be formed and overlaps with the active layer of 115 of FIG. 4L. The first photoresist pattern 191a having the first thickness is formed in an area where the active layer (115 of FIG. 4L) of pure polysilicon is not formed among the portions where the gate electrode (107 of FIG. 4L) is to be formed. All regions on the substrate 101 on which the gate electrode 107 of FIG. 4L is not formed are removed to form the pure polysilicon layer 111 by removing the photoresist layer (not shown).

Next, as shown in FIG. 4D, the pure polysilicon layer (111 of FIG. 4C) exposed to the outside of the first and second photoresist patterns 191a and 191b and the first inorganic insulating layer disposed below the pure polysilicon layer are disposed. A gate electrode 107 made of impurity polysilicon sequentially stacked as an island form in the switching region TrA by sequentially etching and removing the layer (108 in FIG. 4C) and the impurity polysilicon layer (106 in FIG. 4C); The gate insulating film 109 and the pure polysilicon pattern 112 are formed thereon. In this case, in a region other than the switching region TrA, when the surface of the substrate 101 or the buffer layer (not shown) is formed, the buffer layer (not shown) is exposed.

Meanwhile, in the embodiment of the present invention, forming the gate electrode 107 with pure impurity polysilicon instead of a metal material may occur when the polysilicon pattern 112 formed on the gate electrode 107 is formed. To solve the problem. In the case of forming a thin film transistor having a bottom gate structure, a gate electrode is formed of a metal material on a substrate, and a pure amorphous silicon layer is formed on the substrate through a gate insulating film to form a semiconductor layer. The solid phase crystallization from the polysilicon layer requires a relatively high temperature of 600 ° C or higher. Accordingly, during the solid phase crystallization process requiring a relatively high temperature, the gate electrode made of a metal material may be deformed or may have spikes that come into contact with the crystallized pure polysilicon layer through the gate insulating layer. Causes Accordingly, in the embodiment of the present invention, the gate electrode 107 is formed by using impurity polysilicon that does not cause the above-mentioned problems at high temperature in order to solve the problem occurring during the crystallization process by forming the gate electrode of the metal material. It is. In the case of the gate electrode 107 made of impurity polysilicon, the conductivity is lower than that of the metal material. However, when the thickness of the gate electrode 107 of the impurity polysilicon is 500 kW to 1000 kW, the resistance value per unit area is 150 kW / sq (□) to 230 mW / sq (□), which is similar to that of indium tin oxide (ITO) or indium zinc oxide (IZO). Accordingly, it has been found experimentally that there is no problem in performing a role as a gate electrode such as forming a channel in the active layer even if the gate electrode is formed of impurity polysilicon.

Next, as illustrated in FIG. 4E, ashing is performed on the substrate 101 on which the gate electrode 107, the gate insulating layer 109, and the pure polysilicon pattern 112 of the impurity polysilicon are formed. By removing the first photoresist pattern 191a of FIG. 4D having a first thickness, one side of the pure polysilicon pattern 112 is exposed to the outside of the second photoresist pattern 191b in the switching region TrA. Let's do it. The ashing process also reduces the thickness of the second photoresist pattern, but still remains on the pure polysilicon pattern 112.

 Next, as shown in FIG. 4F, the pure polysilicon pattern (112 in FIG. 4E) and the gate insulating layer 109 disposed below the second photoresist pattern (191b in FIG. 4E) are etched away. By removing, a part of the gate electrode 107 of the impurity polysilicon is exposed. In this case, the pure polysilicon pattern (112 of FIG. 4E) remaining without being etched by the second photoresist pattern 191b of FIG. 4E forms the active layer 115 of pure polysilicon. In this case, in the exemplary embodiment according to the present disclosure, the active layer 115 of the pure polysilicon and the gate insulating layer 109 disposed below the pure polysilicon have the same shape and size with respect to the entire surface of the substrate 101. It is characterized by being formed.

Next, as shown in FIG. 4G, the pure polysilicon is removed by performing a strip to remove the second photoresist pattern (191b of FIG. 4F) remaining on the active layer 115 of the pure polysilicon. The active layer 115 is exposed.

Next, as shown in FIG. 4H, a metal material such as aluminum (Al), aluminum alloy (AlNd), copper is formed on the exposed active layer 115 of pure polysilicon and the gate electrode 107 of impurity polysilicon. (Cu), copper alloy, molybdenum (Mo), and chromium (Cr) are deposited to form a first metal layer, which is coated with a photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, etc. Patterning is performed by a mask process including a unit process of to form a gate wiring 118 that contacts the gate electrode 107 of the exposed impurity polysilicon and extends in one direction at the boundary of each pixel region P. Referring to FIG. In this case, the gate wiring 118 may be formed of only one metal material of the above-described metal material to form a single layer structure, or may form a double layer or triple layer structure by depositing two or more different metal materials. For example, the double layer structure may be made of aluminum alloy (AlNd) / molybdenum (Mo), the triple layer may be made of molybdenum (Mo) / aluminum alloy (AlNd) / molybdenum (Mo). In the figure, the gate wiring 118 of a single layer structure is shown.

Next, as shown in FIG. 4I, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 118 and the active layer 115 of pure polysilicon. An inorganic insulating layer (not shown) is formed.

Subsequently, the second inorganic insulating layer (not shown) is subjected to a mask process including a series of unit processes such as application of photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, and the like. By patterning, the center portion of the active layer 115 of pure polysilicon covers the active layer 115 of pure polysilicon to serve as an etch stopper, and the interlayer insulating layer serves as an insulating layer to correspond to other regions. And form 122. In this case, the interlayer insulating layer 122 formed on the active layer 115 of pure polysilicon may be formed on both sides of the active layer 115 of the pure polysilicon based on the center of the active layer 115 of the pure polysilicon. It is characterized in that the active contact hole 125 is formed to expose.

Next, as shown in FIG. 4J, an active contact hole 125 is formed to correspond to the active layer of the pure polysilicon and is exposed on the entire surface above the interlayer insulating layer 122 serving as an etch stopper. The impurity amorphous silicon is deposited to form a second impurity amorphous silicon layer (not shown) having a thickness of about 100 GPa to 300 GPa. Thereafter, a second metal layer (not shown) is formed by depositing any one of a metal material, for example, molybdenum (Mo), chromium (Cr), and molybdenum (MoTi), on the second impurity amorphous silicon layer (not shown). do.

Meanwhile, before forming the second impurity amorphous silicon layer (not shown) on the interlayer insulating layer 122 having the active contact hole 125, pure amorphous silicon is first deposited on the entire surface of the substrate 101 to have a thickness of about 50 μs to about 100 μs. Barrier layer (not shown) may be further formed. In this case, the reason for forming a barrier layer (not shown) made of pure amorphous silicon is that the barrier layer (not shown) is formed between the active layer 115 of the pure polysilicon and the impurity amorphous silicon layer (not shown). This is to improve the bonding force between the two layers 115 (not shown) by being interposed. That is, the bonding strength of the pure polysilicon with the active layer 115 is because pure amorphous silicon is more excellent than impurity amorphous silicon. However, the barrier layer (not shown) made of pure amorphous silicon is not necessarily formed and may be omitted.

Next, the second metal layer (not shown) and the second impurity amorphous silicon layer (not shown) disposed thereunder are patterned by performing a mask process so that the boundary between the pixel regions P is disposed on the interlayer insulating layer 122. The data line 130 defining the pixel area P is formed to cross the gate line 118. At the same time, in the switching region TrA, source and drain electrodes 133 and 136 spaced apart from each other are formed on the interlayer insulating layer 122 and impurity amorphous silicon is formed under the source and drain electrodes 133 and 136. The ohmic contact layer 127 is formed to contact the active layer 115 of pure polysilicon through the active contact hole 125. In this case, the source electrode 133 and the data line 130 formed in the switching region TrA are connected to each other.

On the other hand, when a barrier layer (not shown) is formed, the barrier layer (not shown) is formed under the ohmic contact layer 127 formed under the source and drain electrodes 133 and 136, and the barrier layer (Not shown) forms a structure in which the active layer 115 of pure polysilicon contacts with the active contact hole 125.

In addition, a first dummy pattern 128 made of impurity amorphous silicon is formed under the data line 130 by the above-described process, and when the barrier layer (not shown) is formed, the first dummy pattern 128 is formed. A second dummy pattern (not shown) made of pure amorphous silicon is formed under the pattern 128.

In the process of forming the data line 130 and the source and drain electrodes 133 and 136, the arch stopper 120 corresponds to the central portion of the active layer 115 of pure polysilicon forming the channel region. Since the source and drain electrodes 133 and 136 are formed, the active layer 115 of pure polysilicon has no influence at all in the etching of the ohmic contact layer 127, for example, during dry etching. Will not receive. Therefore, it can be seen that the surface damage of the active layer due to the problem dry etching process mentioned in the prior art does not occur. That is, after forming the data line 130 and the source and drain electrodes 133 and 136 by patterning the second metal layer (not shown), the data wire 130 and the source and drain electrodes 133, 136) The removal of the impurity amorphous silicon layer (not shown) exposed to the outside is performed by dry etching. In this case, between the source and drain electrodes 133 and 136 in the switching region TrA. Since the interlayer insulating film 122 serving as an etch stopper is formed, the active layer 115 of pure polysilicon is not affected by the dry etching. Therefore, unlike conventional array substrate fabrication, when the ohmic contact layer 127 is formed by patterning an impurity amorphous silicon layer (not shown), surface damage of the active layer 115 of pure polysilicon by dry etching does not occur. The thickness of the active layer 115 of pure polysilicon is also not reduced, so that the active layer 115 of pure polysilicon has a constant thickness in the entire switching region TrA.

At this time, the gate electrode 107 of the impurity polysilicon, the gate insulating film 109, the active layer 115 of pure polysilicon, the interlayer insulating film 122, which are sequentially stacked in the switching region TrA, The ohmic contact layer 127 of impurity amorphous silicon and the source and drain electrodes 133 and 136 form a thin film transistor Tr.

Although not shown in the drawing, when used as an array substrate for an organic light emitting device, the data line 130 is spaced apart from the data line 130 in the same layer on which the data line 130 is formed in parallel with the data line 130. A power supply wiring (not shown) may be further formed, and in each pixel region P, a plurality of structures having the same structure besides the thin film transistor Tr connected to the gate wiring 118 and the data wiring 130 described above may be provided. A driving thin film transistor (not shown) may be further formed.

Next, as shown in FIG. 4K, the source and drain electrodes 133 and 136 of the substrate 101 having the data line 130, the source and drain electrodes 133 and 136, and the ohmic contact layer 127 are formed. ) And a protective layer 140 by depositing an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the data line 130 and by patterning the drain electrode by performing a mask process. A drain contact hole 143 exposing the 136 is formed.

Next, as shown in FIG. 4L, a transparent conductive material such as a metal material, indium-tin-oxide (ITO) or indium-ink-oxide, is disposed on the protective layer 140 including the drain contact hole 143. IZO) is deposited on the entire surface to form a transparent conductive material layer (not shown). Subsequently, the transparent conductive material layer (not shown) is patterned by performing a mask process so that the pixel electrode 150 contacting the drain electrode 136 through the drain contact hole 143 for each pixel region P is formed. By forming, the array substrate 101 according to the embodiment of the present invention is completed.

Although not shown in the drawings, when a driving thin film transistor (not shown) is formed in each of the pixel regions P, the thin film transistor Tr formed in the switching region TrA is connected to the pixel electrode 150. A drain contact hole formed without exposing the drain electrode (not shown) of the driving thin film transistor (not shown) to expose the pixel electrode 150 and the drain electrode (not shown) of the driving thin film transistor (not shown). It is formed to be electrically connected by contacting through (not shown). In this case, the thin film transistor Tr formed in the switching region TrA is completely covered by the protective layer 140 without the drain contact hole 143 being formed. In addition, the thin film transistor Tr of the switching region TrA and the driving thin film transistor (not shown) are configured to be electrically connected to each other. In the case of an array substrate in which a thin film transistor Tr connected to the gate and data lines 118 and 130 and a driving thin film transistor (not shown) are formed in the pixel region P in the switching region TrA. The array substrate is formed.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.

2A through 2E are cross-sectional views illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;

3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor having a polysilicon semiconductor layer in the related art.

4A to 4L are cross-sectional views illustrating manufacturing steps of one pixel region including a thin film transistor of an array substrate according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101 substrate 107 gate electrode of impurity polysilicon

109: gate insulating film 115: active layer of pure polysilicon

118 gate wiring 122 interlayer insulating film

125: active contact hole 127: ohmic contact layer of impurity amorphous silicon

128: first dummy pattern 130: data wiring

133: source electrode 136: drain electrode

P: Pixel Area Tr: Thin Film Transistor

TrA: switching area

Claims (11)

A gate insulating film and an active layer of pure polysilicon are sequentially stacked while exposing a gate electrode of impurity polysilicon and one side of the gate electrode in an island form to the pixel region and the switching region on the substrate where the switching region is defined in the pixel region. Forming a layer; Forming a gate wiring as a metal material and in contact with the gate electrode exposed to the outside of the active layer and extending in one direction at a boundary of the pixel region; Depositing and patterning an inorganic insulating material over the active layer and the gate wiring to form an interlayer insulating film covering the gate wiring, the active contact hole exposing and spaced apart from the active layer;  Forming an ohmic contact layer of impurity amorphous silicon in contact with the active layer and spaced apart from the active layer through the active contact hole, and a source and a drain electrode spaced apart from each other over the ohmic contact layer, and simultaneously on the interlayer insulating layer Forming a data line connected to a source electrode and crossing the gate line to define the pixel area; Forming a protective layer having a drain contact hole exposing the drain electrode on a front surface of the data line and the source and drain electrodes; Forming a pixel electrode on the protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method of manufacturing an array substrate comprising a. The method of claim 1, Forming a gate insulating film and an active layer of pure polysilicon sequentially stacked while exposing a gate electrode of impurity polysilicon and one side of the gate electrode in an island form in the switching region on the substrate, Sequentially depositing an impurity amorphous silicon layer, a second inorganic insulating layer, and a pure amorphous silicon layer on the substrate; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; A first photoresist pattern having a first thickness is formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and the first to correspond to the gate electrode exposed to the outside of the active layer. Forming a second photoresist pattern having a second thickness thinner than the thickness; The pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the second inorganic insulating layer and the impurity polysilicon layer underneath are sequentially removed and sequentially stacked in the switching region on the substrate. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of the impurity polysilicon; Exposing the one side of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing one side of the gate electrode of the impurity polysilicon by removing the pure polysilicon pattern exposed to the outside of the first photoresist pattern and the inorganic insulating pattern thereunder; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. The method of claim 2, The solid phase crystallization process is characterized in that the crystallization through heat treatment or alternating magnetic field crystallization using alternating magnetic field crystallization (AMFC) device. The method of claim 1, Forming a buffer layer over the substrate as an inorganic insulating material on the substrate prior to forming the gate electrode. The method of claim 1, Forming a barrier layer formed of pure amorphous silicon under the ohmic contact layer having the active contact hole and having a thickness of 50 μs to 100 μs and contacting the active layer through the active contact hole. Method of manufacturing an array substrate. The method of claim 1, And the barrier layer, the ohmic contact layer, the source and the drain electrode are patterned and formed at the same time by performing the same mask process so as to sequentially form the same shape and the same size. The method of claim 1, The gate electrode of the impurity polysilicon has a thickness of about 500 kPa to 1000 kPa, and the active layer of the pure polysilicon is formed to have a thickness of about 400 kPa to 600 kPa. A gate electrode of impurity polysilicon formed in an island shape in the pixel region and in the switching region on the substrate on which the switching region is defined; An active layer of a gate insulating film and pure polysilicon formed sequentially stacked to expose one side of the gate electrode; A gate wiring made of a metal material and in contact with the gate electrode exposed to the outside of the active layer and formed at a boundary of the pixel region; An interlayer insulating layer having an active contact hole spaced apart from each other and exposing the active layer over the active layer and the gate line, and having an center portion of the active layer serving as an etch stopper;  An ohmic contact layer of impurity amorphous silicon formed in the switching region and spaced apart from the active layer through the active contact hole, respectively, in the switching region; Source and drain electrodes spaced apart from each other on the ohmic contact layer in the switching region; A data line connected to the source electrode at a boundary of the pixel area over the interlayer insulating layer and defining the pixel area to cross the gate line;  A protective layer having a drain contact hole exposing the drain electrode over the data line and the source and drain electrodes; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the passivation layer; Array substrate comprising a. The method of claim 8, An array substrate comprising a barrier layer made of pure amorphous silicon and having a thickness of 50 GPa to 100 GPa between the active layer of pure polysilicon and the ohmic contact layer of impurity polysilicon. The method of claim 8, And a buffer layer formed of an inorganic insulating material on an entire surface between the gate electrode of the impurity polysilicon and the substrate. The method of claim 8, And the gate electrode of the impurity polysilicon has a thickness of 500 mW to 1000 mW, and the active layer of the pure polysilicon has a thickness of 400 mW to 600 mW.

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