KR101484965B1 - Method of fabricating array substrate - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device, comprising: forming a polysilicon pattern in the switching region on a substrate; Forming an etch stopper corresponding to a central portion of the polysilicon pattern so that both sides of the polysilicon pattern are exposed; Performing phosphorus (PH ₃ ) plasma processing on the substrate on which the etch stopper is formed to cause phosphorus (P) to be implanted into both sides of the polysilicon pattern exposed to the outside of the etch stopper; Forming a first metal layer on the etch stopper over the entire surface of the etch stopper and performing a heat treatment so that both sides of the polysilicon pattern become ohmic contact layers having good conductivity; Removing the first metal layer; Forming a gate insulating film on the entire surface of the etch stopper; Forming a gate electrode corresponding to the etch stopper over the gate insulating film and simultaneously forming a gate wiring extending in one direction; Forming a protective layer over the gate wiring and the gate electrode, the protective layer having a semiconductor layer contact hole exposing the ohmic contact layer; Forming source and drain electrodes spaced apart from each other in contact with the ohmic contact layer through the semiconductor layer contact hole over the protective layer and forming a data line crossing the gate line and defining a pixel region over the protective layer ; And forming a pixel electrode in contact with the drain electrode for each pixel region on the source and drain electrodes.

Description

[0001] The present invention relates to a method of fabricating array substrate,

The present invention relates to an array substrate, and more particularly, to a method of fabricating a thin film transistor array substrate having an active layer which originally suppresses the surface damage of the active layer due to dry etching progress and has excellent mobility characteristics.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

An array substrate having a thin film transistor, which is essentially a switching element, is provided in order to commonly turn on and off each pixel region in the liquid crystal display device and the organic electroluminescent device.

FIG. 1 is a cross-sectional view of a conventional array substrate constituting the above-described liquid crystal display device or organic electroluminescent device including one pixel region including a thin film transistor.

A gate electrode 15 is formed in a switching region TrA in a plurality of pixel regions P in which a plurality of gate wirings (not shown) and a data wiring 33 are defined in the array substrate 11, And a gate insulating film 18 is formed on the entire surface of the gate electrode 15. An active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon A semiconductor layer 28 is formed. A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method and the characteristic difference of the thin film transistor Tr occurs due to the difference in thickness (t1? T2) of the active layer 22 have.

2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate. In the figure, the gate electrode and the gate insulating film are omitted for convenience of explanation.

First, as shown in FIG. 2A, a pure amorphous silicon layer 20 is formed on a substrate 11, and an impurity amorphous silicon layer 24 and a metal layer 30 are sequentially formed thereon. Thereafter, a photoresist layer is formed on the metal layer 30 to form a photoresist layer (not shown), exposing the photoresist layer using an exposure mask, and successively developing the photoresist layer, thereby forming a third And a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed corresponding to the spacing region between the source and drain electrodes .

Next, as shown in FIG. 2B, the metal layer (30 in FIG. 2A) exposed at the outside of the first and second photoresist patterns 91 and 92 and the impurities and the pure amorphous silicon layer 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top and an impurity amorphous silicon pattern 25 and an active layer 22 as a bottom portion.

Next, as shown in FIG. 2C, the second photoresist pattern (92 in FIG. 2B) of the fourth thickness is removed by performing ashing. In this case, the first photoresist pattern (91 of FIG. 2B) having the third thickness becomes a third photoresist pattern 93 in a reduced thickness and remains on the source drain pattern 31.

Next, as shown in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching away the source drain pattern (31 in FIG. 2C) exposed to the outside of the third photoresist pattern 93, . At this time, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the impurity amorphous silicon pattern (25 in FIG. 2D) exposed in the spacing region between the source and drain electrodes 36 and 38 is subjected to dry etching, The ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38.

At this time, the dry etching is performed for a sufficiently long time to completely eliminate the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38. In this process, the impurity amorphous silicon pattern A portion of the impurity amorphous silicon pattern (25 in FIG. 2D) is etched to a predetermined thickness even to the active layer 22 located at the lower portion of the impurity-amorphous silicon pattern 25 (FIG. 2D). Therefore, in the active layer 22, there is a difference in thickness (t1? T2) between the portion where the ohmic contact layer 26 is formed on the active layer 22 and the portion where the ohmic contact layer 26 is formed. If the dry etching is not performed for a sufficiently long time, the impurity amorphous silicon pattern (25 in FIG. 2D) to be removed in the spacing region between the source and drain electrodes 36 and 38 remains on the active layer 22 This is to prevent this.

Therefore, in the above-described conventional method of manufacturing the array substrate 11, inevitably, the thickness of the active layer 22 is different, and the characteristics of the thin film transistor (Tr in FIG. 1) deteriorates.

2A) which is thick enough to form the active layer 22 in consideration of the thickness at which the active layer 22 is etched and removed at the time of dry etching for forming the ohmic contact layer 26. The amorphous silicon layer The deposition must be sufficiently thick that the deposition time is increased and the productivity is lowered.

The most important constituent elements of the array substrate include a thin film transistor formed for each pixel region and connected to a gate line, a data line and a pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode .

However, in the case of a thin film transistor generally constituted in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using such an amorphous silicon, the amorphous silicon is disordered in its atomic arrangement. Therefore, the amorphous silicon changes to a metastable state upon irradiation with light or an electric field, and stability becomes a problem when used as a thin film transistor device. The carrier mobility is as low as 0.1 cm 2 / V · s to 1.0 cm 2 / V · s and it is difficult to use it as a device for a driving circuit.

In order to solve such a problem, a method of manufacturing a thin film transistor using polysilicon as an active layer by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by progressing a crystallization process using a laser device has been proposed.

3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate including a thin film transistor having a conventional polysilicon as a semiconductor layer, polysilicon is formed on the semiconductor layer Region 55b or a p + region (not shown) containing a high concentration of impurities is formed in the semiconductor layer 55 made of polysilicon, in order to manufacture the array substrate 51 including the thin film transistor Tr used as the p- need. Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the progress of the doping process. In this case, the manufacturing cost is increased, and a problem arises that a manufacturing line must be newly constructed for manufacturing the array substrate 51 by adding new equipment.

It is an object of the present invention to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching and the surface of the active layer is not damaged so that the characteristics of the thin film transistor are improved .

It is another object of the present invention to provide a method of manufacturing an array substrate including a thin film transistor which does not require a doping process and which can improve mobility characteristics even when the semiconductor layer is formed of polysilicon.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including forming a polysilicon pattern on the switching region on a substrate; Forming an etch stopper corresponding to a central portion of the polysilicon pattern so that both sides of the polysilicon pattern are exposed; Performing phosphorus (PH ₃ ) plasma processing on the substrate on which the etch stopper is formed to cause phosphorus (P) to be implanted into both sides of the polysilicon pattern exposed to the outside of the etch stopper; Forming a first metal layer on the etch stopper over the entire surface of the etch stopper and performing a heat treatment so that both sides of the polysilicon pattern become ohmic contact layers having good conductivity; Removing the first metal layer; Forming a gate insulating film on the entire surface of the etch stopper; Forming a gate electrode corresponding to the etch stopper over the gate insulating film and simultaneously forming a gate wiring extending in one direction; Forming a protective layer over the gate wiring and the gate electrode, the protective layer having a semiconductor layer contact hole exposing the ohmic contact layer; Forming source and drain electrodes spaced apart from each other in contact with the ohmic contact layer through the semiconductor layer contact hole over the protective layer and forming a data line crossing the gate line and defining a pixel region over the protective layer ; And forming a pixel electrode in contact with the drain electrode on each of the pixel regions over the source and drain electrodes.

The forming of the polysilicon pattern may include forming a buffer layer as an inorganic insulating material on the entire surface of the substrate; Forming an amorphous silicon layer over the buffer layer; Crystallizing the amorphous silicon layer into a polysilicon layer by performing a solid-phase crystallization process; And patterning the polysilicon layer.

The step of forming the etch stopper may include forming a first inorganic insulating layer by depositing silicon oxide (SiO ₂ ) on the entire surface of the polysilicon layer; Depositing silicon nitride (SiNx) on the first inorganic insulating layer to form a second inorganic insulating layer; And continuously or collectively patterning the second and first inorganic insulating layers.

The first metal layer is formed of molybdenum (Mo) or titanium (Ti), which is a metal material having excellent diffusibility, and is formed to have a thickness of about 50 Å to about 200 Å.

Wherein the step of forming the gate electrode and the gate wiring includes forming a gate pad electrode connected to one end of the gate wiring over the gate insulation film, And forming a data pad electrode connected to one end of the data line on a layer. The forming of the passivation layer may include forming a gate pad contact hole exposing the gate pad electrode. The forming of the pixel electrode may include forming a contact hole with the gate pad electrode through the gate pad contact hole, And forming a data assist pad electrode covering the data pad electrode.

The pixel electrode is formed to completely cover the drain electrode. An island-shaped auxiliary source electrode is formed on the source electrode to completely cover the source electrode with the same material having the pixel electrode formed thereon .

The polysilicon pattern preferably has a thickness of 400 ANGSTROM to 600 ANGSTROM.

(HF) dilution water having a ratio of deionized water to hydrogen fluoride (HF) of about 1000: 1 to about 600: 1 is used before the etch stopper is formed on the polysilicon pattern, or a weakened oxide etchant Buffered Oxide Etchant (BOE).

The heat treatment is performed for several minutes to several tens minutes in a temperature atmosphere of 300 ° C to 400 ° C.

As described above, according to the method of manufacturing an array substrate according to the present invention, since the active layer is not exposed to dry etching, the surface damage is not caused, and the characteristics of the thin film transistor are prevented from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness of the active layer to be etched away. Therefore, the thickness of the active layer is reduced, thereby reducing the deposition time and improving the productivity.

The array substrate manufactured by the manufacturing method according to the present invention includes a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming the thin film transistor as a semiconductor layer There is an effect of improving mobility characteristics by several tens to several hundreds of times as compared with an array substrate.

Since the active layer of polysilicon is used as a semiconductor layer of a thin film transistor, doping of impurities is not required, and thus it is not necessary to invest new equipment to proceed the doping process, which is advantageous in reducing initial investment cost

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

FIGS. 4A through 4L illustrate one pixel region P including a thin film transistor of an array substrate according to an embodiment of the present invention, a gate pad portion GPA where a gate pad electrode is formed, and data (DPA) according to the present invention. Here, for convenience of description, a portion where a thin film transistor connected to the gate and data lines in each pixel region P is to be formed is defined as a switching region TrA.

First, as shown in Figure 4a, by depositing a transparent substrate 101, an inorganic insulating material on, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx), forms a buffer layer (103). The buffer layer 103 may generate alkali ions such as potassium ion (K +), sodium ion (Na +), and the like existing in the substrate 101 due to heat applied during the progress of the crystallization process. And to prevent the semiconductor characteristics of the active layer formed thereon from deteriorating. The buffer layer 103 having such a role may be omitted.

Next, pure amorphous silicon is deposited on the buffer layer 103 to form a pure amorphous silicon layer 106. In this case, the pure amorphous silicon layer 106 is formed to have a thickness of about 800 Å to 1000 Å in consideration of etchability in the related art. However, in the embodiment of the present invention, since the active layer is not exposed to dry etching, It is preferable to have a relatively small thickness of about 600 ANGSTROM.

Next, as shown in FIG. 4B, a solid phase crystallization (SPC) process is performed to improve the mobility characteristics of the amorphous silicon layer (106 in FIG. 4A) Layer 107 to crystallize. For example, the solid-phase crystallization process is preferably an annealing crystallization or an alternating magnetic field crystallization (AMFC).

Next, as shown in FIG. 4C, the photoresist is applied to the polysilicon layer (107 in FIG. 4B) formed by the progress of the solid-phase crystallization process, exposure using an exposure mask, development of exposed photoresist, A polysilicon pattern 110 is formed in the switching region TrA by performing a mask process including a series of unit processes such as a strip. At this time, the polysilicon layer (107 in FIG. 4B) is removed in regions other than the switching region TrA.

Next, as shown in FIG. 4D, the inorganic insulating layer 113 is formed by depositing an inorganic insulating material over the polysilicon pattern 110. At this time, before the inorganic insulating layer 113 is formed, foreign substances may adhere to the surface of the polysilicon pattern 110, or may be contaminated by organic substances or the like, or a natural oxide film may be formed. Cleaning is performed to improve the interfacial property. At this time, the polysilicon surface 110 may be cleaned using diluted hydrogen fluoride (HF) water mixed with pure water and hydrogen fluoride (HF) in a ratio of about 1000: 1 to 600: 1 or using a weakened oxide etchant (BOE) Is preferably used.

On the other hand, the inorganic insulating layer 113 is preferably formed to have a bilayer structure. In this case, the lower layer 113a contacting with the polysilicon pattern 110 is formed of silicon oxide (SiO ₂ ) to have a thickness of about 50 Å to 500 Å, and the upper layer 113b located on the lower layer 113a is nitrided It is preferable to form silicon (SiNx) to have a thickness of about 50 to 500 ANGSTROM. The reason why the inorganic insulating layer 113 is formed as a double layer is that the bonding property between the silicon oxide (SiO ₂ ) and the polysilicon is superior to the bonding property between the silicon nitride (SiNx) and the polysilicon, Because the silicon nitride (SiNx) is excellent in the bonding property with the photoresist used in the patterning of the photoresist. However, the inorganic insulating layer 113 is not necessarily formed to have a bilayer structure, and may be formed to have a single layer structure of any one of silicon oxide (SiO ₂ ) and silicon nitride (SiN x).

Thereafter, a photoresist layer (not shown) is formed on the inorganic insulating layer 113 to form a photoresist layer (not shown). By patterning the photoresist layer, as shown in the figure, the polysilicon pattern 110 formed in the switching region TrA A photoresist pattern 191 is formed.

Next, as shown in FIG. 4E, by removing the inorganic insulating layer (113 in FIG. 4D) exposed to the outside of the polysilicon pattern 110, an inorganic insulating material corresponding to the central portion of the polysilicon pattern 110 Thereby forming an etch stopper 115. [ At this time, in the embodiment of the present invention, the etch stopper 115 has a bilayer structure including a lower layer 115a and an upper layer 115b, but it may have a single layer structure.

On the other hand, the formation of the etch stopper 115 allows the polysilicon pattern 110 to have a predetermined width at both ends except for the central portion thereof exposed to the outside of the etch stopper 115. Thereafter, the photoresist pattern (191 in FIG. 4D) remaining on the etch stopper 115 is stripped and removed.

Next, as shown in FIG. 4F, the substrate 101 on which the etch stopper 115 is formed is subjected to a plasma treatment in a phosphine (PH ₃ ) gas atmosphere. At this time, the portion of the polysilicon pattern 110 exposed to the outside of the etch stopper 115 by the phosphine (PH ₃ ) plasma treatment results in the implantation of phosphorus (P), forming the impurity polysilicon layer 119 do. The impurity polysilicon layer 119 is formed on the impurity polysilicon layer 119 as an active layer. The impurity polysilicon layer 119 is formed of a metal material The ohmic contact is formed, but its conductivity is reduced as compared with the conventional ohmic contact layer. Therefore, in order to increase the conductivity of the impurity polysilicon layer 119 formed as described above, a metal material diffusion process is performed as shown in FIG. 4G, thereby forming the ohmic contact layer 120 having high conductivity.

First, the etch stopper 115 and the impurity polysilicon layer (119 in FIG. 4F) of the substrate 101 subjected to the phosphine plasma treatment are formed on the top of the etch stopper 115 and the impurity polysilicon layer The diffusion metal layer 118 is formed by depositing a metal material having excellent diffusion characteristics on the entire surface, for example, molybdenum (Mo) or titanium (Ti) to have a thickness of about 50 to 200 angstroms.

Thereafter, the substrate 101 on which the diffusion metal layer 118 is formed is subjected to heat treatment for several minutes to several ten minutes (1 minute to 90 minutes) in a temperature atmosphere of 300 ° C to 400 ° C to form the diffusion metal layer 118, To diffuse into the impurity polysilicon layer (119 in FIG. 4F). Accordingly, in the impurity polysilicon layer (119 in FIG. 4F), a small amount of metal material is diffused from the diffusion metal layer 118 to improve the conductivity and form the ohmic contact layer 120 in the state where the heat treatment process is completed. The ohmic contact layer 120 formed by the above-described two steps, that is, the phosphine plasma processing step and the metal material diffusion step, has the same ohmic characteristic and the same conduction characteristic as the ohmic contact layer formed by depositing the conventional impurity- Level.

The ohmic contact layer 120 is formed through the above steps so that the polysilicon pattern 123 is formed of the polysilicon active layer 110 made of only pure polysilicon and the ohmic contact layer 120 in which the metal material is mixed . At this time, the region of the active layer 110 of the polysilicon located between the ohmic contact layers 120 is not exposed to the phosphine plasma process or the like by the etch stopper 115 formed thereon, Therefore, the manufacturing method of the array substrate according to the embodiment of the present invention is characterized in that the deterioration of the characteristics of the thin film transistor due to the surface damage of the active layer 110 can be prevented originally.

Next, as shown in FIG. 4H, the metal layer for diffusion (118 in FIG. 4G) formed on the ohmic contact layer 120 formed by the diffusion of the metal material is etched to remove the etch stopper 115 and the ohmic contact Thereby exposing the layer 120.

On the other hand, if the buffer layer 103 is not formed, only the buffer layer 103 is formed in all the regions except for the switching region TrA, or if the substrate 101 surface is exposed State.

Next, the front be as shown in 4i, the deposition of the exposed ohmic contact layer 120 and the etch stopper 115, the inorganic insulating material to the upper part, for example a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) A gate insulating film 124 is formed.

Thereafter, a metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy and chromium (Cr) is deposited on the gate insulating film 124 to form a first A gate wiring (not shown) extending in one direction is formed by patterning a metal layer (not shown), and a masking process is performed thereon. At the same time, the switching region TrA is connected to the gate wiring (not shown) The gate electrode 130 is formed. At the same time, a gate pad electrode 132 connected to one end of the gate wiring (not shown) is formed in the gate pad portion GPA.

At this time, the first metal layer (not shown) is formed by successively depositing different metal materials to form a double or multi-layered structure and patterned to form a double or multi-layer gate wiring (not shown) You may. In the drawings, gate lines (not shown) having a single layer structure, gate electrodes 130, and gate pad electrodes 132 are shown for convenience.

Next, as shown in Fig. 4j, the gate wiring (not shown) and a gate electrode 130 and the gate pad electrode 132 over the inorganic insulating material, for example, silicon oxide (SiO ₂₎ or silicon nitride (SiNx) Or a protective layer 134 is formed on the entire surface by applying an organic insulating material such as benzocyclobutene (BCB) or photo acryl.

The ohmic contact layer 120 located on both sides of the etch stopper 115 in the switching region TrA is patterned by successively patterning the protective layer 134 and the gate insulating layer 124 located thereunder. A semiconductor layer contact hole 136 is formed. At the same time, in the gate pad portion GPA, the gate pad contact hole 137 exposing the gate pad electrode 132 is formed by patterning the passivation layer 134.

Next, as shown in FIG. 4K, a metal material such as aluminum (Al), an aluminum alloy (AlNd), or the like is formed on the passivation layer 134 having the semiconductor layer contact hole 136 and the gate pad contact hole 137, ), Copper (Cu), copper alloy, chromium (Cr), molybdenum, and moly titanium (MoTi) are deposited to form a second metal layer (not shown). Then, the second metal layer (not shown) is patterned by performing a mask process to form a data line 140 which intersects the gate line (not shown) and defines the pixel region P.

At the same time, the source and drain electrodes 143 and 146 are formed in the switching region TrA in contact with the ohmic contact layer 120 through the semiconductor layer contact hole 136. At this time, the source electrode 143 and the data line 140 are formed to be connected to each other. At this time, the polysilicon pattern 123 including the active layer 110 and the ohmic contact layer 120 sequentially stacked in the switching region TrA, the etch stopper 115, the gate insulating film 124, And the source and drain electrodes 143 and 146, which are spaced from each other, constitute a thin film transistor Tr.

The data line 140 and the source and drain electrodes 143 and 146 are formed and connected to one end of the data line 140 on the protective layer 134 in the data pad unit DPA. The data pad electrode 148 is formed.

Although not shown in the drawing, when the array substrate 101 is used as an array substrate for an organic electroluminescent device, power lines (not shown) may be further formed at a predetermined interval in parallel with the data lines 140 A plurality of driving thin film transistors (not shown) having the same structure may be further formed in each pixel region P in addition to the thin film transistor Tr connected to the data line 140.

Then, a transparent conductive material such as indium-tin-oxide (ITO) or indium-tin-oxide (ITO) is formed on the data line 140, the source and drain electrodes 143 and 146, -Zinc-oxide (IZO) on the entire surface to form a layer of a transparent conductive material (not shown). Thereafter, the transparent conductive material layer (not shown) is patterned by performing a masking process to form pixel electrodes 150 in each pixel region P that are in contact with the drain electrodes 146.

At the same time, a gate auxiliary pad electrode 152 is formed in the gate pad portion GPA to contact the gate pad electrode 132 through the gate pad contact hole 137 on the protection layer 134, DPA, the data substrate pad electrode 154 is formed to cover the data pad electrode 148 to complete the array substrate 101 according to the embodiment of the present invention.

In this case, the pixel electrode 150 is formed to completely cover the drain electrode 146, but only a part of the pixel electrode 150 may be in contact with the drain electrode 146. In addition, although the source electrode 143 is exposed in the drawing, the transparent conductive material layer (not shown) may not be removed from the source electrode 143 when the pixel electrode 150 is formed, A transparent conductive pattern (not shown) that does not contact the pixel electrode 150 in an island shape with respect to the upper portion of the electrode 143 may be formed.

When a driving thin film transistor (not shown) is formed in each pixel region P, the thin film transistor Tr formed in the switching region TrA does not contact the pixel electrode 150, A drain electrode (not shown) of a driving thin film transistor (not shown) is formed to be connected to the pixel electrode 150 as shown in the drawing, and the thin film transistor Tr of the switching region TrA, The transistors (not shown) are electrically connected to each other. In the case of an array substrate in which driving thin film transistors (not shown) are formed in the pixel region P and the thin film transistor Tr connected to the gate and data lines (not shown) 140 in the switching region TrA, Thereby forming an array substrate.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device, including one pixel region including a thin film transistor. Fig.

FIGS. 2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate; FIGS.

3 is a cross-sectional view of a pixel region including the thin film transistor in an array substrate having a thin film transistor having a conventional polysilicon semiconductor layer.

FIGS. 4A to 4L are cross-sectional views illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention. Referring to FIGS. 4A to 4L, a pixel region including a thin film transistor of an array substrate, a gate pad portion, Process section.

Description of the Related Art

101: substrate 103: buffer layer

110: active layer 115: etch stopper

115a, 115b: a lower layer (of the etch stopper)

118: diffusion metal layer 120: ohmic contact layer

123: Polysilicon pattern

P: pixel region TrA: switching region

GPA: Gate pad part DPA: Data pad part

Claims (11)

Forming a polysilicon pattern in a switching region on the substrate; Forming an etch stopper corresponding to a central portion of the polysilicon pattern so that both sides of the polysilicon pattern are exposed; Performing phosphorus (PH ₃ ) plasma processing on the substrate on which the etch stopper is formed to cause phosphorus (P) to be implanted into both sides of the polysilicon pattern exposed to the outside of the etch stopper; Forming a first metal layer on the etch stopper over the entire surface of the etch stopper and performing a heat treatment so that both sides of the polysilicon pattern become ohmic contact layers having good conductivity; Removing the first metal layer; Forming a gate insulating film on the entire surface of the etch stopper; Forming a gate electrode corresponding to the etch stopper over the gate insulating film and simultaneously forming a gate wiring extending in one direction; Forming a protective layer over the gate wiring and the gate electrode, the protective layer having a semiconductor layer contact hole exposing the ohmic contact layer; Forming source and drain electrodes spaced apart from each other in contact with the ohmic contact layer through the semiconductor layer contact hole over the protective layer and forming a data line crossing the gate line and defining a pixel region over the protective layer ; Forming a pixel electrode in contact with the drain electrode for each pixel region on the source and drain electrodes, Wherein the substrate is a substrate. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1, Wherein forming the polysilicon pattern comprises: Forming a buffer layer as an inorganic insulating material on the entire surface of the substrate; Forming an amorphous silicon layer over the buffer layer; Crystallizing the amorphous silicon layer into a polysilicon layer by performing a solid-phase crystallization process; Patterning the polysilicon layer Wherein the substrate is a substrate. The method according to claim 1, Wherein forming the etch stopper comprises: Depositing silicon oxide (SiO ₂ ) over the polysilicon layer to form a first inorganic insulating layer; Depositing silicon nitride (SiNx) on the first inorganic insulating layer to form a second inorganic insulating layer; Continuously or collectively patterning the second and first inorganic insulating layers Wherein the substrate is a substrate. The method according to claim 1, Wherein the first metal layer is made of molybdenum (Mo) or titanium (Ti), which is a metal material having excellent diffusibility, and has a thickness of about 50 Å to about 200 Å. Claim 5 has been abandoned due to the setting registration fee. The method according to claim 1, Wherein forming the gate electrode and the gate wiring includes forming a gate pad electrode connected to one end of the gate wiring over the gate insulation film, Wherein forming the data line with the source and drain electrodes comprises forming a data pad electrode connected to one end of the data line over the protective layer. Claim 6 has been abandoned due to the setting registration fee. 6. The method of claim 5, Wherein forming the passivation layer includes forming a gate pad contact hole exposing the gate pad electrode, Wherein forming the pixel electrode comprises forming a gate assist pad electrode contacting the gate pad electrode through the gate pad contact hole and a data assist pad electrode covering the data pad electrode, . The method according to claim 1, Wherein the pixel electrode is formed to completely cover the drain electrode. The method according to claim 1, And an island-shaped auxiliary source electrode is formed on the source electrode to completely cover the source electrode with the same material having the pixel electrode formed thereon. The method according to claim 1, Wherein the polysilicon pattern has a thickness of 400 ANGSTROM to 600 ANGSTROM. The method according to claim 1, (HF) dilution water having a ratio of deionized water to hydrogen fluoride (HF) of about 1000: 1 to about 600: 1 is used before the etch stopper is formed on the polysilicon pattern, or a weakened oxide etchant Buffered Oxide Etchant (BOE). ≪ / RTI > The method according to claim 1, Wherein the heat treatment is performed for several minutes to several tens of minutes in a temperature atmosphere of 300 ° C to 400 ° C.

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