KR20030057655A - Method for fabricating of poly silicon Thin film transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a poly silicon TFT(Thin Film Transistor) is provided to reduce the generation of defects on the surface of a poly silicon layer by activating a catalytic metal material under the atmosphere of nitrogen. CONSTITUTION: A buffer layer(112) is formed on a substrate(100). An amorphous silicon layer is deposited on the entire surface of the buffer layer including the buffer layer. A catalytic metal material is absorbed on an upper portion of the amorphous silicon layer. A poly silicon layer(115) is forming by crystallizing the amorphous silicon layer. The poly silicon layer is stabilized by performing an activation process under the atmosphere of nitrogen. A surface of the stabilized poly silicon layer is etched by using a predetermined material such as HF.

Description

Method for fabricating polycrystalline silicon thin film transistor {Method for fabricating of poly silicon thin film transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a method for manufacturing a polycrystalline silicon thin film transistor which is a switching element of a liquid crystal display device.

Generally, in order to form a polycrystalline silicon thin film, pure amorphous silicon (intrinsic amorphous silicon) in a predetermined method, that is, plasma silicon vapor deposition (Plasma chemical vapor deposition) or LPCVD (Low pressure CVD) method of amorphous silicon with a thickness of 500 Å on the insulating substrate After the film was deposited, a method of crystallizing it was used. Crystallization methods can be classified into four categories as follows.

First, laser annealing is a method of growing polycrystalline silicon by applying a laser to a substrate on which an amorphous silicon thin film is deposited.

Second, solid phase crystallization (hereinafter referred to as SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Third, the metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

Fourth, the metal induced lateral crystallization method (MILC) is a method of forming an oxide pattern in an active region and then depositing metal to form polycrystalline silicon. Since it grows, it is a method which can improve the mobility of a carrier.

The first method, laser heat treatment, is a method of forming polycrystalline silicon, which is currently widely studied, which supplies laser energy to a substrate on which amorphous silicon is deposited to make the amorphous silicon in a molten state, and then forms polycrystalline silicon by cooling.

The second method, solid crystallization, forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then As a method of obtaining polycrystalline silicon by heat treatment at a high temperature for a long time, as described above, since the solid phase crystallization is performed for a long time at a high temperature, a desired polycrystalline silicon phase cannot be obtained, and the grain growth direction is irregular so that the polycrystalline silicon is applied to a thin film transistor. The breakdown voltage of the device is lowered due to irregular growth of the gate insulating layer to be connected to the gate, and the grain size of the polycrystalline silicon is extremely uneven, which lowers the electrical characteristics of the device and requires the use of an expensive quartz substrate. There is a problem.

The third and fourth methods, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate, but film quality reliability is more likely because metal residues are more likely to exist in the network inside the polycrystalline silicon. Although it is difficult to guarantee the MIC method, attempts are being made to apply crystallized polycrystalline silicon to switching devices of thin film transistors and liquid crystal displays by newly applying the MIC method.

Hereinafter, a conventional polycrystalline silicon forming process through a metal induced crystallization process will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views sequentially illustrating a manufacturing process of a polycrystalline silicon thin film transistor using a metal induced crystallization method.

First, as shown in FIG. 1A, one selected from a group of silicon insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited on the substrate 10 to form a buffer layer 12.

The buffer layer 12 is to prevent the elution of the alkaline substance inside the substrate 10 by the applied heat.

Subsequently, amorphous silicon (a-Si: H) is deposited on the buffer layer 12 to form an amorphous silicon layer 14.

Next, as shown in FIG. 1B, the catalyst metal 16 is adsorbed onto the surface of the amorphous silicon layer 14.

Nickel (Ni) is used as a representative catalyst metal (16), and lead (Pb) and cobalt (Co) are used.

As the method of adsorbing the catalyst metal 16, an ion shower, ion doping, sputtering, CVD, or the like may be used.

When heat is applied to amorphous silicon to which the catalytic metal 16 is adsorbed by the above-described method, a polycrystalline silicon layer 15 as shown in FIG. 1C is formed.

As shown in FIG. 1D, the polycrystalline silicon layer is patterned to form an island 8.

Next, the process illustrated in FIG. 1E is a step of forming a gate insulating film and a gate electrode. The gate insulating film 10 and the gate electrode 12, which are second insulating films, are formed on the island 8.

The island 8 may be divided into two regions, in which the first active region 14 is a pure silicon region, and the second active regions 16 and 17 are impurity regions. The second active regions 16 and 17 are located at both edges of the first active region 14.

As a result, the gate insulating layer 10 and the gate electrode 12 have a shape located on the first active region 14.

In this case, the first insulating film and the second insulating film are formed of a material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

Subsequently, p + impurity ions (eg, boron) are doped to form an ohmic contact layer on the second active regions 16 and 17.

In this case, the gate electrode 12 serves as an ion stopper to prevent the dopant from penetrating into the first active region 14.

FIG. 1F illustrates depositing and patterning a third insulating layer, an interlayer insulator 18, over the entire surface of the gate electrode 12, the second active regions 16 and 17, and the second insulating layer 10. Thus, first and second contact holes 16 'and 17' are formed in the second active regions 16 and 17.

The figure shown in FIG. 1G combines several processes.

First, the source electrode 20 and the drain electrode 22 contacting the second active regions 16 and 17, respectively, are formed through the contact holes 16 'and 17' formed in FIG. 1F.

By the process as described above, it is possible to form a p + type polycrystalline silicon thin film transistor using a conventional metal induced crystallization method.

When applied to the array substrate for a liquid crystal display device, the protective layer 26 is deposited and patterned over the entire surfaces of the electrodes 20 and 22 and the substrate 10 to expose a portion of the drain electrode 22. The contact hole 27 is formed.

A transparent conductive metal material is deposited and patterned to form a transparent pixel electrode 28 in contact with the exposed drain electrode 22.

In this manner, an array substrate for a liquid crystal display device including the polycrystalline silicon thin film transistor according to the present invention can be manufactured.

However, in the polycrystalline thin film transistor fabricated by the above-described process, residues of the catalytic metal still remain in the active region.

Residues of catalytic metal present in the active region act as defects to trap carriers.

Therefore, leakage current occurs in the thin film transistor and causes a threshold voltage.

The present invention has been proposed for the purpose of solving the above-described problems, the first method of removing the metal residue and ionic impurities by thinly etching the surface of the polycrystalline silicon layer with hydrofluoric acid (HF), and the polycrystalline silicon layer After forming a separate oxide film pattern in the defined active region, a second method of removing the catalytic metal remaining in the active region by doping ions is used.

In this case, an etching process using fluorine in the first method and a process of activating the polycrystalline silicon layer in a nitrogen (N ₂ ) atmosphere before forming the oxide film pattern in the second method are performed.

In this case, since the etching process for removing the residue of the catalyst metal is performed while the surface of the polycrystalline silicon layer is stabilized, the probability of defect generation on the surface of the crystal layer is decreased, and then the dopant is diffused during the doping process. Since it can be controlled, deterioration of the device can be prevented.

1A to 1G are cross-sectional views illustrating a conventional polycrystalline silicon thin film transistor manufacturing method according to a process sequence.

2A to 2G are cross-sectional views illustrating a method of manufacturing a polycrystalline thin film transistor in a process sequence according to a first embodiment of the present invention.

3A to 3I are cross-sectional views illustrating a method of manufacturing a polycrystalline thin film transistor in a process sequence according to a second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: transparent insulating substrate 112: buffer layer

115: polycrystalline silicon layer

According to an aspect of the present invention, there is provided a method of forming an active layer of a polycrystalline silicon thin film transistor, the method including forming a buffer layer as an insulating film on a substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer on which the catalyst metal is adsorbed into a polycrystalline silicon layer; Stabilizing the polycrystalline silicon layer by performing a process of activating the polycrystalline silicon layer at a predetermined temperature in a nitrogen atmosphere; Thinly etching the surface of the stabilized polycrystalline silicon layer by a predetermined means.

The catalyst metal is formed of one selected from the group of metals consisting of nickel (Ni), cobalt (Co), and lead (Pb).

The means for etching the surface of the silicon layer is hydrofluoric acid (HF).

A method of manufacturing a polycrystalline silicon thin film transistor according to a first aspect of the present invention includes forming a buffer layer as an insulating film on a substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer to which the catalyst metal is adsorbed into a polycrystalline silicon layer; Stabilizing the polycrystalline silicon layer by performing a process of activating the polycrystalline silicon layer at a predetermined temperature in a nitrogen atmosphere; Etching the surface of the stabilized polycrystalline silicon layer thinly by a predetermined means; Patterning the surface-etched polycrystalline silicon layer to form an active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Doping an active layer exposed to both sides of the gate electrode to form an ohmic contact layer on both sides of the active layer; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating film to form first and second contact holes on both sides of the gate electrode to expose the ohmic contact layer; And forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole.

The first and second insulating layers are formed of one of materials selected from the group consisting of a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

A method of forming an active layer of a polycrystalline silicon thin film transistor according to a second aspect of the present invention includes forming a buffer layer as an insulating film on a substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer to which the catalyst metal is adsorbed into a polycrystalline silicon layer; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the crystalline silicon layer including the oxide layer pattern and then performing a heat treatment to remove the catalytic metal present in the active region under the oxide layer pattern; Etching the exposed polycrystalline layer using the oxide layer pattern as a mask.

The doped n + ions react with silicon in the polycrystalline silicon layer to form silicide on the surface of the polycrystalline silicon layer on which the oxide layer pattern is not formed.

Activating the polycrystalline silicon layer crystallized with the catalytic metal at a predetermined temperature in a nitrogen (N ₂ ) atmosphere to stabilize the polycrystalline silicon layer.

According to an aspect of the present invention, there is provided a method of manufacturing a polycrystalline silicon thin film transistor, the method comprising: forming a buffer layer as a first insulating layer on a substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer to which the catalyst metal is adsorbed into a polycrystalline silicon layer; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the crystalline silicon layer including the oxide film pattern and then performing a heat treatment to remove the catalytic metal present in the lower portion of the oxide film pattern; Etching the exposed polycrystalline layer using the oxide film pattern as a mask; Removing the oxide layer pattern to form an island-shaped active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Forming an ohmic contact layer on both sides of the active layer by doping impurities into the active layer exposed to both sides of the gate electrode; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating film to form first and second contact holes on both sides of the gate electrode to expose the ohmic contact layer; And forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole.

Hereinafter, with reference to the accompanying drawings and embodiments will be described the present invention in detail.

First Embodiment

The first embodiment of the present invention is characterized in that the polycrystalline silicon layer crystallized using the catalytic metal is activated at a predetermined temperature in a nitrogen atmosphere.

2A to 2G are cross-sectional views illustrating a process of manufacturing a polycrystalline thin film transistor in a process sequence according to the first embodiment of the present invention.

First, as illustrated in FIG. 2A, one of a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited on the substrate 100 to form a buffer layer 112.

The buffer layer 112 is to prevent the elution of the alkali material in the substrate 100 by the applied heat.

Subsequently, amorphous silicon (a-Si: H) is deposited on the buffer layer 112 to form an amorphous silicon layer 114.

Next, as shown in FIG. 2B, the catalyst metal 116 is adsorbed onto the surface of the amorphous silicon layer 114.

Nickel (Ni) is used as a representative catalyst metal 116, and lead (Pb) and cobalt (Co) are used.

As the method of adsorbing the catalyst metal 116, an ion shower, ion doping, sputtering, CVD, or the like may be used.

By applying heat to the amorphous silicon layer to which the catalytic metal 116 is adsorbed by the above-described method, the polycrystalline silicon layer 115 as shown in FIG. 2C is formed.

Subsequently, a process of activating the polycrystalline silicon layer at a predetermined temperature in an N ₂ atmosphere is performed.

In this manner, the surface of the polycrystalline silicon layer is stabilized.

That is, a plurality of defects are present in the crystalline silicon layer in which crystallization is advanced by reaction with the catalytic metal (116 in FIG. 2B). When the process of activating them in a nitrogen (N ₂ ) atmosphere is performed, the defects are repaired. It can work.

Next, the surface of the polycrystalline silicon layer 115 is etched thinly using fluorine (HF) to remove metal residues and ionic impurities remaining on the surface of the polycrystalline silicon layer.

In this process, since the polycrystalline silicon layer is already stabilized, defects on the surface of the etching process are less likely to occur.

In addition, in the doping step performed in a subsequent step, the diffusion rate of the ions can be controlled to prevent deterioration characteristics of the device.

Next, as illustrated in FIG. 2D, the island 108 is formed by patterning the polycrystalline silicon thin film.

Next, the process illustrated in FIG. 2E is a step of forming a gate insulating film and a gate electrode to form a gate insulating film 100 and a gate electrode 112 as a second insulating film on the island 108.

The island 108 may be divided into two regions, in which the first active region 114 is a pure silicon region, and the second active regions 116 and 117 are impurity regions. The second active regions 116 and 117 are positioned at both edges of the first active region 114.

As a result, the gate insulating layer 100 and the gate electrode 112 have a shape located on the first active region 114.

In this case, the first insulating film and the second insulating film are formed of a material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

Subsequently, p + impurity ions (eg, boron) are doped to form an ohmic contact layer on the second active regions 116 and 117.

In this case, the gate electrode 112 serves as an ion stopper to prevent the dopant from penetrating into the first active region 114.

2F illustrates depositing and patterning a third insulating layer, an interlayer insulator 18, over the entire surface of the gate electrode 112, the second active regions 116 and 117, and the second insulating layer 100. Thus, first contact holes and second contact holes 116 ′ and 117 ′ are formed in the second active regions 116 and 117.

The figure shown in FIG. 2G combines several processes.

First, the source electrode 120 and the drain electrode 122 contacting the second active regions 116 and 117, respectively, are formed through the contact holes 116 ′ and 117 ′ formed in FIG. 2G.

By the process as described above, it is possible to form a p + type polycrystalline silicon thin film transistor using a conventional metal induced crystallization method.

When applied to the array substrate for a liquid crystal display device, the protective layer 126 is deposited and patterned over the entire surfaces of the electrodes 120 and 122 and the substrate 100 to expose a portion of the drain electrode 122. A contact hole 127 is formed.

In addition, a transparent conductive metal material including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited and patterned to form a pixel electrode 128 in contact with the exposed drain electrode 122. .

Through the process as described above, it is possible to manufacture a polycrystalline silicon thin film transistor according to the first embodiment of the present invention.

Hereinafter, the second embodiment describes a method of removing the residue of the catalyst metal by ion doping after activating the polycrystalline silicon layer in the nitrogen atmosphere as described above.

Second Embodiment

The second embodiment of the present invention is characterized in that the surface of the polycrystalline silicon layer crystallized using the catalyst metal is stabilized in a nitrogen atmosphere, and then the catalyst metal is removed using an ion doping method.

3A to 3I are cross-sectional views illustrating a process of manufacturing a polycrystalline thin film transistor in a process sequence according to a second embodiment of the present invention.

First, as shown in FIG. 3A, one selected from a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited and patterned on a substrate 200 to form a buffer layer 202. do.

Subsequently, amorphous silicon is deposited on the buffer layer 202 to form an amorphous silicon layer 204.

Subsequently, as shown in FIG. 3B, a small amount of catalyst metal 205 is adsorbed onto the amorphous silicon layer 204.

When heat is applied to the amorphous silicon layer 204 to which the catalyst metal 205 is adsorbed, silicide (NiSi ₂ ) is formed by reacting the adsorbed catalyst metal with silicon on the surface of the amorphous silicon layer 204. As the silicide diffuses to the lower portion of the amorphous silicon layer 204, crystallization proceeds.

Accordingly, as shown in FIG. 3C, the polycrystalline silicon layer 206 including the plurality of crystal grains 210 may be formed.

Subsequently, a process of activating the polycrystalline silicon layer at a predetermined temperature in a nitrogen (N ₂ ) atmosphere is performed to stabilize the crystal layer.

The stabilization of the crystal layer has been described above.

Next, as illustrated in FIG. 3D, an oxide film is formed on the polycrystalline silicon layer 206 and then patterned to form an oxide film pattern 212 defining the active region 208.

The active region 208 is divided into a first active region 214 serving as a channel and a second active region 216 and 217 serving as an ohmic contact layer.

Subsequently, when the heat treatment process is performed after doping n + ions on the polycrystalline silicon layer including the oxide layer pattern 212, the first active region 214 and the second active region below the oxide layer pattern 212 are performed. The catalytic metal remaining at 216 and 217 diffuses out of the oxide film and exits to react with the doped ions.

If the catalyst metal is nickel (Ni) and the doping material is phosphorus, phosphorus is reacted with NiP.

Accordingly, the reactant reacted with the residue of the catalyst metal and the doped ions is present in the polycrystalline silicon layer 206 in which the oxide layer pattern 212 is not formed.

The oxide layer pattern 212 is used as an ion stopper to prevent doping of ions (n +) in the active region.

Next, as shown in FIG. 3E, the polycrystalline layer exposed below is removed using the oxide film pattern 212 as a mask.

Subsequently, by removing the oxide layer pattern 212 using a predetermined etching means, the active region 208 patterned in an island shape can be formed.

As shown in FIG. 3F, the active region 208 is defined as a first active region 214 and a second active region 216 and 217.

Next, the process shown in FIG. 3H is a step of forming a gate insulating film and a gate electrode to form a gate insulating film 210 and a gate electrode 212 as a second insulating film on the island-shaped active layer 208. .

In the above-described configuration, the second active regions 216 and 217 are located at both edges of the first active region 214.

Accordingly, the gate insulating layer 210 and the gate electrode 212 have a shape located on the first active region 214.

In this case, the first insulating film and the second insulating film are formed of a material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

The gate electrode 212 and the gate insulating film 210 are formed in the same pattern to reduce the number of masks.

After forming the gate electrode 212, p + ions are doped to form an ohmic contact layer in the second active region. In this case, the gate electrode 212 serves as an ion stopper to prevent the dopant from penetrating into the first active region 214.

Since the doped dopant is a Group 3 element such as B ₂ H ₆ , it forms a P planar channel.

In this case, the active regions 214, 216, and 217 may be stabilized in a nitrogen atmosphere in advance to control rapid diffusion of the dopant.

Therefore, deterioration of the device can be prevented.

3H illustrates depositing and patterning a third insulating layer, an interlayer insulator 218, over the entire surface of the gate electrode 212, the second active regions 216 and 217, and the second insulating layer 210. The first contact hole and the second contact hole 216 ′ and 217 ′ are formed in the second active regions 216 and 217.

The figure shown in FIG. 3I shows a combination of various processes.

First, the source electrode 220 and the drain electrode 222 contacting the second active regions 216 and 217, respectively, are formed through the contact holes 116 ′ and 117 ′ formed in FIG. 3H.

Thereafter, the protective layer 226 is deposited and patterned over the electrodes 220 and 222 and the entire surface of the substrate to form a contact hole 227 exposing a portion of the drain electrode 222.

Subsequently, by depositing and patterning a transparent conductive metal material including indium tin oxide (ITO) and indium zinc oxide (IZO), the transparent pixel electrode 228 is in contact with the exposed drain electrode 222. Form.

In this manner, the present invention can produce an array substrate for a liquid crystal display device including the polycrystalline silicon thin film transistor according to the second embodiment.

In the method of manufacturing a polycrystalline thin film transistor according to the present invention, since the silicon layer crystallized using a catalytic metal is activated at a predetermined temperature in a nitrogen atmosphere, a process of removing metal residue by etching the surface of the crystal layer with fluorine, and During the doping process to remove metal residues, the probability of defects occurring on the surface of the polycrystalline layer can be reduced.

In addition, since the diffusion rate of the dopant may be controlled during the doping of the dopant for forming the ohmic contact layer in the active region, deterioration of the device may be prevented.

Therefore, there is an effect that can improve the operating characteristics of the polycrystalline thin film transistor.

Claims (16)

Forming a buffer layer which is an insulating film on the substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer adsorbed by the catalyst metal into a polycrystalline silicon layer Steps; Stabilizing the polycrystalline silicon layer by performing a process of activating the polycrystalline silicon layer at a predetermined temperature in a nitrogen atmosphere; And etching the surface of the stabilized polycrystalline silicon layer thinly by a predetermined means. The method of claim 1, The catalyst metal is an active layer forming method of a polycrystalline silicon thin film transistor formed of a metal group consisting of nickel (Ni), cobalt (Co), lead (Pb). The method of claim 1, And a means for etching the surface of the silicon layer is hydrofluoric acid (HF). Forming a buffer layer which is an insulating film on the substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer adsorbed by the catalyst metal into a polycrystalline silicon layer Steps; Stabilizing the polycrystalline silicon layer by performing a process of activating the polycrystalline silicon layer at a predetermined temperature in a nitrogen atmosphere; Etching the surface of the stabilized polycrystalline silicon layer thinly by a predetermined means; Patterning the surface-etched polycrystalline silicon layer to form an active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Doping an active layer exposed to both sides of the gate electrode to form an ohmic contact layer on both sides of the active layer; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating layer to form first and second contact holes on both sides of the gate electrode to expose the ohmic contact layer; Forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole Polycrystalline thin film transistor manufacturing method comprising a. The method of claim 4, wherein The catalyst metal is a polycrystalline silicon thin film transistor manufacturing method formed of a metal group consisting of nickel (Ni), cobalt (Co), lead (Pb). The method of claim 4, wherein The first and second insulating layers are a material selected from the group consisting of a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), and TEOS (Tetra Ethoxy Silane). The method of claim 4, wherein And the impurity is a P-type semiconductor. Forming a buffer layer which is an insulating film on the substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer adsorbed by the catalyst metal into a polycrystalline silicon layer Steps; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the crystalline silicon layer including the oxide layer pattern and then performing a heat treatment to remove the catalytic metal present in the active region under the oxide layer pattern; Etching the exposed polycrystalline layer using the oxide layer pattern as a mask; A method of forming an active layer of a polycrystalline silicon thin film transistor comprising. The method of claim 8, And the doped n + ions react with silicon in the polycrystalline silicon layer so that silicide is formed on a surface of the polycrystalline silicon layer on which the oxide layer pattern is not formed. The method of claim 8, A method of forming an active layer of a polycrystalline silicon thin film transistor, comprising: stabilizing a polycrystalline silicon layer by activating the polycrystalline silicon layer crystallized with the catalyst metal at a predetermined temperature in a nitrogen atmosphere. The method of claim 8, The catalyst metal is an active layer forming method of a polycrystalline silicon thin film transistor formed of a metal group consisting of nickel (Ni), cobalt (Co), lead (Pb). The method of claim 8, The buffer layer is a method of forming an active layer of a polycrystalline silicon thin film transistor deposited by one selected from the group of inorganic insulating materials including silicon nitride (SiO ₂ ) and silicon oxide (SiN _X ). Forming a buffer layer, which is a first insulating film, on the substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer adsorbed by the catalyst metal into a polycrystalline silicon layer Steps; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the crystalline silicon layer including the oxide film pattern and then performing a heat treatment to remove the catalytic metal present in the lower portion of the oxide film pattern; Etching the exposed polycrystalline layer using the oxide film pattern as a mask; Removing the oxide layer pattern to form an island-shaped active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Forming an ohmic contact layer on both sides of the active layer by doping impurities into the active layer exposed to both sides of the gate electrode; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating film to form first and second contact holes on both sides of the gate electrode to expose the ohmic contact layer; Forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole Polycrystalline thin film transistor manufacturing method comprising a. The method of claim 13, The doped n + ion and the silicon of the polycrystalline silicon layer is reacted, so that the silicide is formed on the surface of the polycrystalline silicon layer in which the oxide film pattern is not formed. The method of claim 13, Forming a polycrystalline silicon layer with the catalyst metal, and then stabilizing the polycrystalline silicon layer by activating at a predetermined temperature in a nitrogen atmosphere. The method of claim 13, And the impurity is a P-type semiconductor.