KR100470021B1 - Method for crystallizing of silicon and method for fabricating of Thin film transistor - Google Patents

Abstract

The present invention relates to a method for forming a polycrystalline thin film transistor, and more particularly, to a method for crystallizing amorphous silicon used as an active layer of a thin film transistor.

Briefly summarizing the present invention, after depositing amorphous silicon on a substrate on which a trace amount of catalytic metal is deposited, crystallization is performed by irradiating a laser beam on the amorphous silicon after the dehydrogenation process.

In this method, during the dehydrogenation process, the pre-deposited metal and silicon react to form crystal nuclei, and polycrystalline silicon is formed according to the distribution of the nuclei so that the size of the crystal grains can be coarsely distributed in a micrometer unit. It is possible to crystallize a large area in a short time.

Description

Method for crystallizing of silicon and method for fabricating of Thin film transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a manufacturing method of a polycrystalline thin film transistor which is a switching element of a liquid crystal display device.

Generally, in order to form a polycrystalline silicon thin film, pure amorphous silicon (intrinsic amorphous silicon) in a predetermined method, that is, plasma silicon vapor deposition (Plasma chemical vapor deposition) or LPCVD (Low pressure CVD) method of amorphous silicon with a thickness of 500 Å on the insulating substrate After the film was deposited, a method of crystallizing it was used. Crystallization methods can be classified into three categories as follows.

First, laser annealing is a method of growing polycrystalline silicon by applying a laser to a substrate on which an amorphous silicon thin film is deposited.

Second, solid phase crystallization (hereinafter referred to as SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Third, the metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

The first method, laser heat treatment, is a method of forming polycrystalline silicon, which is currently widely studied, which supplies laser energy to a substrate on which amorphous silicon is deposited to make the amorphous silicon in a molten state, and then forms polycrystalline silicon by cooling.

The second method, solid crystallization, forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then As a method of obtaining polycrystalline silicon by heat treatment at a high temperature for a long time, as described above, since the solid phase crystallization is performed for a long time at a high temperature, a desired polycrystalline silicon phase cannot be obtained, and the grain growth direction is irregular so that the polycrystalline silicon is applied to a thin film transistor. The breakdown voltage of the device is lowered due to the irregular growth of the gate insulating layer to be connected to the gate, and the grain size of the polycrystalline silicon is extremely uneven to degrade the electrical characteristics of the device, and an expensive quartz substrate should be used. There is a problem.

The third method, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate, but it ensures the reliability of the film because metal residues are likely to exist in the network inside the polycrystalline silicon. Although it is difficult, a new application of the MIC method is attempting to apply crystallized polycrystalline silicon to thin film transistors and switching elements of liquid crystal displays.

Hereinafter, a process of crystallizing amorphous silicon into polycrystalline silicon using a laser will be described with reference to the accompanying drawings.

1A to 1C illustrate a crystallization process using a laser beam according to a conventional process sequence.

First, as shown in FIG. 1A, a buffer layer 12 is formed by depositing one selected from a group of silicon insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on a substrate 10.

The buffer layer 12 is to prevent the elution of the alkaline substance inside the substrate 10 by the applied heat.

Subsequently, amorphous silicon (a-Si: H) is deposited on the buffer layer 12 to form an amorphous silicon layer 14.

Next, as shown in FIG. 1B, a dehydrogenation process for removing hydrogen contained in the amorphous silicon is performed by applying heat of 400 ° C. to 500 ° C. to the substrate 10 on which the amorphous silicon layer 14 is formed. .

Next, as shown in FIG. 1C, a process of crystallizing amorphous silicon into crystalline silicon 15 is performed by irradiating a laser beam onto the surface of the substrate 10 having undergone the dehydration process.

Through the process as described above, it is possible to produce polycrystalline silicon through conventional laser crystallization.

However, in the conventional polycrystalline silicon crystallization method, the process window is very narrow because two reactions, such as nucleation reaction and grain growth, are instantaneously performed by laser beam irradiation.

That is, for example, there is a problem of increasing the energy density of the laser beam or irradiating the laser beam of low energy band several times for crystallization.

In such a case, since the crystallization takes a long time, there is a problem that the yield is lowered.

In addition, since the grain size is usually very small, such as thousands of microwatts, when used as an element, the operating characteristics of the element are not stable.

This is because, if a large number of crystal grains exist in the predetermined area, there are a large number of trap states capable of trapping electrons in the crystal grains, thereby reducing the mobility of electrons.

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above problems, and defines the distribution of crystal nuclei in advance so that the distribution of crystal grains is coarse before the laser beam is irradiated.

1A to 1C are diagrams sequentially illustrating a process of crystallizing conventional amorphous silicon,

2A to 2D are views illustrating a process of crystallizing amorphous silicon in the order of the present invention,

3A to 3G are diagrams sequentially illustrating a thin film transistor manufacturing process including a polycrystalline silicon crystallization process according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100 substrate 102 buffer layer

104: amorphous silicon layer 106: catalytic metal

Polysilicon crystallization method according to the present invention for achieving the above object comprises the steps of forming a buffer layer as an insulating film on a substrate; Depositing a trace amount of catalytic metal on top of the buffer layer; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Performing a dehydrogenation process on the amorphous silicon at a predetermined temperature; And irradiating a laser beam on the surface of the amorphous silicon layer where the dehydrogenation process is completed.

The dehydrogenation process is carried out at a temperature of approximately 400 ℃ to 500 ℃.

In the dehydrogenation process, the amorphous silicon and the catalytic metal react to form crystal nuclei.

A method of manufacturing a polycrystalline silicon thin film transistor according to the present invention includes forming a buffer layer as a first insulating film on a substrate; Depositing a trace amount of catalytic metal on top of the buffer layer; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Performing a dehydrogenation process on the amorphous silicon at a predetermined temperature; Irradiating a laser beam on the surface of the amorphous silicon layer where the dehydrogenation process is completed and crystallizing the polycrystalline silicon layer; Patterning the polycrystalline silicon layer in an island shape to form an active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Forming an ohmic contact layer on both sides of the active layer by doping impurities into the active layer exposed to both sides of the gate electrode; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating film to form first and second contact holes on both sides of the gate electrode to expose the ohmic contact layer; And forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole.

Hereinafter, with reference to the accompanying drawings and embodiments will be described the present invention in detail.

Example

2A to 2E, a method of crystallizing amorphous silicon according to the present invention will be described.

First, as shown in FIG. 2A, one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited and patterned on the substrate 100, thereby forming a buffer layer on the substrate. 102).

Subsequently, a small amount of the metal catalyst 103 is adsorbed to the upper portion of the buffer layer 102 at 5 × 10 ₁₈ / cm 2 or less by a sputtering method, a CVD method, a spin coating method, or the like.

Amorphous silicon is deposited on the buffer layer 102 on which the trace amount of the catalytic metal 103 is adsorbed to form the amorphous silicon layer 104.

At this time, the adsorption of the catalytic metal 103 may be performed on the upper part after depositing the amorphous silicon, or another amorphous silicon may be deposited on the amorphous silicon to which the catalyst metal is adsorbed so as to exist inside the amorphous silicon.

Subsequently, as shown in FIG. 2B, the dehydrogenation process is performed on the amorphous silicon in the range of 400 ° C. to 500 ° C. FIG.

During the dehydrogenation process, silicide 106 is formed by reacting the metal adsorbed in the trace amount with silicon of amorphous silicon. If the catalyst metal is nickel (Ni), the reactants react with NiSi ₂ .

The silicide acts as a crystal nucleus.

Next, as shown in FIG. 2C, the surface of the amorphous silicon layer 104 having the dehydrogenation process is irradiated with a laser beam to crystallize.

When the laser beam is irradiated, amorphous silicon is melted instantaneously and crystallized while cooling.

At this time, since the nuclei are generated in advance, the laser beam irradiation can control only the grain growth reaction, so that the process window is relatively wide.

That is, since the tolerance of the optimum conditions for crystallization is large, crystallization can be achieved in a stable state, and the time for crystallization can be shortened.

The crystal grains 110 of polysilicon produced by the process as described above are very coarse to several micrometers as shown in FIG.

Hereinafter, a method of manufacturing a crystalline thin film transistor including a polycrystalline silicon thin film process according to the present invention will be described with reference to FIGS. 3A to 3G.

Referring to FIG. 3A, one selected from a group of inorganic insulating materials including silicon nitride (SiO ₂ ) and silicon oxide is deposited on a substrate 200 to form a buffer layer 202 as a first insulating layer.

The buffer layer 202 is to prevent the elution of the alkali material in the substrate 200 which may be generated in a later process.

Subsequently, the catalyst metal 204 is adsorbed at 5 * 10 ₁₈ / cm 2 by using a sputtering method, a CVD method, a spin coating method, and the like on the entire surface of the substrate 200 on which the buffer layer 202 is formed.

The catalyst metal is nickel (Ni), cobalt (Co), lead (Pb) and the like and adsorbs a very small amount.

Next, as shown in FIG. 3B, a very small amount of catalytic metal 204 deposits amorphous silicon on top of a buffer layer adsorbed with a catalyst metal of 5 * 10 ₁₈ / cm 2 or less to form an amorphous silicon layer 206. .

At this time, as in the case of the first embodiment, the catalyst metal may be adsorbed on or inside the amorphous silicon.

Subsequently, the amorphous silicon layer 206 is dehydrogenated at a temperature of approximately 400 ° C to 500 ° C.

The reason for the dehydrogenation process is to remove hydrogen contained in the amorphous silicon in advance before crystallizing the amorphous silicon layer 206, to prevent the defects in the crystal layer in advance as the hydrogen is released during the crystallization process. For that.

In addition, in the dehydrogenation process, silicon (Si) reacts with a small amount of the catalytic metal 204 adsorbed to the buffer layer 202 and the amorphous silicon layer 206 to generate crystal nuclei 205.

As shown in FIG. 3C, the polysilicon layer 208 is formed by irradiating a laser beam to the amorphous silicon having the dehydrogenation process completed and performing a crystallization process.

At this time, the crystal grains constituting the polycrystalline silicon layer is formed to a size of several ㎛ and is very coarse.

Next, as shown in FIG. 3D, the polycrystalline silicon thin film is patterned to form an island 208.

Next, the process illustrated in FIG. 3E is a step of forming a gate insulating film and a gate electrode. The gate insulating film 210 and the gate electrode 212, which are second insulating films, are formed on the island 208. The island 208 may be divided into two regions, in which the first active region 214 is a pure silicon region, and the second active regions 216 and 217 are impurity regions. The second active regions 216 and 217 are located at both edges of the first active region 214.

The gate insulating layer 210 and the gate electrode 212 are formed on the first active region 214.

In this case, the first insulating film and the second insulating film are formed of a material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

The gate electrode 212 and the gate insulating film 210 are formed in the same pattern to reduce the number of masks. After the gate electrode 212 is formed, ion doping is performed to form an ohmic contact layer in the second active region. In this case, the gate electrode 212 serves as an ion stopper to prevent the dopant from penetrating into the first active region 214. When the ion doping, the electrical characteristics of the silicon island 208 is changed according to the type of dopant, and when the dopant is doped with a group 3 element such as B ₂ H ₆ , it is a P-type semiconductor and a group 5 such as PH ₃ . When the element is doped, it acts as an N-type semiconductor. The dopant needs to be appropriately selected according to the use of the semiconductor device.

FIG. 3F illustrates depositing and patterning a third insulating layer, an interlayer insulator 218, over the entire surface of the gate electrode 212, the second active regions 216 and 217, and the second insulating layer 210. The first contact hole and the second contact hole 216 ′ and 217 ′ are formed in the second active regions 216 and 217.

The figure shown in FIG. 3G shows a combination of various processes.

First, the source electrode 220 and the drain electrode 222 contacting the second active regions 216 and 217, respectively, are formed through the contact holes 216 ′ and 217 ′ formed in FIG. 3F.

Thereafter, a protective layer 226 is deposited and patterned on the electrodes 220 and 222 and the entire surface of the substrate to form a contact hole in the protective layer 226 on the drain electrode 222.

The transparent conductive electrode is deposited and patterned to form a pixel electrode 228 in electrical contact with the drain electrode 222 through a contact hole formed in the protective layer 226 on the drain electrode 222.

In this manner, an array substrate for a liquid crystal display device including the polycrystalline silicon thin film transistor according to the present invention can be manufactured.

Silicon crystallization method according to the present invention is to enable the size of the grains to be distributed coarsely in the unit of μm, there is an effect that can improve the operating characteristics of the device.

In addition, since the crystallization process time can be shortened, there is an effect of improving the yield.

Claims (11)

Forming a buffer layer which is an insulating film on the substrate; Depositing amorphous silicon adsorbed with a trace amount of catalytic metal on the buffer layer; Performing a dehydrogenation process on the amorphous silicon at a predetermined temperature; Irradiating a laser beam on the surface of the amorphous silicon layer where the dehydrogenation process is completed to crystallize Polysilicon crystallization method comprising the step. The method of claim 1, The adsorption of the trace amount of the catalytic metal is a polysilicon crystallization method which proceeds in any one of the processes before the deposition of amorphous silicon, after the deposition of amorphous silicon or between two amorphous silicon deposition. The method of claim 1, The dehydrogenation process is a polysilicon crystallization process proceeds at a temperature of approximately 400 ℃ to 500 ℃. The method of claim 1, In the dehydrogenation process, the polysilicon crystallization method in which the amorphous silicon and the catalytic metal reacts to form crystal nuclei. Forming a buffer layer, which is a first insulating film, on the substrate; Depositing amorphous silicon adsorbed with a trace amount of catalytic metal on the buffer layer; Performing a dehydrogenation process on the amorphous silicon at a predetermined temperature; Irradiating a laser beam on the surface of the amorphous silicon layer where the dehydrogenation process is completed and crystallizing the polycrystalline silicon layer; Patterning the polycrystalline silicon layer in an island shape to form an active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Forming an ohmic contact layer on both sides of the active layer by doping impurities into the active layer exposed to both sides of the gate electrode; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating layer to form first and second contact holes on both sides of the gate electrode to expose the ohmic contact layer; Forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole Polycrystalline thin film transistor manufacturing method comprising a. The method of claim 5, wherein The adsorption of the trace amount of the catalytic metal is a polycrystalline thin film transistor manufacturing method which proceeds in any one of the processes before the deposition of amorphous silicon, after the deposition of amorphous silicon or between two amorphous silicon deposition. The method of claim 5, The first and second insulating layers are a material selected from the group consisting of a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), and TEOS (Tetra Ethoxy Silane). The method of claim 5, wherein The impurity is an N-type or P-type semiconductor manufacturing method of a polycrystalline thin film transistor. The method of claim 5, wherein The adsorbed metal is a material selected from the group consisting of nickel (Ni), lead (Pb), cobalt (Co). The method of claim 5, wherein The dehydrogenation process is a polycrystalline thin film transistor manufacturing method is carried out at a temperature of approximately 400 ℃ to 500 ℃. The method of claim 5, wherein In the dehydrogenation process, the amorphous silicon and the catalytic metal reacts to form a crystal nucleus polycrystalline thin film transistor manufacturing method.