KR100659911B1 - The method of fabricating poly crystaline silicon and the thin film transistor fabricating method of the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor having an active channel composed of a polysilicon layer.

Conventionally, an ion implantation or ion shower method is used, which requires expensive equipment to form an ohmic contact layer.

In the present invention, PSG or BSG thin film is formed on the surface of amorphous silicon by chemical vapor deposition (CVD) and irradiated with a laser to form a channel made of polysilicon and an impurity layer can be formed at the same time. In a simple process, a thin film transistor having stable electrical characteristics can be manufactured.

Description

The method of fabricating poly crystaline silicon and the thin film transistor fabricating method of the same}

1A to 1E are process cross-sectional views illustrating a manufacturing process of a liquid crystal display device using a polycrystalline silicon thin film transistor according to the prior art,

2 is a flowchart illustrating an ohmic contact layer manufacturing process of a thin film transistor according to the present invention;

3 is a graph showing the relationship between the density of the laser energy and the sheet resistance,

4 is a graph showing the change in sheet resistance according to the SiH ₄ / PH ₃ flow rate change when the thin film is PSG, and the change in sheet resistance according to the laser energy density when the thin film is BSG,

5A and 5B are graphs showing the relationship between concentration of impurities and depth of doping region according to sheet resistance and energy density.

6A and 6B are graphs showing the change of sheet resistance and average impurity concentration according to the number of laser irradiation, the doping depth according to the number of laser irradiation, and the spreading resistance value according to each depth,                 

7A to 7E are cross-sectional views illustrating a manufacturing process of a thin film transistor which is a switching element of an array substrate for a liquid crystal display device incorporating an ohmic contact layer forming method according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: substrate 154: amorphous silicon

154`: PSG (Phosposilicate glass) thin film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and more particularly, to a polycrystalline silicon TFT, which is a switching device using a channel made of polycrystalline silicon.

In general, in order to form a polycrystalline silicon thin film, pure amorphous silicon (intrinsic amorphous silicon) is a predetermined method, that is, amorphous silicon by a plasma vapor deposition (Plasma chemical vapor deposition) method or a low pressure CVD (LPCVD) method of 500Å thickness on an insulating substrate After the film was deposited, it was used to crystallize it again.

Crystallization methods can be classified into three categories as follows.                         

First, laser annealing is a method of growing polycrystalline silicon by applying a laser to a substrate on which an amorphous silicon thin film is deposited.

Second, solid phase crystallization (hereinafter referred to as SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Third, the metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

The first method, laser heat treatment, is a method of forming polycrystalline silicon, which is currently widely studied, and is a method of forming polycrystalline silicon by cooling laser energy by supplying laser energy to a substrate on which amorphous silicon is deposited.

The second method, solid crystallization, forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then As a method of obtaining polycrystalline silicon by heat treatment at high temperature for a long time, as described above, since the solid phase crystallization is performed for a long time at a high temperature, a desired polycrystalline silicon phase cannot be obtained, and the grain growth direction is irregular, so that the polycrystalline silicon is applied to a thin film transistor. The breakdown voltage of the device is lowered due to the irregular growth of the gate insulating layer to be connected to the gate, and the grain size of the polycrystalline silicon is extremely uneven to degrade the electrical characteristics of the device, and an expensive quartz substrate should be used. There is a problem.                         

The third method, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate. However, since metal residues are more likely to be present in the network inside the polycrystalline silicon, it is possible to ensure film quality reliability. However, attempts are being made to apply the MIC method newly to apply crystallized polycrystalline silicon to thin film transistors and switching elements of liquid crystal displays.

Hereinafter, a manufacturing process of a liquid crystal display using a conventional polycrystalline silicon thin film transistor will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a process of fabricating a conventional polycrystalline silicon thin film transistor.

First, the drawing illustrated in FIG. 1A is a process of continuously depositing the first insulating material 2 and the amorphous silicon 4 on the substrate 1. The first insulating film 2 is for preventing the elution of the alkali material in the substrate 1 which may be generated in a later process.

After the amorphous silicon 4 is deposited, it is crystallized by a predetermined crystallization method. The crystallization method has been described above. In the present description, a general laser crystallization method is used as an example.

Thereafter, the step of patterning the polycrystalline silicon crystallized in the process of FIG. 1A into the island 8 of the active layer is shown in FIG. 1B.

The process illustrated in FIG. 1C is a step of forming a gate insulating film and a gate electrode, forming a gate insulating film 10 and a gate electrode 12 as a second insulating layer on the island 8. The island 8 may be divided into two regions, in which the first active region 14 is a pure silicon region, and the second active regions 16 and 17 are impurity regions. The second active regions 16 and 17 are located at both edges of the first active region 14.

In addition, the gate insulating layer 10 and the gate electrode 12 are formed on the first active region 14.

The gate electrode 12 and the gate insulating film 10 are formed in the same pattern to reduce the number of masks. After the gate electrode 12 is formed, ion doping is performed to form an ohmic contact layer in the second active region.

As the ion doping method, an ion implantation method and an ion shower method may be generally used.

In this case, the gate electrode 12 serves as an ion stopper to prevent a dopant, that is, impurities from penetrating into the first active 14 region. When the ion doping, the electrical properties of the silicon island (8) is changed according to the type of dopant, and when the dopant is doped with a group III element containing boron (B), it is a P-type semiconductor, phosphorus (phosphorus) When the Group 5 element including P) is doped, it operates as an N-type semiconductor. The dopant needs to be appropriately selected according to the use of the semiconductor device. After the ion doping process, an annealing procassing is performed at a predetermined temperature as a process for activating the dopant.

FIG. 1D illustrates the deposition and patterning of an interlayer insulator 18, which is a third insulating layer, over the entire surface of the gate electrode 12, the second active regions 16 and 17, and the first insulating layer 2. In the step, source / drain contact holes 16 'and 17' are formed in the second active regions 16 and 17, respectively.

The figure shown in FIG. 1E is a combination of several processes.

First, the source electrode 20 and the drain electrode 22 contacting the second active regions 16 and 17, respectively, are formed through the contact holes 16 ′ and 17 ′ formed in FIG. 1D.

Thereafter, the protective layer 26 is deposited and patterned on the electrodes 20 and 22 and the entire surface of the substrate to form a contact hole in the protective layer 26 on the drain electrode 22.

The transparent conductive electrode is deposited and patterned to form a pixel electrode 28 in electrical contact with the drain electrode 22 through a contact hole formed in the protective layer 26 on the drain electrode 22.

In the process of forming the ohmic contact layer in the conventional process as described above, the impurity implantation method using the ion implantation or ion shower method not only requires expensive and complicated equipment, but also damages the thin film due to impurity activation and ion implantation. There is a disadvantage that a subsequent annealing process for treatment is required.

In order to reduce such process complexity, excimer laser doping using a thin film containing impurities or impurities in gas form, rather than ion implantation or ion shower method, is useful because the method is simple and can be processed at low temperature. .

In this case, the excimer laser melts the amorphous silicon thin film, and the diffusion coefficient of impurities increases with respect to the thin film in the liquid state, thereby making it easier to form the doped polycrystalline silicon thin film.

However, the use of gaseous impurities requires more complicated and sophisticated chambers and control devices. Furthermore, in this case, the surface resistance (the amount of impurities is mainly determined by the amount of impurity gas adsorbed on the thin film before and during laser irradiation). Sheet resistance and junction depth can not be precisely adjusted.

In order to solve the problems described above, in the present invention, to form the ohmic contact layer, PSG (phosphosilicate glass) and BSG (borosilicate glass) thin films each containing phosphorus (P) and boron (B) are used as doping materials. The purpose of the present invention is to propose a method of doping in low temperature laser, and to manufacture a thin film transistor having stable electrical characteristics using simple equipment.

Polycrystalline silicon forming method for achieving the above object comprises the steps of depositing amorphous silicon on a substrate; Forming a PSG (thin film containing phosphorus (P)) or BSG (thin film containing boron (B)) thin film on the surface of the amorphous silicon; Irradiating the amorphous silicon on which the PSG or BSG thin film is formed with laser to cause the phosphorus (P) or boron (B) to diffuse into the amorphous silicon to crystallize the amorphous silicon.

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The PSG film is formed by reacting a predetermined ratio of SiH ₄ and PH ₃ in an oxygen atmosphere.

The BSG film is formed by reacting SiH ₄ and B ₂ H ₆ in a predetermined ratio in an oxygen atmosphere.

According to an aspect of the present invention, a method of forming a thin film transistor includes: providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Depositing an insulating film on the gate electrode and the exposed substrate; Depositing pure amorphous silicon on the insulating film; Forming a PSG (thin film containing phosphorus (P)) or BSG (thin film containing boron (B)) thin film on the surface of the amorphous silicon; Irradiating the amorphous silicon on which the PSG or BSG thin film is formed with laser to form crystalline silicon having a surface on which phosphorus (P) or boron (B) is diffused, thereby forming an impurity semiconductor layer / pure semiconductor layer Wow; Simultaneously patterning the impurity semiconductor layer and the pure semiconductor layer to form an active layer and an ohmic contact layer formed in an island form on the gate electrode; Depositing and patterning a conductive metal material on the entire surface of the substrate on which the ohmic contact layer is formed, and forming source and drain electrodes overlapping the ohmic contact layer and spaced apart from each other. It includes.

In the above-described step, the method may further include removing the ohmic contact layer exposed between the source electrode and the drain electrode.

Hereinafter, with reference to the accompanying drawings and embodiments will be described the present invention in detail.                     

Example

An embodiment of the present invention is a PSG containing pentavalent or trivalent ions using chemical vapor deposition on amorphous silicon when forming an ohmic contact layer interposed between an active channel constituting the thin film transistor and the source and drain electrodes. Forming a thin film or BSG thin film, and proposes a doping method using the same.

Hereinafter, a method of forming a thin film transistor according to the present invention will be described with reference to FIG. 2.

First, the first step 100 _ST performs a process of thinly oxidizing the surface of a silicon substrate in an oxygen atmosphere using a silicon wafer (or transparent substrate). (In the case of a transparent substrate, a thin insulating film is formed of silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) as a buffer layer.

Next, the temperature in the chamber in which the substrate is located is 280 ° C., and hydrogenated amorphous silicon having a thickness of about 100 nm using plasma chemical vapor deposition (PECVD) or the like. -Si: H) thin film is deposited.

In the second step 200 _ST , the deposited amorphous silicon substrate is dehydrogenated for about 3 hours in a chamber at about 450 ° C.

If the dehydrogenation process is not performed, a plurality of hydrogen ions bonded to the amorphous silicon are released during the subsequent laser process, and the surface of the silicon has a plurality of defects trapping electrons.

Therefore, it is necessary to proceed with the dehydrogenation process in advance to maintain the state of the silicon surface from which hydrogen is released in a relatively stable state.

In the third step (300 _ST ), the amorphous silicon that has completed the dehydrogenation process using SiH ₄ , PH ₃ , O ₂ as a reactant using an atmospheric pressure chemical vapor deposition (APCVD) method at about 375 ° C., A thin PSG (phosphosilicate glass) film (or BSG (borosilicate glass) film) is formed on the surface of the amorphous silicon layer.

At this time, the amount of impurities (P ions) in the PSG thin film can be adjusted by the flow rate ratio of the SiH ₄ / PH ₃ in a fixed state of the oxygen flow.

In this case, in the case of the BSG film as well, the amount of impurities may be controlled by adjusting the flow rate ratio of SiH ₄ / B ₂ H ₆ .

The fourth step 400 _ST irradiates an excimer laser (lambda = 308 nm) having a pulse of about 20 ns on the PSG thin film or the BSG thin film substrate. During laser irradiation, most of the laser energy is absorbed into the a-Si thin film under the PSG (or BSG) because the PSG (or BSG) thin film above the a-Si thin film has a low absorption coefficient near the laser wavelength λ = 300 nm. This is because it has an absorption coefficient.

Therefore, the a-Si thin film is melted by laser irradiation and diffused into the a-Si thin film in which impurities in the PSG are dissolved to form a successfully doped polysilicon thin film.                     

Hereinafter, the electrical characteristics of the specimen fabricated under a number of conditions such as laser energy density, sheet resistance and doping concentration according to the number of pulses of the laser will be described with reference to the graph below.

3 is a graph showing the relationship between the density of the laser energy and the sheet resistance in the case of the PSG thin film.

At this time, when the pulse number of the laser is applied 1 pulse, 5 pulses, 10 pulses, the flow rate ratio of the SiH ₄ / PH ₃ is fixed to 0.38, the flow rate of 0 ₂ is fixed by measuring 3000sccm.

As shown, it can be seen that the sheet resistance value decreases as the density and the number of irradiation times of the laser energy increase.

The decrease in sheet resistance can be interpreted to mean that the occurrence rate of defects on the surface of the polysilicon is reduced.

Hereinafter, FIG. 4 is a graph showing the change of the sheet resistance according to the SiH ₄ / PH ₃ flow rate change in the case of the PSG thin film and the laser energy density when the thin film is BSG.

Two dotted lines 111 and 113 of the dotted lines are respectively measured for the sheet resistance of the specimen prepared by varying the flow rate change of SiH ₄ / PH ₃ . (SiH ₄ / PH ₃ = 0.19 (111), SiH ₄ / PH ₃ = 0.38 (113))

As can be seen from the graph, as a result of changing the flow rate ratio of SiH ₄ / PH ₃ , when the amount of PH ₃ was large, a result having a significantly lower sheet resistance value was obtained.

In the case of boron indicated by the solid line 115 of the graph, the higher the laser energy density, the lower the sheet resistance value.

At this time, although not _shown, the flow rate ratio of SiH ₄ / B ₂ H ₆ was about 0.32, and the difference between the experimental results and the case of SiH ₄ / PH ₃ = 0.38 (113) having a similar flow rate was slightly different. The difference in the case of the same flow rate is due to the difference in mobility between electrons and holes in the doped n-type / p-type thin film. The electron mobility is much faster.)

Therefore, the doping method proposed in the present invention can be confirmed that the doping concentration can be controlled by changing the flow rate ratio of the reaction gas SiH ₄ / PH ₃ .

In this experiment, a minimum sheet resistance of 450 Ω / cm 2 was obtained for phosphorus (P) doping, and a minimum sheet resistance value of 1100 Ω / cm 2 for boron doping, and these values were obtained from a polysilicon thin film transistor (poly-Si TFT). And a value low enough to form a drain region.

Hereinafter, the graphs of FIGS. 5A and 5B show the concentration of impurities and the doping profile of doping regions according to sheet resistance and energy density, respectively, when doping is performed according to the present invention. This is the result of the measurement. (In this case, the ion concentration uses the Hall measurement method, and the doping profile uses the spreading resistance profiling method.)

The solid line 117 of FIG. 5A shows the relationship between the energy density and the sheet resistance value, and the dotted line 119 shows the doping concentration according to the energy density.

As shown, as the energy density increased, sheet resistance decreased and the doping concentration increased.

FIG. 5B shows a laser output by changing the energy density to 250 mJ / cm 2 (solid line 121), 300 mJ / cm 2 (dotted line 123), 350 mJ / cm 2 (dotted line 125), 400 mJ / cm 2 (dotted line 127), and the depth according to each case. As a result of measuring the spreading resistance value, it can be seen that as the laser energy density increases, the diffusion depth of the same impurity increases and the impurity concentration of the surface also increases.

6A and 6B illustrate changes according to the number of laser irradiations. (At this time, the energy density is fixed at 300mJ / ㎠ and the number of irradiation is measured once, twice, five times and ten times.)

6A shows the change in sheet resistance and average impurity concentration according to the number of laser irradiation times. The solid line 129 shows the sheet resistance value according to the number of laser irradiation times, and the dotted line 131 shows the doping concentration according to the number of laser irradiation times. It is shown.

As shown, it can be seen that as the number of times of laser irradiation increases, the sheet resistance decreases and the doping concentration of the surface increases.                     

6B shows the doping depth according to the number of laser irradiation times and the spreading resistance value according to each depth. One pulse (solid line 133), two pulses (dotted line 135), five pulses (dotted line 137), and ten pulses (dotted line 139) are shown. ) Is the measured value for the case.

As illustrated, the look a little difference in doping depth and the resistance value for each depth corresponding to the pulse number, the difference can be seen that they are so large (measurement result according to the energy density of the front is about 10 ^double Although there is a difference in accuracy, the measurement result according to the number of pulses is about 10 times difference).

Therefore, a difference exists in the depth of change of the permeation depth and the surface impurity concentration of the impurity as compared with the case of FIGS. 5A and 5B. In other words, it can be concluded that the electrical properties of the doped region depend more on the change in laser energy density than on the number of laser irradiations.

Therefore, the impurity region, which is the ohmic contact layer of the thin film transistor according to the present invention, has a flow rate of SiH ₄ / PH ₃ , which is a reaction gas when doped with pentavalent phosphorus, and SiH ₄ /, which is a reaction gas when doped with trivalent boron. Depending on the flow rate, energy density, and number of irradiation times of B ₂ H _6, the doping profile and the sheet resistance, which represent the depth of doping, can be properly adjusted.

Hereinafter, a manufacturing process of a thin film transistor, which is a switching element of an array substrate for a liquid crystal display device, employing the ohmic contact layer forming method according to the present invention will be described with reference to FIGS. 7A to 7E. An example is explained.)

7A to 7E are diagrams illustrating a manufacturing process of a liquid crystal display device manufactured according to an exemplary embodiment of the present invention.                     

First, as shown in FIG. 7A, after the gate electrode 150 is formed at a predetermined position on the substrate 111, the insulating film 152 and the amorphous silicon 154 are continuously deposited to a predetermined thickness. The insulating film 152 may be a silicon nitride film (SiN _x ), TEOS (Tetra Ethoxy Silane), or the like, and preferably, a silicon oxide film (SiO ₂ ) is used.

The substrate on which the amorphous silicon is formed is placed in a chamber maintaining about 450 ° C. to proceed with dehydrogenation.

As described above, the reason why the dehydrogenation process is performed is to prevent defects occurring on the silicon surface due to sudden release of hydrogen during the laser process.

Next, PH ₃ and SiH ₄ are reacted with the substrate subjected to the dehydration process. At this time, the flow rate of 0 ₂ is kept constant.

As shown in FIG. 7B, the PSG thin film 154 ′ is formed on the surface of the amorphous silicon layer 154.

When the excimer laser is irradiated at about 300 mJ / cm 2 on the surface of the PSG thin film 154 ′, the amorphous silicon is completely melted and at this time, the impurity ions P of the PSG film are diffused. It turns into crystalline.

Next, as shown in FIG. 7C, the semiconductor layer is patterned to form a semiconductor layer 158 formed by planarly stacking an active layer 155 and an ohmic contact layer 157 on the gate electrode 150. do.                     

Next, as shown in FIG. 7D, molybdenum (Mo), tungsten (W), and chromium (Cr) are formed on the substrate on which the semiconductor layer 158 including the active layer 155 and the ohmic contact layer 157 is formed. One selected from the group of conductive metals including the same may be deposited and patterned to form a source electrode 160 and a drain electrode 162 spaced apart from the predetermined distance.

Next, a process of removing the ohmic contact layer A exposed between the two electrodes spaced apart is performed by using the source electrode 160 and the drain electrode 162 as an etch stop layer.

Next, as shown in FIG. 7E, an organic insulating material including silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and the like on the entire surface of the substrate 100 on which the source and drain electrodes 160 and 162 are formed. A group and, optionally, one selected from the group of inorganic insulating materials including benzocyclobutene, acryl resin, and the like to form a protective layer 163 and then pattern the A drain contact hole 165 is formed on the drain electrode 162.

Depositing one selected from the group of transparent conductive materials including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) on top of the patterned protective layer In addition, the pixel electrode 167 is formed in contact with the drain electrode 162 through the drain contact hole 165.

As described above, the thin film transistor according to the present invention can be configured.

Therefore, the method of forming the ohmic contact layer of the thin film transistor according to the present invention uses a simple method using an excimer laser and forms a doping film by a chemical vapor deposition method which is commonly used, and thus does not require expensive equipment for ion doping. There is an advantage to improve the yield of the product by saving.

Claims (11)

Depositing amorphous silicon on the substrate; Forming a PSG (thin film containing phosphorus (P)) or BSG (thin film containing boron (B)) thin film on the surface of the amorphous silicon; Irradiating the amorphous silicon on which the PSG or BSG thin film is formed with laser to cause the phosphorus (P) or boron (B) in the thin film to diffuse into the amorphous silicon to crystallize the amorphous silicon Polycrystalline silicon forming method comprising a. The method of claim 1, The PSG film is formed by reacting SiH ₄ and PH ₃ in an oxygen atmosphere. The method of claim 1, The BSG film is formed by reacting SiH ₄ and B ₂ H ₆ in an oxygen atmosphere. The method of claim 1, The PSG or BSG thin film is formed using a chemical vapor deposition method. The method of claim 1, The laser irradiation is an excimer laser irradiation to generate a laser in the wavelength band of 308nm. Providing a substrate; Forming a gate electrode at a predetermined position on the substrate; Depositing an insulating film on the gate electrode and the exposed substrate; Depositing pure amorphous silicon on the insulating film; Forming a PSG (thin film containing phosphorus (P)) or BSG (thin film containing boron (B)) thin film on the surface of the amorphous silicon; Irradiating the amorphous silicon on which the PSG or BSG thin film is formed with laser to form crystalline silicon having a surface on which phosphorus (P) or boron (B) is diffused, thereby forming an impurity semiconductor layer / pure semiconductor layer Wow; Simultaneously patterning the impurity semiconductor layer and the pure semiconductor layer to form an active layer and an ohmic contact layer formed in an island form on the gate electrode; Depositing and patterning a conductive metal material on the entire surface of the substrate on which the ohmic contact layer is formed, and forming source and drain electrodes overlapping the ohmic contact layer and spaced apart from each other. Thin film transistor forming method comprising a. The method of claim 6, The PSG film is a thin film transistor forming method of reacting SiH ₄ and PH ₃ in an oxygen atmosphere. The method of claim 6, The BSG film is formed by reacting SiH ₄ and B ₂ H ₆ in an oxygen atmosphere. The method of claim 6, The PSG or BSG thin film is a thin film transistor forming method formed by chemical vapor deposition. The method of claim 6, The laser irradiation is excimer laser irradiation to generate a laser in the wavelength range of 308nm thin film transistor forming method. The method of claim 6, And removing the ohmic contact layer exposed between the source electrode and the drain electrode.

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