KR101050284B1 - Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon liquid crystal display device, and to a polycrystalline silicon thin film transistor having good characteristics and a manufacturing method thereof.

A polycrystalline silicon thin film transistor according to the present invention includes a buffer layer formed on a substrate; An active layer formed on the buffer layer by being etched first and second to be stepped; A gate insulating film formed on the active layer; A gate electrode formed on the gate insulating layer to correspond to the active layer; An interlayer insulating layer formed on the gate electrode including a contact hole; And a source electrode and a drain electrode formed on the interlayer insulating layer and connected to the active layer through the contact hole.

Accordingly, the present invention improves the characteristics and reliability of the device by forming a step in forming an active layer in a polycrystalline silicon thin film transistor, thereby preventing a step coverage defect due to an under cut.

Step, active layer, undercut, step coverage

Description

Polysilicon thin film transistor and the fabrication method

1A-1D are flow charts illustrating a portion of a method of manufacturing a polycrystalline silicon thin film transistor according to the present invention.

2 is a plan view schematically showing a pixel of an array substrate for a polycrystalline silicon liquid crystal display device according to the present invention;

3 is a cross-sectional view taken along line II ′ of FIG. 2 and schematically illustrates a portion of a pixel region of an array substrate having a polycrystalline silicon thin film transistor according to the present invention;

4A to 4I are flowcharts showing a method of manufacturing a polycrystalline silicon thin film transistor according to the present invention.

Description of the Related Art [0002]

200: substrate 211: gate wiring

212: data line 214: buffer layer

216 active layer 220 gate electrode

222a and 222b: first and second active layer contact holes

224: interlayer insulating film 226, 228: source and drain electrodes                 

230: drain contact hole 232: protective layer

234 pixel electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon liquid crystal display device, and to a polycrystalline silicon thin film transistor having good characteristics and a manufacturing method thereof.

Recently, a liquid crystal display device has been spotlighted as a next generation advanced display device having low power consumption, good portability, technology intensiveness, and high added value.

The liquid crystal display injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner is attracting the most attention due to its excellent resolution and ability to implement video.

Hydrogenated amorphous silicon (H) (hereinafter abbreviated as amorphous silicon (a-Si)) is mainly used as the thin film transistor device because a low-temperature process is possible and a low-cost insulating substrate can be used. .

However, because hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist. When used, stability is a problem. In particular, amorphous silicon has a problem of deterioration in characteristics due to light irradiation, and is difficult to use in driving circuits due to electrical characteristics (low field effect mobility: 0.1 to 1.0 cm 2 / V · s) and reliability deterioration of display pixel driving elements.

However, since polycrystalline silicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. If the driving circuit is directly made on the substrate, the IC cost can be reduced and the mounting can be simplified.

1A to 1D are flowcharts illustrating a part of a method of manufacturing a polycrystalline silicon thin film transistor according to the present invention.

As shown in FIG. 1A, a buffer layer 102 is formed on an insulating substrate 100 by plasma CVD, and an amorphous silicon (a-Si) layer is deposited on the buffer layer 102 by plasma CVD. As a result, the polycrystalline silicon layer 110a is formed.

Here, the buffer layer 102 is an insulating material such as silicon oxide film (SiOx) or silicon nitride film (SiNx).

In addition, the buffer layer 102 is formed to prevent the elution of the alkali material in the insulating substrate 100, which may be generated in a later process.

A photoresist pattern 190 for forming the active layer 110 is formed on the polycrystalline silicon layer 110a.

The polysilicon layer 110a is etched by etching the photoresist pattern 190 as a mask.

In this case, as illustrated in FIG. 1B, a portion of the buffer layer 102 may be etched by performing over etch when the polycrystalline silicon layer 110a is etched.

This is to prevent a short due to the remaining film of the polycrystalline silicon layer 110a.

Subsequently, as shown in FIG. 1C, after the polycrystalline silicon layer 110a is etched to form the active layer 110, hydrofluoric acid (HF) is removed to remove the residual film and improve device characteristics on the buffer layer 110. Perform cleaning.

In this case, there is a problem that the under-cut (A) occurs due to the excessive etching occurs under the active layer 110.

As illustrated in FIG. 1D, the gate insulating layer 120 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the active layer 110 by a chemical vapor deposition (CVD) method.

In this case, the gate insulation layer 120 may have a problem in that step coverage is worsened in the stepped portion B of the active layer 110 due to the undercut A. FIG.

This step coverage problem causes poor heat dissipation in the active layer, thereby degrading device characteristics, and causing breakage or cracking of the undercut portion due to external impact, thereby causing product defects. have.

SUMMARY OF THE INVENTION An object of the present invention is to provide a polycrystalline silicon thin film transistor having a good device characteristic and preventing step coverage defect due to undercut by forming a step when forming an active layer in a polycrystalline silicon thin film transistor, and a method of manufacturing the same.

In order to achieve the above object, a polycrystalline silicon thin film transistor according to the present invention comprises a buffer layer formed on a substrate; An active layer formed on the buffer layer by being etched first and second to be stepped; A gate insulating film formed on the active layer; A gate electrode formed on the gate insulating layer to correspond to the active layer; An interlayer insulating layer formed on the gate electrode including a contact hole; And a source electrode and a drain electrode formed on the interlayer insulating layer and connected to the active layer through the contact hole.

The active layer may include source and drain impurity regions in which impurities are injected to both sides of the gate electrode.

In addition, a method of manufacturing a polycrystalline silicon thin film transistor according to the present invention for achieving the above object comprises the steps of forming a buffer layer on a substrate; Forming and crystallizing amorphous silicon on the buffer layer to form a polycrystalline silicon layer; Forming a photoresist pattern on the polycrystalline silicon layer; First etching the polycrystalline silicon layer using the photoresist pattern as a mask; Ashing the photoresist pattern; Forming a stepped active layer by secondary etching the polycrystalline silicon layer using the ashed photoresist pattern as a mask; Forming a gate insulating film on the active layer; Forming a gate electrode on the gate insulating film; Forming a source / drain impurity region by doping the active layer with the gate electrode as a mask; And depositing an interlayer insulating film having contact holes formed over the entire substrate and forming a source electrode and a drain electrode connected to the active layer thereon.

In the first etching of the polycrystalline silicon layer, the buffer layer is over-etched.

In the forming of the stepped active layer by secondary etching the polycrystalline silicon layer, the polycrystalline silicon layer may be under etched.

The method may further include performing fluorine cleaning on the active layer before forming the gate insulating layer on the active layer.

Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a plan view schematically illustrating a pixel of an array substrate for a polycrystalline silicon liquid crystal display according to the present invention.

As shown in FIG. 2, a plurality of gate lines 211 arranged in parallel on the transparent substrate and a plurality of parallel data lines 212 orthogonal to each other form a matrix and define a pixel area. The thin film transistor including the active layer 216, the gate electrode 220, the source electrode and the drain electrodes 226 and 228 is positioned at the intersection of the two wires, and the pixel electrode 234 electrically connected to the thin film transistor is positioned. do.

In this case, the active layer 216 is electrically connected to the source and drain electrodes 226 and 228 by the first and second active layer contact holes 222a and 222b, and is drained by the drain contact hole 230. The electrode 228 and the pixel electrode 234 are electrically connected to each other.

The active layer 216 is made of polycrystalline silicon (p-si) that is coated on a substrate with amorphous silicon (a-si) and then polycrystallized by laser annealing or the like.

3 is a cross-sectional view taken along line II ′ of FIG. 2 and schematically illustrates a portion of a pixel region of an array substrate having a polycrystalline silicon thin film transistor according to the present invention.

As shown in FIG. 3, when the cross section is taken along the line II ′ of FIG. 1, a buffer layer 214 is formed over the entire surface of the insulating substrate 200, and an active layer 216 is formed over the buffer layer 214. ) Is formed.

At this time, a portion of the buffer layer 214 except the lower portion of the active layer 216 is etched to form a step with the active layer 216, and the active layer 216 is further etched to form a step. That is, the buffer layer 214 has a protrusion protruding upward, and has the stepped portion and the active layer 216 is disposed on the protrusion.

As described above, the gate insulating layer 224 is formed on the active layer 216 forming the step, and the gate electrode 220 is formed on the gate insulating layer 224.

Subsequently, an interlayer insulating layer 224 including the first and second active layer contact holes 222a and 222b is formed on the active layer 216 and the gate electrode 220. The source and drain electrodes 226 and 228 respectively connected to the first and second active layer contact holes 222a and 222b are formed to be spaced apart from each other by a predetermined interval.

The protective layer 232 including the drain contact hole 230 is formed on the source and drain electrodes 226 and 228, and the drain contact hole 230 is formed on the protective layer 232. The pixel electrode 234 is formed in connection with the drain electrode 228.

A method of manufacturing the polycrystalline silicon thin film transistor configured as described above will be described in detail.

4A to 4I are flowcharts illustrating a method of manufacturing a polycrystalline silicon thin film transistor according to the present invention.

First, as shown in FIG. 4A, a buffer layer 214 is formed on the transparent substrate 200 by plasma CVD, and an amorphous silicon (a-Si) layer is deposited on the buffer layer 214 by plasma CVD. Crystallization to form the polycrystalline silicon layer 216a.

Here, the buffer layer 214 is an insulating material such as silicon oxide film (SiOx) or silicon nitride film (SiNx).

In addition, the buffer layer 214 is formed to prevent the elution of the alkali material in the insulating substrate 200, which may be generated in a later process.                     

The polycrystalline silicon layer 216a deposits the amorphous silicon layer, undergoes dehydrogenation, and forms crystalline silicon such as polycrystalline or monocrystalline silicon through a laser crystallization step using an excimer laser, and the like. Silicon is used to form the polycrystalline silicon layer 216a.

Thereafter, a photoresist pattern 290 for forming the active layer 216 is formed on the polycrystalline silicon layer 216a.

The polycrystalline silicon layer 216a is etched by using the photoresist pattern 290 as a mask.

In this case, as shown in FIG. 4B, a first active layer etching process is performed on the polycrystalline silicon 216a. That is, the buffer layer 214 is formed with a protrusion protruding upward.

Overetching of the polycrystalline silicon layer 216a is performed to etch a portion of the buffer layer.

This is to prevent a short due to the remaining film of the polycrystalline silicon layer 216a.

Subsequently, the polycrystalline silicon layer 216a is etched to form an active layer 216, and then hydrofluoric acid (HF) cleaning is performed to remove residual films on the buffer layer 214 and improve device characteristics. .

Thereafter, an ashing process is performed on the photoresist pattern 290, as shown in FIG. 4C.

The ashing process may be performed using a dry etching chamber or asher equipment.

Accordingly, a portion of the photoresist pattern 290 formed on the active layer 216 is removed by the ashing process to expose a portion of the active layer 216.

Subsequently, as illustrated in FIG. 4D, a second active layer etching process of etching the exposed active layer 216 is performed. In this case, the active layer 216 is disposed on the protrusion and has a step with the protrusion.

The exposed active layer 216 may be removed or partially under-etched in the second active layer etching process to form a step C in the active layer 216.

As such, the active layer 216 may be formed by a step formed by over etching by the first active layer etching process and a step formed by etching or under etching by the second active layer etching process. ) Will be formed stepped.

Thereafter, as shown in FIG. 4E, a gate insulating layer 224 is formed on the active layer 216.

 The gate insulating layer 224 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) by a chemical vapor deposition (CVD) method.

As shown in FIG. 4F, a metal film is formed on the gate insulating film 224.

Here, the metal film is formed by sputtering a conductive metal film such as aluminum (Al), aluminum alloy (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), or the like.

Subsequently, the metal layer is selectively removed using a photo process and an etching process to form a gate electrode 220 on the gate insulating layer 224 on the active layer 216.

By using the gate electrode 220 as a mask, low concentration n-type or p-type impurity ions are selectively implanted into the entire surface of the insulating substrate 200 to form a surface of the active layer 216 on both sides of the gate electrode 220. LDD regions (not shown) are formed.

Although not shown, after the photoresist is applied onto the insulating substrate 200 including the gate electrode 220, the photoresist is patterned by an exposure and development process.

Here, the patterned photoresist remains only on the top and side surfaces of the gate electrode 220.

Subsequently, a high concentration of n-type or p-type impurity ions are selectively implanted into the entire surface of the insulating substrate 200 by using the photoresist as a mask, so that source / drain impurity regions (not shown) are formed in the surface of the active layer 216. To form.

Thereafter, as illustrated in FIG. 4G, an interlayer insulating layer 224 including first and second active layer contact holes 222a and 222b is formed on the gate electrode 220.

As shown in FIG. 4H, the source and drain electrodes 226 are connected to the first and second active layer contact holes 222a and 222b, respectively, and overlap each other with the gate electrode 220 at a predetermined interval. 228 are formed spaced apart from each other.

Thereafter, as shown in FIG. 4I, a passivation layer 232 including a drain contact hole 230 is formed on the source and drain electrodes 226 and 228, and the passivation layer 232 is formed on the passivation layer 232. The pixel electrode 234 is formed by being connected to the drain electrode 228 through the drain contact hole 230.

Although the present invention has been described in detail through specific embodiments, it is intended to describe the present invention in detail, and the polycrystalline silicon thin film transistor according to the present invention and a method of manufacturing the same are not limited thereto, and the technical scope of the present invention is well known in the art. It is apparent that modifications and improvements are possible by those skilled in the art.

The present invention has the effect of improving the characteristics and reliability of the device by forming a step when forming the active layer in the polycrystalline silicon thin film transistor to prevent a step coverage defect due to under cut (under cut).

Claims (6)

A buffer layer formed on the substrate and having a protrusion protruding upward; An active layer disposed on the protrusion of the buffer layer and formed to be stepped with the protrusion; A gate insulating film formed on the active layer; A gate electrode formed on the gate insulating layer to correspond to the active layer; An interlayer insulating layer formed on the gate electrode including a contact hole; And a source electrode and a drain electrode formed on the interlayer insulating layer and connected to the active layer through the contact hole. The method of claim 1, The active layer is a polycrystalline silicon thin film transistor, characterized in that the source, drain impurity regions in which impurities are injected to both sides of the gate electrode. Forming a buffer layer on the substrate; Forming and crystallizing amorphous silicon on the buffer layer to form a polycrystalline silicon layer; Forming a photoresist pattern on the polycrystalline silicon layer; First etching the polycrystalline silicon layer using the photoresist pattern as a mask to form protrusions in the buffer layer; Ashing the photoresist pattern; Second etching the polycrystalline silicon layer using the ashed photoresist pattern as a mask to form an active layer having a step with the protrusion; Forming a gate insulating film on the active layer; Forming a gate electrode on the gate insulating film; Forming a source / drain impurity region by doping the active layer with the gate electrode as a mask; And Stacking an interlayer insulating film having contact holes formed over the substrate and forming a source electrode and a drain electrode connected to the active layer thereon; The method of claim 3, In the first etching of the polycrystalline silicon layer, And the buffer layer is over etched. The method of claim 3, Forming a stepped active layer by secondary etching the polycrystalline silicon layer; And the polycrystalline silicon layer is under etched. The method of claim 3, Before forming a gate insulating film on the active layer, And performing a fluorine cleaning on the active layer.

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