KR101518851B1 - Method of fabricating array substrate - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device, comprising: forming a pixel region, a first metal layer, a first inorganic insulating layer, and a pure amorphous silicon layer on a substrate on which a switching region is defined; Crystallizing the pure amorphous silicon layer into a pure polysilicon layer by performing a solid phase crystallization process; Forming a gate electrode, a gate insulating film, and an active layer of pure polysilicon sequentially on the switching region by patterning the pure polysilicon layer, the first inorganic insulating layer, and the first metal layer, Forming a gate wiring connected to the electrode and extending in one direction; Depositing and patterning an inorganic insulating material on the active layer and the gate wiring over the entire surface to form an interlayer insulating film having an active contact hole exposing and spacing the active layer and covering the gate wiring; An ohmic contact layer of an impurity amorphous silicon which is in contact with the active layer and is spaced apart from each other through the active contact hole on the interlayer insulating film; source and drain electrodes spaced apart from each other on the ohmic contact layer; Forming a data line connected to the source electrode and intersecting the gate line to define the pixel region; And forming pixel electrodes in the pixel region directly on the interlayer insulating film in contact with one end of the drain electrode.

Array substrate, polysilicon, active layer, surface damage, dry etching, crystallization, 4 mask

Description

[0001] The present invention relates to a method of fabricating array substrate,

The present invention relates to an array substrate, and more particularly, to a method of manufacturing an array substrate including a thin film transistor having an active layer which originally suppresses the surface damage of the active layer due to dry etching progress and has excellent mobility characteristics.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix type liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling on / off of a voltage for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

An array substrate having a thin film transistor, which is essentially a switching element, is provided in order to commonly turn on and off each pixel region in the liquid crystal display device and the organic electroluminescent device.

FIG. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device including a pixel region including a thin film transistor.

A gate electrode 15 is formed in a switching region TrA in a plurality of pixel regions P in which a plurality of gate wirings (not shown) and a data wiring 33 are defined in the array substrate 11, And a gate insulating film 18 is formed on the entire surface of the gate electrode 15. An active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon A semiconductor layer 28 is formed. A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method and the characteristic difference of the thin film transistor Tr occurs due to the difference in thickness (t1? T2) of the active layer 22 have.

2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate. In the figure, the gate electrode and the gate insulating film are omitted for convenience of explanation.

First, as shown in FIG. 2A, a pure amorphous silicon layer 20 is formed on a substrate 11, and an impurity amorphous silicon layer 24 and a metal layer 30 are sequentially formed thereon. Thereafter, a photoresist layer is formed on the metal layer 30 to form a photoresist layer (not shown), exposing the photoresist layer using an exposure mask, and successively developing the photoresist layer, thereby forming a third And a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed corresponding to the spacing region between the source and drain electrodes .

Next, as shown in FIG. 2B, the metal layer (30 in FIG. 2A) exposed at the outside of the first and second photoresist patterns 91 and 92 and the impurities and the pure amorphous silicon layer 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top and an impurity amorphous silicon pattern 25 and an active layer 22 as a bottom portion.

Next, as shown in FIG. 2C, the second photoresist pattern (92 in FIG. 2B) of the fourth thickness is removed by performing ashing. In this case, the first photoresist pattern (91 of FIG. 2B) having the third thickness becomes a third photoresist pattern 93 in a reduced thickness and remains on the source drain pattern 31.

Next, as shown in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching away the source drain pattern (31 in FIG. 2C) exposed to the outside of the third photoresist pattern 93, . At this time, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, dry etching is performed on the impurity amorphous silicon pattern (25 in FIG. 2D) exposed in the spacing region between the source and drain electrodes 36 and 38, The ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38.

At this time, the dry etching is performed for a sufficiently long time to completely eliminate the impurity amorphous silicon pattern (25 in FIG. 2D) exposed to the outside of the source and drain electrodes 36 and 38. In this process, the impurity amorphous silicon pattern A portion of the impurity amorphous silicon pattern (25 in FIG. 2D) is etched to a predetermined thickness even to the active layer 22 located at the lower portion of the impurity-amorphous silicon pattern 25 (FIG. 2D). Therefore, in the active layer 22, there is a difference in thickness (t1? T2) between the portion where the ohmic contact layer 26 is formed on the active layer 22 and the portion where the ohmic contact layer 26 is formed. If the dry etching is not performed for a sufficiently long time, the impurity amorphous silicon pattern (25 in FIG. 2D) to be removed in the spacing region between the source and drain electrodes 36 and 38 remains on the active layer 22 This is to prevent this.

Therefore, in the above-described conventional method of manufacturing the array substrate 11, inevitably, the thickness of the active layer 22 is different, and the characteristics of the thin film transistor (Tr in FIG. 1) deteriorates.

2A) which is thick enough to form the active layer 22 in consideration of the thickness at which the active layer 22 is etched away during the dry etching for forming the ohmic contact layer 26, The deposition must be sufficiently thick that the deposition time is increased and the productivity is lowered.

The most important constituent elements of the array substrate include a thin film transistor formed for each pixel region and connected to a gate line, a data line and a pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode .

However, in the case of a thin film transistor generally constituted in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using such an amorphous silicon, the amorphous silicon is disordered in its atomic arrangement. Therefore, the amorphous silicon changes to a metastable state upon irradiation with light or an electric field, which is a problem in stability when used as a thin film transistor device. The carrier mobility is as low as 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a device for a driving circuit.

In order to solve such a problem, a method of manufacturing a thin film transistor using polysilicon as an active layer by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by progressing a crystallization process using a laser device has been proposed.

3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate including a thin film transistor having a conventional polysilicon as a semiconductor layer, polysilicon is formed on the semiconductor layer Region 55b or a p + region (not shown) containing a high concentration of impurities is formed in the semiconductor layer 55 made of polysilicon, in order to manufacture the array substrate 51 including the thin film transistor Tr used as the p- need. Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the progress of the doping process. In this case, the manufacturing cost is increased, and a problem arises that a manufacturing line must be newly constructed for manufacturing the array substrate 51 by adding new equipment. In addition, since the mask process must be performed in the doping process, the number of mask processes must be increased to perform at least 7 mask processes. Therefore, the manufacturing time of the array substrate is prolonged and the manufacturing cost is increased again by the addition of the mask process .

It is a first object of the present invention to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching and the surface of the active layer is not damaged to improve the characteristics of the thin film transistor. do.

A second object of the present invention is to provide a manufacturing method of an array substrate which can reduce the manufacturing cost by shortening the number of times of the mask process and the manufacturing time because the active layer is formed of polysilicon and does not require a doping process. A third object of the present invention is to provide a method of manufacturing an array substrate including a thin film transistor capable of improving the mobility characteristics by forming an active layer of polysilicon.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, including forming a pixel region, a first metal layer, a first inorganic insulating layer, and a pure amorphous silicon layer on a substrate on which a switching region is defined, ; Crystallizing the pure amorphous silicon layer into a pure polysilicon layer by performing a solid phase crystallization process; Forming a gate electrode, a gate insulating film, and an active layer of pure polysilicon sequentially on the switching region by patterning the pure polysilicon layer, the first inorganic insulating layer, and the first metal layer, Forming a gate wiring connected to the electrode and extending in one direction; Depositing and patterning an inorganic insulating material on the active layer and the gate wiring over the entire surface to form an interlayer insulating film having an active contact hole exposing and spacing the active layer and covering the gate wiring; An ohmic contact layer of an impurity amorphous silicon which is in contact with the active layer and is spaced apart from each other through the active contact hole on the interlayer insulating film; source and drain electrodes spaced apart from each other on the ohmic contact layer; Forming a data line connected to the source electrode and intersecting the gate line to define the pixel region; And forming a pixel electrode on the interlayer insulating film in the pixel region, the pixel electrode being in direct contact with one end of the drain electrode.

The forming of the gate wiring may include forming a gate pad electrode connected to the first storage electrode and one end of the gate wiring on the substrate in the pixel region and a data link pattern contacting the one end of the data wiring, And forming a data pad electrode connected to the data link pattern.

The step of forming the interlayer insulating layer may include forming a gate pad contact hole exposing the gate pad electrode, a data link contact hole exposing the data link pattern, and a data pad contact hole exposing the data pad electrode Wherein the step of forming the pixel electrode comprises: a gate assist pad electrode contacting the gate pad electrode through the gate pad contact hole; and a data assist pad contacting the data pad electrode through the data pad contact hole. Forming an electrode, and forming a second storage electrode overlapping the first storage electrode to form a storage capacitor.

In addition, a gate electrode, a gate insulating film and an active layer of pure polysilicon, which are sequentially stacked as an island in the switching region, and the gate wiring, the first storage electrode, the gate and the data pad electrode And forming the data link pattern includes forming a first photoresist pattern having a first thickness corresponding to the switching region on the pure polysilicon layer, Forming a second photoresist pattern having a second thickness that is less than the first thickness corresponding to a portion of the data pad electrode and the portion where the data link pattern is formed; The pure second polysilicon layer exposed outside the first and second photoresist patterns and the second inorganic insulating layer and the first metal layer below the first and second photoresist patterns are sequentially removed to sequentially form the gate electrode and the gate insulating film And an active layer of pure polysilicon are formed on the gate insulating film, and the gate wiring, the first storage electrode, the gate and the data pad electrode, and the data link pattern are formed at the border of the pixel region, Forming an inorganic insulating pattern and a pure polysilicon pattern on the first storage electrode, the gate and data pad electrode, and the data link pattern, respectively; Exposing the gate electrode, the first storage electrode, the gate electrode, the data pad electrode, and the pure polysilicon pattern located in the upper portion of the data link pattern, respectively, by ashing and removing the second photoresist pattern; Removing the inorganic polysilicon pattern and the inorganic insulating pattern below the pattern; And removing the first photoresist pattern.

The forming of the gate interconnection may include forming a first storage electrode in the pixel region and a gate pad electrode connected to one end of the gate interconnection, Wherein forming the data line comprises forming a data pad electrode connected to one end of the data line, wherein forming the pixel electrode comprises forming a gate pad contact hole in the gate A gate auxiliary pad electrode contacting the gate pad electrode through a pad contact hole, a data auxiliary pad electrode covering the data pad electrode, and a second storage electrode overlapping the first storage electrode and connected to the pixel electrode .

The solid-phase crystallization process is characterized by crystallization through heat treatment or alternating magnetic field crystallization using an alternating magnetic field crystallization (AMFC) device.

The active layer of the pure polysilicon is formed to have a thickness of about 400 Å to about 600 Å.

According to the method of manufacturing an array substrate according to the present invention, since the active layer is not exposed to dry etching, its surface damage is not caused and the characteristics of the thin film transistor are prevented from deteriorating.

Since the active layer is not affected by the dry etching, it is not necessary to consider the thickness of the active layer to be etched away. Thus, the thickness of the active layer is reduced to shorten the deposition time and improve the productivity.

The array substrate manufactured by the manufacturing method according to the present invention is characterized in that a pure amorphous silicon layer is crystallized into a pure polysilicon layer by a crystallization process and the thin film transistor is constituted as an active layer to form a thin film transistor including a semiconductor layer of an amorphous silicon layer There is an effect of improving mobility characteristics by several tens to several hundreds of times.

Since polysilicon is used as an active layer of a thin film transistor, doping of the impurity is not required. Therefore, it is not necessary to carry out a separate mask process and new equipment investment for the progress of the doping process, thereby reducing the manufacturing cost including the initial investment cost. There are advantages to be able to.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

FIGS. 4A to 4J are cross-sectional views illustrating a pixel region including a thin film transistor and a storage capacitor of an array substrate according to an exemplary embodiment of the present invention. Referring to FIGS. 5A to 5J, FIGS. 6A to 6J are cross-sectional views illustrating a data pad portion and a data line portion of a data line portion of an array substrate according to an exemplary embodiment of the present invention. Referring to FIG. Here, for convenience of explanation, a portion where the thin film transistor Tr connected to the gate and the data wiring in each pixel region P is to be formed is referred to as a switching region TrA, and a portion where the storage capacitor is formed is referred to as a storage region StgA define.

4A, 5A, and 6A, a first metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, a titanium ) And a titanium alloy (MoTi) to form a first metal layer 103 of a single layer, a double layer or a triple layer structure. The thickness of the first metal layer 103 may be about 1000 Å to about 5000 Å. When the first metal layer 103 has a double layer structure (not shown), it may be made of an aluminum alloy (AlNd) / molybdenum (Mo). In the case of a triple layer structure (not shown), molybdenum (Mo) / Aluminum (Al) / molybdenum (Mo), molybdenum (Mo) / aluminum alloy (AlNd) / molybdenum (Mo), titanium (Ti) / copper (Cu) / titanium (Ti), titanium alloy (MoTi) Cu) / titanium alloy (MoTi), molybdenum (Mo) / copper (Cu) / molybdenum (Mo)

The reason why the first metal layer 103 is formed so as to have a double or triple layer structure other than the single layer is that the deformation due to high temperature is minimized during the crystallization process of the pure amorphous silicon layer 112 to be formed thereafter, (Al), an aluminum alloy (AlNd), a copper (Cu), and a copper alloy, and thereby minimize the resistance per unit area of the gate wiring (not shown). Titanium (Ti), titanium alloy (Ti), and molybdenum (Mo) have relatively high melting points and hardly cause deformation even at a high temperature of 600 to 700 ° C. Therefore, Even when exposed to an atmosphere at a high temperature of 600 ° C to 700 ° C for crystallization, a portion made of a metal material having low resistance characteristics such as aluminum (Al) can be prevented from being deformed. However, the first metal layer 103 is not necessarily formed as a double layer or a triple layer structure, and even if a single layer structure is formed, the first metal layer 103 is finally patterned. In the drawing, the first metal layer 103 having a single-layer structure is illustrated as an example.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the first metal layer 103 to form a first inorganic insulating layer 108. At this time, it is preferable that the first inorganic insulating layer 108 has a thickness of about 500 Å to 4000 Å.

Thereafter, pure amorphous silicon is deposited on the first inorganic insulating layer 108 continuously to form a pure amorphous silicon layer 112 having a thickness of about 400 Å to about 600 Å.

In this case, the formation of the first inorganic insulating layer 108 and the pure amorphous silicon layer 112 can be performed by the chemical vapor deposition (CVD) apparatus (not shown) through a chemical vapor deposition (Not shown) of the reactor (not shown). In this case, the pure amorphous silicon layer 112 is formed to a thickness of about 800 Å to 1000 Å in consideration of the fact that the pure amorphous silicon layer 112 is etched by being exposed to dry etching in the related art to remove a part of its thickness from its surface. However, Since the active layer of polysilicon (115 of FIG. 4J) ultimately realized through the pure amorphous silicon layer 112 is not exposed to the dry etching, the pure amorphous silicon layer 112 is formed in order to reduce the material cost and shorten the unit process time It is preferable to have a relatively thin thickness of about 400 to 600 angstroms.

4b, 5b and 6b, a solid phase crystallization (SPC) process is performed to improve the mobility characteristics of the pure amorphous silicon layer (112 of Figs. 4A, 5A and 6A) The pure amorphous silicon layer (112 of FIGS. 4A, 5A, and 5B) is crystallized to form a pure polysilicon layer 113. As shown in FIG. In this case, the solid phase crystallization (SPC) may be performed using an alternating magnetic field crystallization (AMFC) apparatus in an atmosphere of 600 ° C. to 700 ° C. using an alternating magnetic field crystallization (AMFC) Crystallization is preferable.

4C, 5C, and 6C, the pure polysilicon layer 113 formed by crystallizing the pure amorphous silicon layer (112 of FIGS. 4A, 5A, and 6A) by the progress of the solid phase crystallization (SPC) (Not shown) to form a photoresist layer (not shown) by applying a photoresist to the photoresist layer (not shown), and a light transmission region and a blocking region (not shown) and a slit- (Not shown) having a semi-transmissive region (not shown) whose light transmittance is smaller than the transmissive region (not shown) and larger than the blocking region (not shown) by adjusting the amount of light passing through the diffraction grating Exposure or halftone exposure is performed.

Thereafter, the exposed photoresist layer (not shown) is developed so that the boundary of the pixel region P, the gate pad portion GPA, the storage region StgA, and the data pad portion DPA are formed on the pure polysilicon layer 113, A first photoresist pattern 191a having a first thickness is formed corresponding to the first polysilicon layer 113 and the data link portion DLA and a second photoresist pattern 191b having a first thickness is formed on the pure polysilicon layer 113 corresponding to the switching region TrA, A second photoresist pattern 191b having a second thicker thickness is formed.

Next, as shown in Figs. 4D, 5D and 6D, the pure polysilicon layer (113 of Figs. 4C, 5C and 6C) exposed to the outside of the first and second photoresist patterns 191a and 191b, The first inorganic insulating layer (108 of FIGS. 4C, 5C and 6C) and the first metal layer (103 of FIGS. 4C, 5C and 6C) The first metal pattern 104 and the inorganic insulating pattern 104 are sequentially stacked in the gate pad portion GPA, the storage region StgA, the data pad portion DPA, the data link portion DLA and the switching region TrA, (109) and a pure polysilicon pattern (114) are formed.

Next, as shown in FIGS. 4E, 5E, and 6E, the substrate 101 having the first metal pattern 104, the inorganic insulating pattern 109, and the pure polysilicon pattern 114 sequentially stacked is subjected to ashing ashing is performed to remove the first photoresist pattern having the first thickness (191a in FIGS. 4D, 5D and 6D), thereby forming a boundary between the boundary of the pixel region P excluding the switching region TrA and the gate pad portion GPA and the polysilicon pattern 114 formed in the storage region StgA, the data pad portion DPA and the data link portion DLA. At this time, the second photoresist pattern 191b is also reduced in thickness by the ashing process, but remains in the switching region TrA.

 Next, as shown in Figs. 4F, 5F and 6F, the polysilicon patterns (114 of Figs. 4E, 5E and 6E) exposed to the outside of the second photoresist pattern 191b remaining in the switching region TrA, (Not shown) is formed on the boundary of the pixel region P by etching and removing the inorganic insulating pattern (109 of FIGS. 4E, 5E, and 6E) A gate pad electrode 117 is formed on the gate pad portion GPA and the data pad electrode 118 and the data link pattern 119 are connected to each other in the data pad portion DPA and the data link portion DLA, And the first storage electrode 106 is formed in the storage region StgA. At this time, the first storage electrode 106 may be connected to the gate wiring (not shown) or by forming a storage wiring (not shown) in parallel with the gate wiring (not shown) May form the first storage electrode 106 by itself.

Meanwhile, in the switching region TrA, a first metal pattern having the same area and shape as the lower portion of the second photoresist pattern 191b, an inorganic insulating pattern and a polysilicon pattern are sequentially stacked, 105, a gate insulating film 110, and an active layer 115 of pure polysilicon.

Next, as shown in FIGS. 4G, 5G, and 6G, a strip is advanced to remove the second photoresist pattern (191b in FIG. 4F) remaining on the active layer 115 of the pure polysilicon Thereby exposing the active layer 115 of the pure polysilicon.

Next, as shown in FIGS. 4H, 5H and 6H, the active layer 115, the gate wiring (not shown), the gate pad electrode 117 and the first storage electrode 106 of the exposed pure polysilicon and data depositing a pad electrode 118 and the data link pattern (119) over the inorganic insulating material, for example silicon oxide (SiO ₂₎ or silicon nitride (SiNx) to form a second inorganic insulating layer (not shown).

Thereafter, the second inorganic insulating layer (not shown) is patterned by a mask including a series of unit processes such as coating of photoresist, exposure using an exposure mask (not shown), development of exposed photoresist, etching and strip, So as to cover the active layer 115 of the pure polysilicon and serve as an etch stopper corresponding to the central portion of the active layer 115 of the pure polysilicon and serve as an etch stopper An interlayer insulating film 122 is formed. At this time, the active layer 115 of the pure polysilicon is formed on the both sides of the active layer 115 of the pure polysilicon with respect to the center of the active polysilicon layer 115 in the interlayer insulating layer 122 formed on the active layer 115 of the pure polysilicon. A gate pad contact hole 126 exposing the gate pad electrode 117 is formed in the gate pad portion GPA and the data pad portion DPA is formed in the gate pad portion GPA, A data pad contact hole 127 exposing the data pad electrode 118 and a data link contact hole 128 exposing the data link pattern 119 are formed in the data link part DLA.

Next, as shown in FIGS. 4I, 5I, and 6I, an active contact hole 125 for exposing the active layer 115 of the pure polysilicon is formed, and at the center thereof, Impurity amorphous silicon is deposited on the entire surface of the insulating film 122 to form an impurity amorphous silicon layer (not shown) having a thickness of about 100 Å to 300 Å.

Thereafter, a second metal layer (not shown) is formed by continuously depositing a second metal material such as molybdenum (Mo) or molybdenum (MoTi) on the impurity amorphous silicon layer (not shown).

Next, the impurity amorphous silicon layer (not shown) located below the second metal layer (not shown) and the impurity amorphous silicon layer (not shown) are patterned by a mask process to form a gate electrode And a data line 131 which intersects the wiring (not shown) to define the pixel region P is formed. The data line 131 is formed so that the data link pattern 119 and one end of the data line pattern 119 are in contact with each other through the data link contact hole 128. The impurity amorphous silicon layer (not shown) And a first dummy pattern 130 made of an impurity amorphous silicon is formed under the data line 131 by patterning. The first dummy pattern 130 is interposed between the data line 131 and the data link pattern 119 at the portion where the data link contact hole 128 is formed, Is made of an impurity amorphous silicon and has a conductive characteristic, so that the electric connection between the data line 131 and the data link pattern 119 is not a problem.

The data line 131 is formed and source and drain electrodes 133 and 136 are formed on the interlayer insulating layer 122 in the switching region TrA so that the source and drain electrodes 133 and 136 are spaced apart from each other. And an ohmic contact layer 129 made of impurity amorphous silicon and in contact with the active layer 115 of the pure polysilicon through the active contact holes 125 is formed in the lower portions of the gate electrodes 133 and 136. At this time, the source electrode 133 formed in the switching region TrA and the data line 131 formed at the boundary between the pixel region P are formed to be connected to each other.

In the process of forming the data line 131 and the source and drain electrodes 133 and 136 as described above, the active layer 115 of the pure polysilicon forming the channel region functions as an isolating stopper The source and drain electrodes 133 and 136 are formed so as to be more accurately etched for patterning the ohmic contact layer 129. For example, when the source and drain electrodes 133 and 136 are formed, The layer 115 is completely unaffected. Therefore, it is understood that the problem mentioned in the related art, that is, the surface damage of the active layer 115 due to dry etching progress does not occur. That is, after the data line 131 and the source and drain electrodes 133 and 136 are formed by patterning the second metal layer (not shown), the data line 131 and the source and drain electrodes 133, The impurity amorphous silicon layer (not shown) exposed to the outside is removed by dry etching. In this case, in the switching region TrA, the amorphous silicon layer 136 is removed between the source and drain electrodes 133 and 136 The active layer 115 of the pure polysilicon is not affected at all by the dry etching because the interlayer insulating film 122 serving as an etch stopper is formed. Therefore, unlike the conventional array substrate fabrication, the impurity amorphous silicon layer (not shown) is patterned to prevent the surface of the active layer 115 of pure polysilicon from being dry-etched when the ohmic contact layer 129 is formed, The thickness of the active layer 115 of the pure polysilicon is not reduced and the active layer 115 of the pure polysilicon has a constant thickness in the entire switching region TrA.

At this time, the gate electrode 105 of the impurity polysilicon, the gate insulating film 109, the active layer 115 of pure polysilicon, the interlayer insulating film 122, and the interlayer insulating film 122, which are sequentially stacked in the switching region TrA, The ohmic contact layer 129 of the impurity amorphous silicon and the source and drain electrodes 133 and 136 constitute the thin film transistor Tr.

Although not shown in the drawing, when used as an array substrate for an organic electroluminescent device, the data line 131 is spaced apart from the data line 131 by a predetermined distance in the same layer on which the data line 131 is formed, (Not shown) may be further formed in each pixel region P and a plurality of thin film transistors Tr having the same structure in addition to the thin film transistor Tr connected to the gate wiring (not shown) and the data wiring 131 may be further formed in each pixel region P A driving thin film transistor (not shown) may be further formed.

  Next, as shown in FIGS. 4J, 5J, and 6J, the source and drain electrodes 133 and 136 and the ohmic contact layer 129 are formed on the substrate 101 on which the data line 131, the source and drain electrodes 133 and 136, For example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the entire surface of the data lines 131 and 133 and the data lines 131, A pixel electrode 150 directly contacting one end of the drain electrode 136 is formed on the interlayer insulating layer 122 in the region P and the pixel electrode 150 is formed in the storage region StgA on the interlayer insulating layer 122, A second storage electrode 152 connected to the electrode 150 and overlapped with the first storage electrode 106 is formed. That is, the second storage electrode 152 is a part of the pixel electrode 150. At this time, in the storage region StgA, the first storage electrode 106, the interlayer insulating film 122, and the second storage electrode 152 form a storage capacitor StgC.

At the same time, in the gate pad portion GPA, a gate auxiliary pad electrode 155 which contacts the gate pad electrode 117 is formed on the interlayer insulating layer 122 through a gate pad contact hole 126. Also, in the data pad unit DPA, the data assist pad electrode 157 is formed on the interlayer insulating film 122 to contact the data pad electrode 118 through the data pad contact hole 127, The array substrate 101 according to the embodiment of the present invention is completed.

Although not shown in the figure, when a driving thin film transistor (not shown) is formed in each of the pixel regions P, the drain electrode 136 of the thin film transistor Tr formed in the switching region TrA is formed in the A drain electrode (not shown) of the driving thin film transistor (not shown) is electrically connected to the pixel electrode 150 by contacting the pixel electrode 150. At this time, the thin film transistor Tr of the switching region TrA and the driving thin film transistor (not shown) are electrically connected to each other. In the case of an array substrate in which driving thin film transistors (not shown) are formed in the pixel region P and the thin film transistor Tr connected to the gate and data lines (not shown) 130 in the switching region TrA, Thereby forming an array substrate.

Since the active layer 115 of pure polysilicon and the doping process of the impurity are not required in the method of manufacturing the array substrate according to the embodiment of the present invention, The present invention is characterized in that it provides an array substrate 101 having a thin film transistor (Tr) that uses pure polysilicon as an active layer 115 through a via hole, thereby simplifying the process and reducing the manufacturing cost.

7 is a cross-sectional view of a data pad portion of an array substrate according to a modified example of the present invention. As shown in FIG. 7, Only the data pad electrode 218 may be formed on the substrate 201 so as to be connected to one end of a data line (not shown) without a data link pattern. At this time, a first dummy pattern 230 of impurity amorphous silicon is formed under the data pad electrode 218. That is, in the step of forming the gate wiring (not shown) and the gate pad electrode (117 of FIG. 5J) as in the embodiment, the data link pattern and the data pad electrode are not formed. In the data pad portion DPA, (Not shown) are formed on the boundary of the pixel region on the interlayer insulating film 222, and at the same time, a data line (not shown) is formed in the data pad portion DPA And a data pad electrode 218 connected to one end of the data line (not shown) may be formed. In this modification, in forming the pixel electrode (not shown), the data assist pad electrode 257 is formed to completely cover the data pad electrode 218 when the transparent conductivematerial layer is patterned. In this case, the data pad electrode 218 contacts the data assist pad electrode 257 without a data pad contact hole. Other processes are the same as those of the above-described embodiment, and a description thereof will be omitted.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device, in which one pixel region is cut including a thin film transistor. Fig.

FIGS. 2A to 2E are process cross-sectional views showing steps of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate; FIGS.

3 is a cross-sectional view of a pixel region including the thin film transistor in an array substrate having a thin film transistor having a conventional polysilicon semiconductor layer.

FIGS. 4A through 4J are cross-sectional views illustrating steps of manufacturing one pixel region including a thin film transistor and a storage capacitor of an array substrate according to an embodiment of the present invention. FIG.

5A to 5J are cross-sectional views illustrating steps of manufacturing a gate pad portion of an array substrate according to an embodiment of the present invention.

6A to 6J are cross-sectional views illustrating a data pad portion and a data link portion of an array substrate according to an embodiment of the present invention.

7 is a cross-sectional view illustrating a data pad portion of an array substrate according to a modification of the present invention.

Description of the Related Art

101: substrate 105: gate electrode

106: first storage electrode 110: gate insulating film

115: active layer of pure polysilicon 122: interlayer insulating film

125: active contact hole 129: ohmic contact layer

130: first dummy pattern 131: data wiring

133: source electrode 136: drain electrode

150: pixel electrode 152: second storage electrode

P: pixel area StgA: storage area

StgC: storage capacitor Tr: thin film transistor

TrA: switching area

Claims (8)

Forming a first metal layer, a first inorganic insulating layer, and a pure amorphous silicon layer on a substrate in which a switching region is defined in the pixel region; Crystallizing the pure amorphous silicon layer into a pure polysilicon layer by performing a solid phase crystallization process; Forming a gate electrode, a gate insulating film, and an active layer of pure polysilicon sequentially on the switching region by patterning the pure polysilicon layer, the first inorganic insulating layer, and the first metal layer, Forming a gate wiring connected to the electrode and extending in one direction; Depositing and patterning an inorganic insulating material on the active layer and the gate wiring over the entire surface to form an interlayer insulating film having an active contact hole exposing and spacing the active layer and covering the gate wiring;  An ohmic contact layer of an impurity amorphous silicon which is in contact with the active layer and is spaced apart from each other through the active contact hole on the interlayer insulating film; source and drain electrodes spaced apart from each other on the ohmic contact layer; Forming a data line connected to the source electrode and intersecting the gate line to define the pixel region; Forming a pixel electrode in the pixel region on the interlayer insulating film in direct contact with one end of the drain electrode; Wherein the substrate is a substrate. The method according to claim 1, Wherein forming the gate wiring includes: A gate pad electrode connected to the first storage electrode and one end of the gate wiring, a data link pattern contacting the one end of the data line, and a data pad electrode connected to the data link pattern are formed on the substrate in the pixel region The method comprising the steps of: 3. The method of claim 2, Wherein forming the interlayer insulating film comprises: A gate pad contact hole exposing the gate pad electrode; a data link contact hole exposing the data link pattern; and a data pad contact hole exposing the data pad electrode. The method of claim 3, Wherein forming the pixel electrode includes: A gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole, And forming a second storage electrode that forms a storage capacitor. 3. The method of claim 2, A gate electrode, a gate insulating film, and an active layer of pure polysilicon sequentially stacked in an island shape in the switching region, a gate electrode, a gate electrode, a data pad electrode, The forming of the data link pattern may include: A first photoresist pattern having a first thickness corresponding to the switching region is formed on the pure polysilicon layer, and the gate wiring, the first storage electrode, the gate and the data pad electrode, and the data link pattern are formed Forming a second photoresist pattern having a second thickness that is thinner than the first thickness corresponding to the portion of the first photoresist pattern; The pure second polysilicon layer exposed outside the first and second photoresist patterns and the second inorganic insulating layer and the first metal layer below the first and second photoresist patterns are sequentially removed to sequentially form the gate electrode and the gate insulating film And an active layer of a pure polysilicon are formed, and the gate wiring, the first storage electrode, the gate and the data pad electrode, and the data link pattern are formed at the boundary of the pixel region, Forming an inorganic insulating pattern and a pure polysilicon pattern on the first storage electrode, the gate and data pad electrode, and the data link pattern, respectively; Exposing the gate electrode, the first storage electrode, the gate electrode, the data pad electrode, and the pure polysilicon pattern located in the upper portion of the data link pattern, respectively, by ashing and removing the second photoresist pattern; Removing the inorganic polysilicon pattern and the inorganic insulating pattern below the pattern; Removing the first photoresist pattern Wherein the substrate is a substrate. The method according to claim 1, Wherein forming the gate wiring includes forming a first storage electrode in the pixel region and a gate pad electrode connected to one end of the gate wiring, Wherein forming the interlayer insulating film includes forming a gate pad contact hole exposing the gate pad electrode, Wherein forming the data line includes forming a data pad electrode connected to one end of the data line, The method of claim 1, wherein forming the pixel electrode comprises: a gate assist pad electrode contacting the gate pad electrode through the gate pad contact hole; a data aiding pad electrode covering the data pad electrode; And forming a second storage electrode connected to the electrode. The method according to any one of claims 1, 2, and 6, Wherein the solid-phase crystallization process is an alternating magnetic field crystallization process using heat treatment or an alternating magnetic field crystallization (AMFC) device. The method according to any one of claims 1, 2, and 6, Wherein the active layer of the pure polysilicon is formed to have a thickness of about 400 to 600 ANGSTROM.

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