KR101713146B1 - Array substrate for organic electroluminescent device and method of fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate, and more particularly, to a thin film transistor having an active layer which suppresses the surface damage of the active layer from occurring by dry etching progress and has an excellent mobility characteristic, and further, To an array substrate.
The present invention has an effect of preventing the surface layer from being damaged due to the fact that the active layer is not exposed to the dry etching because the interlayer insulating film serving as an etch stopper is provided and the characteristics of the thin film transistor are prevented from being deteriorated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic electroluminescent device,

The present invention relates to an array substrate, and more particularly, to a thin film transistor having an active layer which suppresses the surface damage of the active layer from occurring by dry etching progress and has an excellent mobility characteristic, and further, To an array substrate.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix type liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling on / off of a voltage for each pixel, The ability is excellent and is getting the most attention.

In addition, since the organic electroluminescent device has a high luminance and a low operating voltage characteristic and is a self-luminous type that emits light by itself, it has a large contrast ratio, can realize an ultra-thin display, has a response time of several microseconds Mu s), has no limitation of viewing angles, is stable at low temperatures, and is driven at a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit, and has recently attracted attention as a flat panel display device.

In such a liquid crystal display device and an organic electroluminescent device, an array substrate including a thin film transistor, which is a switching element, is provided in order to commonly turn on / off each pixel region. In addition, In the light emitting device, a driving thin film transistor for driving an organic light emitting diode other than the switching thin film transistor is provided in each pixel region of the array substrate.

FIG. 1 is a cross-sectional view of a conventional array substrate constituting an organic electroluminescent device including one pixel region including a driving thin film transistor. A region where the driving thin film transistor is formed for convenience of description is defined as a driving region.

A gate electrode 15 is formed in a drive region TrA in a plurality of pixel regions P in which a plurality of gate wirings (not shown) and a data line 33 are defined in the array substrate 11, And a gate insulating film 18 is formed on the entire surface of the gate electrode 15. An active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon A semiconductor layer 28 is formed. A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked, constitute a driving thin film transistor Tr. Although not shown in the figure, the pixel region has the same shape as the driving thin film transistor Tr and is connected to the driving thin film transistor Tr and the gate wiring (not shown) and the data wiring 33, (Not shown) are formed.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of the pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the driving region TrA in the conventional array substrate 11 having the above- The second thickness t2 of the portion where the ohmic contact layer 26 is formed and the first thickness t1 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method and the characteristic difference of the thin film transistor Tr occurs due to the difference in thickness (t1? T2) of the active layer 22 have.

2 is a cross-sectional view showing a step of forming a semiconductor layer and source and drain electrodes in a manufacturing step of a conventional array substrate. In the figure, the gate electrode and the gate insulating film are omitted for convenience of explanation.

As shown in the figure, a pure amorphous silicon layer (not shown) is formed on the substrate 11, an impurity amorphous silicon layer (not shown) and a metal layer (not shown) are sequentially formed thereon, A source drain pattern (not shown) is formed as a metal material, and an impurity amorphous silicon pattern (not shown) and an active layer (not shown) are formed thereunder.

Then, the central portion of the source / drain pattern is etched and removed to form source and drain electrodes 36 and 38 spaced apart from each other. At this time, the impurity amorphous silicon pattern (not shown) is exposed between the source and drain electrodes 36 and 398.

Next, dry etching is performed on the impurity amorphous silicon pattern (not shown) exposed in the spacing region between the source and drain electrodes 36 and 38 to expose the impurity exposed between the source and drain electrodes 36 and 38 An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing an amorphous silicon pattern (not shown).

At this time, the dry etching is performed for a sufficiently long time to completely remove the impurity amorphous silicon pattern (not shown) exposed between the source and drain electrodes 36 and 38. In this process, the impurity amorphous silicon pattern (not shown) A portion of the active layer 22 located at a position where the impurity amorphous silicon pattern (not shown) is removed is etched to a predetermined thickness. Therefore, in the active layer 22, there is a difference in thickness (t1? T2) between the portion where the ohmic contact layer 26 is formed on the active layer 22 and the portion where the ohmic contact layer 26 is formed. If the dry etching is not performed for a sufficiently long time, the impurity amorphous silicon pattern (not shown) to be removed in the spacing region between the source and drain electrodes 36 and 38 remains on the active layer 22, This is to prevent the degradation of characteristics.

Therefore, in the above-described conventional method of manufacturing the array substrate 11, a difference in thickness of the active layer 22 necessarily occurs, resulting in deterioration of the characteristics of the thin film transistor (Tr in FIG. 1).

A pure amorphous silicon layer (not shown), which forms the active layer 22 sufficiently thick in consideration of the thickness at which the active layer 22 is etched away during the dry etching for forming the ohmic contact layer 26, It is necessary to deposit it to have a thickness, which results in an increase in deposition time and a decrease in productivity.

The most important constituent elements of the array substrate include a thin film transistor formed for each pixel region and connected to a gate line, a data line and a pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode .

However, in the case of a thin film transistor generally constituted in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using such an amorphous silicon, the amorphous silicon is disordered in its atomic arrangement. Therefore, the amorphous silicon changes to a metastable state upon irradiation with light or an electric field, which is a problem in stability when used as a thin film transistor device. The carrier mobility is as low as 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a device for a driving circuit.

In order to solve such a problem, a method of manufacturing a thin film transistor using polysilicon as an active layer by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by progressing a crystallization process using a laser device has been proposed.

3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate including a thin film transistor having a conventional polysilicon as a semiconductor layer, polysilicon is formed on the semiconductor layer (55b) containing impurities at high concentration on both sides of the first region (55a) in the semiconductor layer (55) made of polysilicon is used for manufacturing the array substrate (51) including the thin film transistor (Tr) Or the formation of a p + region (not shown). Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the progress of the doping process. In this case, the manufacturing cost is increased, and a problem arises that a manufacturing line must be newly constructed for manufacturing the array substrate 51 by adding new equipment.

In addition, in the case of an organic light emitting device, efficiency and lifetime of the organic light emitting layer have been a major issue, and the use of different organic light emitting materials emitting red, green, and blue has minimized the difference in luminous efficiency, An array substrate for an organic light emitting element having a structure that can be formed is desired.

An object of the present invention is to provide an array substrate in which the active layer is not exposed to dry etching and the surface of the active layer is not damaged, thereby improving the characteristics of the thin film transistor.

It is another object of the present invention to provide an array substrate having a thin film transistor which is formed of polysilicon but does not require a doping process and can improve mobility characteristics.

It is another object of the present invention to provide an array substrate for an organic light emitting device having a structure capable of maximizing luminous efficiency for each organic luminescent material while using different organic luminescent materials emitting red, green, and blue light.

According to an aspect of the present invention, there is provided an array substrate comprising: a buffer layer formed on a substrate having a pixel region, a switching region, a driving region, and a storage region defined in the pixel region; First and second gate electrodes formed in the switching region and the driving region on the buffer layer, the first and second gate electrodes being formed of a high melting point metal material in an island shape; A gate insulating layer formed on the first and second gate electrodes to expose one end of each of the first and second gate electrodes in an island shape; First and second active layers of pure polysilicon formed on the gate insulation layer in correspondence with the first and second gate electrodes, respectively, and exposing edges of the respective gate insulation layers; A gate wiring formed in contact with the first gate electrode exposed to the outside of the gate insulating film and formed at a boundary of a pixel region and a gate auxiliary pattern formed in contact with the second gate electrode; First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced from each other, An interlayer insulating film formed on the entire surface of the substrate, the interlayer insulating film serving as an etch stopper for the central portion of each layer; A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A second ohmic contact layer of impurity amorphous silicon in contact with the second active layer through the third and fourth active contact holes; A first source and drain electrode spaced apart from the first ohmic contact layer and spaced apart from the first ohmic contact layer, and a second source and drain electrode spaced apart from the second ohmic contact layer, A data line formed on the interlayer insulating film and connected to the first source electrode at a boundary of the pixel region; A protective layer formed on the data line with first and second drain contact holes exposing the first and second drain electrodes, respectively, and a gate contact hole exposing the gate assist pattern; A pixel electrode formed in contact with the second drain electrode through the second drain contact hole in each pixel region on the protective layer; And a connection pattern formed in contact with the first drain electrode and the gate assist pattern through the first drain contact hole and the gate contact hole, wherein openings are formed in the pixel regions.

The opening is characterized in that the interlayer insulating layer is removed. At this time, the opening may be provided with a buffer layer thinner than the other region by removing a certain thickness of the upper surface of the buffer layer.

In addition, the opening is characterized in that the protective layer and the interlayer insulating film are removed. At this time, the opening may be provided with a buffer layer thinner than the other region by removing a certain thickness of the upper surface of the buffer layer.

The opening may be formed by selectively removing only the interlayer insulating film in each pixel region, removing a part of the thickness of the interlayer insulating film and the buffer layer, removing the protective layer and the interlayer insulating film, And the insulating layer and a part of the upper surface of the buffer layer are removed to have different opening structures.

According to another aspect of the present invention, there is provided an array substrate including a pixel region, a switching region, a driving region and a storage region within the pixel region, A first gate electrode and a second gate electrode; A gate insulating layer formed on the first and second gate electrodes to expose one end of each of the first and second gate electrodes in an island shape; First and second active layers of pure polysilicon formed on the gate insulation layer in correspondence with the first and second gate electrodes, respectively, and exposing edges of the respective gate insulation layers; A gate wiring formed in contact with the first gate electrode exposed to the outside of the gate insulating film and formed at a boundary of a pixel region and a gate auxiliary pattern formed in contact with the second gate electrode; First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced apart from each other, and gate contact An interlayer insulating layer formed on the entire surface of the substrate, the interlayer insulating layer serving as an etch stopper for the central portion of each of the first and second active layers; A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A second ohmic contact layer of impurity amorphous silicon in contact with the second active layer through the third and fourth active contact holes; A first source and drain electrode spaced apart from the first ohmic contact layer and spaced apart from the first ohmic contact layer, and a second source and drain electrode spaced apart from the second ohmic contact layer, A data line formed on the interlayer insulating film and connected to the first source electrode at a boundary of the pixel region; A pixel electrode formed in the pixel region in contact with the second drain electrode over the interlayer insulating film; And a connection pattern formed on the interlayer insulating film at the same time with the gate assist pattern through the first drain electrode and the gate contact hole, and an opening is formed in each pixel region.

At this time, the opening is characterized in that the interlayer insulating layer is removed, and the opening may have a buffer layer thinner than the other region by removing a predetermined thickness of the upper surface of the buffer layer.

A method of manufacturing an array substrate according to an embodiment of the present invention includes forming a buffer layer on a front surface of a substrate having a pixel region having an opening and a switching region and a driving region and a storage region defined in the pixel region; Forming first and second gate electrodes with a high melting point metal material in an island form in the switching region and the driving region over the buffer layer; Forming a gate insulating layer on the first and second gate electrodes to expose one end of each of the first and second gate electrodes, respectively, in an island shape; Forming first and second active layers of pure polysilicon to expose respective edges of the gate insulating layer to the upper portion of the gate insulating layer in correspondence with the first and second gate electrodes; Forming a gate interconnection in contact with the first gate electrode exposed to the outside of the gate insulating film and formed in a boundary of a pixel region and a gate assist pattern in contact with the second gate electrode; First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced from each other, Forming an interlayer insulating film serving as an etch stopper at the center of each of the first and second active layers; A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A first source formed in contact with the second active layer through the third and fourth active contact holes and spaced apart from the second ohmic contact layer of the impurity amorphous silicon and the first ohmic contact layer spaced apart from the first active contact layer, Drain electrode, a second source and drain electrode spaced apart from the second ohmic contact layer and spaced apart from each other, and a data line connected to the first source electrode at the boundary of the pixel region on the interlayer insulating layer Wow; Forming a protective layer over the data line, the protective layer having first and second drain contact holes exposing the first and second drain electrodes, respectively, and a gate contact hole exposing the gate assist pattern; A pixel electrode which is in contact with the second drain electrode through the second drain contact hole in each of the pixel regions on the protective layer, and a second drain electrode which is in contact with the first drain electrode and the gate auxiliary And forming a connection pattern that simultaneously contacts the pattern.

At this time, the step of forming the protective layer includes forming a second opening exposing the buffer layer in the pixel region corresponding to the first opening formed in the interlayer insulating film.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate, including the steps of: forming a buffer layer on a pixel region having an opening, a switching region, a driving region and a storage region defined in the pixel region; ; Forming first and second gate electrodes with a high melting point metal material in an island form in the switching region and the driving region over the buffer layer; Forming a gate insulating layer on the first and second gate electrodes to expose one end of each of the first and second gate electrodes, respectively, in an island shape; Forming first and second active layers of pure polysilicon to expose respective edges of the gate insulating layer to the upper portion of the gate insulating layer in correspondence with the first and second gate electrodes; Forming a gate interconnection in contact with the first gate electrode exposed to the outside of the gate insulating film and formed in a boundary of a pixel region and a gate assist pattern in contact with the second gate electrode; First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced apart from each other, Forming an interlayer insulating film having a gate contact hole exposing the gate assistant pattern and serving as an etch stopper for the central portion of each of the first and second active layers; A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A first source formed in contact with the second active layer through the third and fourth active contact holes and spaced apart from the second ohmic contact layer of the impurity amorphous silicon and the first ohmic contact layer spaced apart from the first active contact layer, Drain electrode, a second source and drain electrode spaced apart from the second ohmic contact layer and spaced apart from each other, and a data line connected to the first source electrode at the boundary of the pixel region on the interlayer insulating layer Wow; Forming a connection pattern in contact with the gate auxiliary pattern through the gate contact hole and simultaneously contacting the first drain electrode; .

Before the first and second ohmic contact layers are formed, the first and second active layers are exposed through the first, second, third and fourth active contact holes, and then cleaned using a buffered oxide etchant (BOE) Removing the oxide film on the surfaces of the first and second active layers exposed through the first, second, third and fourth active contact holes and reducing the thickness of the upper surface of the buffer layer exposed through the first opening, .

The first and second openings are selectively formed in each pixel region.

The array substrate according to the present invention has an interlayer insulating film serving as an etch stopper to prevent the active layer from being exposed to the dry etching so that surface damage does not occur and the characteristics of the thin film transistor are prevented from deteriorating.

In addition, since the active layer is not affected by the dry etching, it is unnecessary to consider the thickness of the active layer to be etched away. Therefore, the thickness of the active layer is reduced, thereby reducing the deposition time and improving the productivity.

The array substrate according to the present invention is characterized in that the amorphous silicon layer is crystallized into a polysilicon layer by a crystallization process and the thin film transistor is formed by using the semiconductor layer as a semiconductor layer to thereby obtain a mobility versus an array substrate having a thin film transistor including a semiconductor layer of an amorphous silicon layer There is an effect of improving the characteristics by tens to hundreds of times.

Since the polysilicon layer is used as an active layer of the thin film transistor, doping of the impurity is not required, so that it is not necessary to invest new equipment to proceed the doping process, thereby reducing the initial investment cost.

In addition, by proposing the opening shapes of various structures of each pixel region, the light emitting efficiency of the organic light emitting layer can be maximized by selectively configuring the most suitable opening shape according to the material characteristics of the organic light emitting layer.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device or an organic electroluminescent device, in which one pixel region is cut including a thin film transistor. Fig.
2 is a process sectional view showing a step of forming a semiconductor layer and source and drain electrodes in a conventional array substrate fabrication step;
3 is a cross-sectional view of a pixel region including the thin film transistor in an array substrate having a thin film transistor having a conventional polysilicon semiconductor layer.
4 is a plan view of one pixel region in the array substrate according to the first embodiment of the present invention constituting the organic electroluminescent device.
5 is a cross-sectional view of one pixel region of an array substrate according to a first modification of the first embodiment of the present invention.
6 is a cross-sectional view of one pixel region of an array substrate according to a second modification of the first embodiment of the present invention;
7 is a cross-sectional view of one pixel region of an array substrate according to a third modification of the first embodiment of the present invention;
8 is a sectional view of one pixel region in an array substrate according to a second embodiment of the present invention constituting an organic electroluminescent device.
9 is a cross-sectional view of one pixel region of an array substrate according to a first modification of the second embodiment of the present invention.
10 is a cross-sectional view of one pixel region of an array substrate according to a second modification of the second embodiment of the present invention;
11A to 11K are cross-sectional views illustrating steps of manufacturing a pixel region in an array substrate according to a third modification of the first embodiment of the present invention constituting an organic electroluminescent device.
12A to 12B are cross-sectional views illustrating steps of manufacturing a pixel region in an array substrate according to a second modification of the second embodiment of the present invention, which constitutes an organic electroluminescent device.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

4 is a cross-sectional view of one pixel region in the array substrate according to the first embodiment of the present invention constituting the organic electroluminescent device. For convenience of explanation, a region where the switching thin film transistor ST is formed in the pixel region P is referred to as a switching region SA, a region where the driving thin film transistor DTr is formed is referred to as a driving region DA, Area is defined as a storage area (StgA).

As shown in the drawing, the array substrate 101 according to the embodiment of the present invention has a buffer layer 102 formed of an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on its entire surface. The buffer layer 102 is crystallized in a later process due to the characteristics of the present invention. The crystallization process requires an atmosphere at a high temperature of 600 to 800 ° C. In this case, the substrate 101 is heated to a high temperature As a result of the exposure, alkaline ions may be eluted from the surface of the substrate 101 to degrade the characteristics of the component made of polysilicon.

A molybdenum (Mo), a molybdenum (Mo) alloy including molybdenum (Mo), a molybdenum (Mo) alloy having a melting point of 800 占 폚 or more in each of the switching region SA and the driving region, The first gate electrode 105a and the second gate electrode each having a thickness of about 100 Å to 1000 Å and made of any one of copper (Cu), copper (Al), titanium (Ti), tantalum (Ta), and tungsten (W) Respectively. At this time, each of the first gate electrodes 105a formed on the same line along the gate line is extended to a portion where the gate line 145 is to be formed, thereby being connected to each other. This is due to the manufacturing method, which is patterned together with the gate wiring 145.

A gate insulating layer 109 made of an insulating material is formed on the first and second gate electrodes 105a and 105b. At this time, the gate insulating layer 109 is completely overlapped with the first and second gate electrodes 105a and 105b and is formed in an island shape, and the first and second gate electrodes 105a and 105b And is formed by exposing one end of the first electrode.

And the first and second gate electrodes (111, 112) which are overlapped completely on the respective island-shaped gate insulating films (109) and which are smaller than the respective gate insulating films (109) The first active layer 115a of pure polysilicon and the second active layer 115b are formed correspondingly to the first polysilicon layer 105a and the second polysilicon layer 150b.

The pixel region P is located at an upper portion of the gate insulating film exposed to the outside of the first active layer 115a in contact with the first gate electrode 105a exposed to the outside of the gate insulating film 109, A gate wiring 119 is formed at the boundary between the source and drain electrodes. The storage region StgC is formed with a gate auxiliary pattern 119 which is made of the same metal material having the gate wiring 119 and which is in contact with each of the second gate electrodes 105b and serves as a first storage electrode 121. [ (Not shown).

 The first and second active layers 115a and 115b are formed on the entire surface of the substrate 101 over the first and second active layers 115a and 115b, the gate line 119, Second, third, and fourth active contact holes 123a, 123b, 123c, and 123d exposing the first and second active layers 115a and 115b on both sides thereof with respect to the center of each of the first and second active layers 115a and 115b, (Not shown).

The first active layer 115a and the second active layer 115b are formed on the interlayer insulating layer 122 so as to be in contact with the switching region SA through the first and second active contact holes 123a and 123b, And first source and drain electrodes 133a and 136a are formed on top of the first ohmic contact layer 127a.

The second active layer 115b is formed on the interlayer insulating layer 122 so as to be in contact with the driving region DA through the third and fourth active contact holes 123c and 123d, And second source and drain electrodes 133b and 136b are formed on top of the second ohmic contact layer 127b. At this time, the second source electrode 133b extends to the storage region StgA to form a second storage electrode 137.

At this time, the first storage electrode 121, the gate insulating film 109, the interlayer insulating film 122, and the second storage electrode 137, which are sequentially stacked in the storage region StgA, form a storage capacitor StgC.

The first gate electrode 105a sequentially stacked in the switching region SA and the gate insulating film 109 and the first active layer 115a of pure amorphous silicon and the first and second active contact holes 123a The first source and drain electrodes 133a and 136a spaced apart from the first ohmic contact layer 127a of the impurity amorphous silicon which are spaced apart from each other and the interlayer insulating film 122 having the first and second source and drain electrodes 123a and 123b form a switching thin film transistor STr .

The second gate electrode 105b sequentially stacked in the driving region DA and the gate insulating film 109 and the second active layer 115b of pure amorphous silicon and the third and fourth active contact holes 123c And 123d and the second source and drain electrodes 133b and 136b which are spaced apart from the second ohmic contact layer 127b of the impurity amorphous silicon which are spaced apart from each other constitute a driving thin film transistor DTr .

Although not shown in the drawing, the pixel region P is defined on the interlayer insulating film 122 by being connected to the first source electrode 133a of the switching thin film transistor STr and intersecting the gate wiring 119, And a power supply line (not shown) is formed, which is connected to the second source electrode 136b and spaced apart from the data line (not shown).

Next, a protective layer 140 made of an insulating material is formed on the entire surface of the first source and drain electrodes 133a and 136a and the second source and drain electrodes 133b and 136b. At this time, the protective layer 140 and the interlayer insulating layer 122 at the lower part thereof are patterned to expose the second gate electrode 105b, more precisely, the gate assist pattern 120 overlapping the two gate electrodes 105b And a gate contact hole 153. The passivation layer 140 includes first and second drain contact holes 152a and 152b for exposing the first and second drain electrodes 136a and 136b, And a power contact hole (not shown) for exposing a power electrode (not shown).

The pixel electrode 170 is formed on the passivation layer 140 by a transparent conductive material in the pixel region P and is in contact with the second drain electrode 136b through the second drain contact hole 152b. And a connection electrode 172 is formed which simultaneously contacts the first drain electrode 136a and the gate assist pattern 120 through the first drain contact hole 152a and the gate contact hole 153 .

On the other hand, in the array substrate 101 according to the first embodiment of the present invention having the above-described structure, since the first and second active layers 115a and 115b of pure polysilicon are formed, have.

In addition, since the interlayer insulating film 122 serves as an etch stopper for the central portions of the first and second active layers 115a and 115b in which the channel region is formed, the thickness of the interlayer insulating film 122 does not change, It is possible to prevent deterioration of the characteristics of the thin film transistor due to the change.

Although not shown in the drawing, the pixel electrode 170 and the gate connection electrode 172 and the second passivation layer 150 are formed so as to cover the boundary between each pixel region P and a portion inside the pixel region P A bank (not shown) is formed as an insulating material and overlaps a rim portion of each pixel electrode 170 with respect to the pixel region SA and the driving region DA, An organic light emitting layer (not shown) that emits red, green, and blue light is sequentially and repeatedly formed in the display region on the pixel electrode 170, and the organic light emitting layer (not shown) And a reference electrode (not shown) is formed on the entire surface of the display region. The pixel electrode 170, the organic light emitting layer (not shown), and the reference electrode (not shown), which are sequentially stacked in each pixel region P, form an organic light emitting diode (not shown).

On the other hand, in the array substrate 101 according to the first embodiment of the present invention having such a structure, the structure of the portion where the organic light emitting layer is formed in each pixel region (hereinafter referred to as an opening portion) A buffer layer made of an insulating material, an interlayer insulating layer, and a protective layer, and a pixel electrode is formed on the protective layer.

The array substrate 101 according to the first embodiment of the present invention having the above-described structure can have various modifications particularly in the openings, and thereafter, the first through third modifications according to the first embodiment of the present invention The sectional structure of the array substrate according to the example will be described. Here, in the first to third modifications of the first embodiment, the same reference numerals are given to the same constituent elements as those of the first embodiment, and the sectional structure thereof is the same as that of the first embodiment except for the opening, Explain that there is a part.

5 and 6 are sectional views of one pixel region of the array substrate according to the first and second modified examples of the first embodiment of the present invention.

In the case of the array substrate 101 according to the first and second modified embodiments of the first embodiment of the present invention, the structure of the opening includes a buffer layer formed on a substrate, a protective layer formed on the buffer layer, A pixel electrode is formed on the protective layer. At this time, in the case of the first modification, since the buffer layer is also removed by a thickness of the upper layer, the buffer layer is thinner than other regions.

In the case of the second modification, the buffer layer is formed on the entire surface of the substrate to have the same thickness, and the buffer layer and the protective layer are formed by removing only the interlayer insulating film according to the first embodiment.

In the case of the openings of the array substrate according to the first and second modified examples having such a configuration, only the interlayer insulating film and the buffer layer thickness or the interlayer insulating film are removed relative to the first embodiment, It can be seen that the thickness is thin.

7 is a cross-sectional view of one pixel region of the array substrate according to the third modification of the first embodiment of the present invention.

In the case of the array substrate 101 according to the third modification of the first embodiment of the present invention, a buffer layer having a thinner thickness than the other regions is formed on the substrate, Is formed. Therefore, in the third modification, the interlayer insulating layer and the protective layer are completely removed from the first embodiment and the buffer layer is partially removed.

On the other hand, the array substrate according to the first embodiment and the first to third modified examples described above can be formed without adding any additional process through the same mask process, and thus, different organic When an organic light emitting layer is formed using a light emitting material, the most suitable type of opening is selectively provided in consideration of the material characteristics of the organic light emitting material for emitting each color, thereby imparting an appropriate confinement effect to the light emitted from the organic light emitting layer So that the luminous efficiency of each color can be maximized.

That is, the above-described different opening structures are configured differently for each pixel region in which the red, green and blue organic emission patterns are formed. For example, in the pixel region in which the organic emission layer for blue emission is formed, And an organic light emitting layer for blue light emission is formed so as to have an opening shape according to the first modification of the first embodiment corresponding to the pixel region in which the organic light emitting layer for green light emission is to be formed It is possible to maximize the luminous efficiency by providing a concave effect suited to the material characteristics of the luminescent materials of the respective colors by providing the opening shape according to the second modification of the first embodiment.

In this case, an example having the opening structure according to the first embodiment corresponding to the portion where the red light emitting layer will be formed has been described as an example, but the present invention is not limited thereto. And the portions where the green and blue light emitting layers are to be formed may have any opening structure shown in the first embodiment and the first to third modifications thereof in consideration of the material characteristics of the organic light emitting material constituting each light emitting layer. Can be achieved.

8 is a cross-sectional view of one pixel region in the array substrate according to the second embodiment of the present invention constituting the organic electroluminescent device. For convenience of explanation, a region where the switching thin film transistor ST is formed in the pixel region P is referred to as a switching region SA, a region where the driving thin film transistor DTr is formed is referred to as a driving region DA, Area is defined as a storage area (StgA), and 100 is added to the same constituent elements as those of the first embodiment. In this case, the second embodiment has a similar structure to that of the first embodiment, and therefore, the description will be focused on the portions having different points.

In the second embodiment of the present invention, the protective layer is omitted in the configuration that is most different from the first embodiment. The pixel electrode 270 is formed in contact with one end of the second drain electrode 236b on the interlayer insulating film 222 in each pixel region P and the first drain electrode 236a and the gate assist pattern 220 or the first drain electrode 236a through the gate contact hole 253 provided in the interlayer insulating film 222. The gate electrode 252 is electrically connected to one end of the first drain electrode 236a, And is formed on the interlayer insulating film 222 in contact with the pattern 220 at the same time. The other constituent elements have the same structure as that of the first embodiment described above, and a description thereof will be omitted.

On the other hand, in the opening portion where the organic light emitting layer of the array substrate 201 according to the second embodiment of the present invention having the above-described structure is formed, a buffer layer and an interlayer insulating film are formed and a pixel electrode is formed on the interlayer insulating film Feature.

In the case of the array substrate according to the second embodiment of the present invention, the insulating layer is formed as a buffer layer, a gate insulating film, and an interlayer insulating film by the 5-mask process. At this time, since the gate insulating film is formed only in a region where the first and second gate electrodes are formed in the island shape, the insulating layer that can be formed substantially in the opening is a buffer layer and an interlayer insulating film. In the case of the second embodiment, All the insulating layers that can be formed in the opening of the laminated structure characteristic that can be manufactured are all formed.

9 and 10 are sectional views of one pixel region of the array substrate according to the first and second modification of the second embodiment of the present invention.

In the first modification of the second embodiment, the difference from the second embodiment is in the opening. That is, in the case of the second embodiment, both the buffer layer and the interlayer insulating film are formed in the opening, but in the first and second modified examples of the second embodiment, the interlayer insulating film is completely removed and only the buffer layer is formed. In this case, in the first modification, the buffer layer has the same thickness as the other regions. In the second modification, the buffer layer having a thin thickness is formed by removing a thickness of the upper portion of the buffer layer.

On the other hand, the array substrate according to the second embodiment and the first and second modified examples described above can be formed without adding any additional process through the same mask process, and thus, different organic luminescence When an organic light emitting layer is formed by using a material, the opening of the most suitable shape is selectively provided in consideration of the material characteristics of the organic light emitting material for emitting each color, thereby giving an appropriate concave effect to the light emitted from the organic light emitting layer The luminous efficiency of each color can be maximized.

That is, as in the first embodiment and the first through third modifications thereof, it is possible to selectively configure the shape of the opening for one array substrate. For example, the opening of the pixel region where the red light emitting layer is to be formed is formed to have the opening structure shown in the second embodiment, and the opening shown in the second embodiment or the first and second light emitting layers corresponding to the pixel region, It can be formed to have an opening structure capable of improving the luminous efficiency by implementing the most complex effect of the opening structure shown in the second modification.

Hereinafter, the method of manufacturing the array substrate according to the first embodiment and the first to third modifications of the present invention will be described. Here, for the sake of convenience, the third modification of the first embodiment will be mainly described. In the first embodiment and the first and second modifications thereof, only the portions having differentiation will be described.

11A to 11K are cross-sectional views illustrating steps for manufacturing one pixel region in an array substrate according to a third modification of the first embodiment of the present invention constituting the organic electroluminescent device. For convenience of explanation, a region where the switching thin film transistor ST is formed in the pixel region P is referred to as a switching region SA, a region where the driving thin film transistor DTr is formed is referred to as a driving region DA, Area is defined as a storage area (StgA).

First, as shown in Figure 11a, a transparent insulating substrate 101, for example, insulating material on the glass substrate, for example deposition of a silicon oxide inorganic insulating material (SiO ₂₎ or silicon nitride (SiNx), or insulating organic A buffer layer 102 is formed on the entire surface by applying a material such as benzocyclobutene (BCB) or photo acryl. In this case, since the substrate 101 is exposed to a high-temperature atmosphere, the substrate 101 (101) is exposed to a high-temperature atmosphere, The alkaline ion may be eluted from the surface of the substrate to degrade the characteristics of the component made of polysilicon. Therefore, the buffer layer 102 is formed to prevent such a problem.

In the third modification of the first embodiment of the present invention, the buffer layer is formed of silicon oxide (SiO ₂ ).

Next, on the buffer layer 102, a metal material having a high melting point of 800 DEG C or more, such as molybdenum (Mo), molybdenum (Mo) alloy containing moly titanium (MoTi), copper (Cu) ), Titanium (Ti), tantalum (Ta), and tungsten (W) are deposited to form a gate metal layer 103 having a thickness of about 100 Å to 1000 Å. Resistance values of molybdenum (Mo) and molybdenum alloy (MoTi), copper (Cu) and copper alloy, titanium (Ti), tantalum (Ta) and tungsten (W) Experiments have shown that the degree of deformation is very small within a temperature range higher than the crystallization temperature and below the melting point, no voids are formed therein, and the degree of expansion and contraction is relatively small with respect to a rapid temperature change .

Thereafter, the first insulating layer 108 and the pure amorphous silicon layer 111 are formed by successively depositing or applying an insulating material and pure amorphous silicon on the gate metal layer 104 in sequence.

At this time, the pure amorphous silicon layer 111 is etched by being exposed to a dry etching process for forming an ohmic contact layer which is separated from a channel in the conventional case, and a part of the thickness is removed from the surface of the amorphous silicon layer 111 The first and second active layers of pure polysilicon ultimately realized through the pure amorphous silicon layer 111 (115a in FIG. 14C) are formed to a thickness of 1000 ANGSTROM or more. However, in the third modification of the first embodiment of the present invention, , And 115b are not exposed to the dry etching by the interlayer insulating film (122 of FIG. 14J) serving as the etch stopper, the problem that the thickness is thinned by the dry etching does not occur And is formed to have a thickness of 300 ANGSTROM to 1000 ANGSTROM which can serve as an active layer later.

The first insulating layer 108 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) or an organic insulating material such as benzocyclobutene (BCB) or photoacryl acryl).

Next, as shown in FIG. 11B, the pure amorphous silicon layer (not shown) is crystallized by performing a crystallization process to improve the mobility characteristics of the pure amorphous silicon layer (not shown) to form a pure polysilicon layer 112).

At this time, it is preferable that the crystallization process is a solid phase crystallization (SPC) or a crystallization process using a laser.

The solid phase crystallization (SPC) process may be performed by, for example, thermal crystallization through heat treatment in an atmosphere at 600 ° C. to 800 ° C., alternating magnetic (Magnetic) crystallization in a temperature atmosphere of 600 ° C. to 700 ° C. using an alternating- Field Crystallization) process, and it is preferable that the crystallization using a laser is, for example, ELA (Excimer Laser Annealing).

Next, as shown in FIG. 11C, a photoresist layer (not shown) is formed by applying a photoresist onto the pure polysilicon layer 112 crystallized by the crystallization process, and the photoresist layer (not shown) (Not shown) and a slit shape, or may further include a plurality of coating layers to control the amount of light passing therethrough so that the light transmittance is smaller than the transmissive area (not shown) Diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a semitransparent area (not shown) larger than a region (not shown).

Thereafter, by developing the exposed photoresist layer (not shown), the first and second gate electrodes (105a and 105b in FIG. 11k) are formed on the pure polysilicon 112 corresponding to the switching region SA and the driving region DA, (Corresponding to the portions of the first and second active layers (115a and 115b of FIG. 11k) of the later-formed pure polysilicon to be formed), the first photoresist having the first thickness A pattern 191a is formed and portions of the first and second active layers (115a and 115b in FIG. 11k) where the first and second gate electrodes (105a and 105b in FIG. 11k) A second photoresist pattern 191b having a second thickness that is thicker than the first thickness is formed.

Therefore, corresponding to the portion where the first and second gate electrodes (105a and 105b of FIG. 11k) are to be formed and overlapped with the first and second active layers (115a and 115b of FIG. 11k) The second photoresist pattern 191b is formed and the first and second active layers 115a and 115b of the portions where the first and second gate electrodes 105a and 105b of FIG. The first photoresist pattern 191a having the first thickness is formed and the entire region on the substrate 101 where the first and second gate electrodes 105a and 105b are not formed The photoresist layer (not shown) is removed to expose the pure polysilicon layer 112 (FIG. 11B).

 Next, the pure polysilicon layer (112 of FIG. 11C) and the first insulating layer (108 of FIG. 11C) exposed to the outside of the first and second photoresist patterns 191a and 191b are sequentially etched and removed, The gate insulating film 109 and the first and second pure polysilicon patterns 113a and 113b are sequentially formed in an island shape on the gate metal layer 104 in the switching region SA and the driving region DA.

As shown in FIG. 14D, ashing is performed on the substrate 101 on which the first and second pure water polysilicon patterns (113a and 113b in FIG. 11C) and the gate insulating film 109 are formed, The first and the second photoresist patterns 191a and 191b are formed outside the second photoresist pattern 191b in the switching region SA and the driving region DA by removing the first photoresist pattern 191a having the first thickness 2 exposed on one surface of the pure polysilicon pattern (113a and 113b in Fig. 14C). At this time, due to the ashing process, the second photoresist pattern 191b is also reduced in thickness but remains on the pure polysilicon pattern 113. [

Next, the first and second pure water polysilicon patterns 113a and 113b exposed to the outside of the second photoresist pattern 191b are removed by dry etching so that the second photoresist pattern 119b is removed, The first and second active layers 115a and 115b of the pure polysilicon are formed at the same time as the portions of the first and second active layers 115a and 115b of the pure polysilicon, Thereby exposing the rim portion of the tapered portion 109.

At this time, in some modifications of the first embodiment, a storage assist pattern (not shown) may be further formed on the storage area StgA using the same material as the first and second active layers 115a and 115b.

Thereafter, the second photoresist pattern 119b is removed by exposing the first and second active layers 115a and 115b.

Next, as shown in FIG. 11E, a metal material having a low resistance property, such as aluminum (Al), an aluminum alloy (AlNd (Al)), or the like is formed on the entire surface of the substrate 101 over the first and second active layers 115a and 115b. ), Copper (Cu), copper alloy, molybdenum (Mo), and chromium (Cr) are continuously deposited to form the first metal layer 118.

Then, a photoresist is coated on the first metal layer 118 and patterned to form a third photoresist pattern corresponding to the portion where the gate wiring (119 in FIG. 11K) and the gate assist pattern (120 in FIG. 193).

Next, as shown in FIG. 11F, the first metal layer (118 in FIG. 11E) exposed at the outside of the third photoresist pattern and the gate metal layer (104 in FIG. 11E) located under the third metal layer A first gate electrode 105a is formed in each of the switching regions SA and a second gate electrode 105b is formed in each of the driving regions DA, A gate wiring 119 is formed in contact with the first gate electrode 105a and a gate assist pattern 120 is formed in contact with the second gate electrode 105b. At this time, the gate assist pattern 120 extends to the storage region StgA to form the first storage electrode 121.

At this time, the gate line 119 and the gate assist pattern 120 may be formed of only one of the metal materials to form a single layer structure, or two or more different metal materials may be deposited to form a double layer or a triple layer Structure. For example, the multilayer structure may be made of an aluminum alloy (AlNd) / molybdenum (Mo), and in the case of a triple layer, molybdenum (Mo) / aluminum alloy (AlNd) / molybdenum (Mo). In the drawing, a gate wiring 119 and a gate assist pattern 120 of a single layer structure are shown for the sake of convenience.

Thereafter, the strip process is performed to remove the third photoresist pattern (193 in FIG. 11E).

Next, as shown in FIG. 11G, the first and second active layers 115a and 115b of the pure polysilicon, the gate wiring 119, and the gate assist pattern 120 are formed on the front surface 101 of the substrate, substances, for example inorganic second insulating layer (not shown) by applying one of the photo acryl or benzocyclobutene as a deposition or an organic insulating material, one of a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) as insulating material for .

Thereafter, a fourth photoresist pattern 194 is formed on the second insulating layer (not shown). The fourth photoresist pattern 194 includes first, second, third and fourth active contact holes 123a, 123b, 123c, and 123d exposing the first and second active layers 115a and 115b of the polysilicon, The portion to be formed and the second insulating layer (not shown) are removed so as to be formed in the region except for the portion where the opening h is to be formed.

Next, the second insulating layer (not shown) exposed to the outside of the fourth photoresist pattern 194 is removed through the etching process, so that in the switching region SA and the driving region DA, The first, second, third, and fourth active layers 115a and 115b, which expose the first and second active layers 115a and 115b of the polysilicon on both sides of the center of the first and second active layers 115a and 115b of silicon, An interlayer insulating film having active contact holes 123a, 123b, 123c and 123d and an opening h formed corresponding to the opening OA of each pixel region P to expose the buffer layer 102 122 are formed.

On the other hand, in the case of the first embodiment in which no opening is formed in the interlayer insulating film 122, the second insulating layer (not shown) is removed by forming the fourth photoresist pattern 194 on the opening h Can be prevented. That is, the fourth photoresist pattern 194 is selectively formed in correspondence with the portion where the opening h of each pixel region P is formed, whereby the second insulating layer (not shown) is removed to form the interlayer insulating film 122, The interlayer insulating film 122 may be formed such that the opening h is formed in the interlayer insulating film 122 or the interlayer insulating film 122 is not removed and thus the opening h is not formed.

On the other hand, the interlayer insulating film 122 formed to have the above-described shape has a shape corresponding to the central portion (channel region) of the first and second active layers 115a and 115b of the pure polysilicon, And the second active layers 115a and 115b to serve as an etch stopper, and serves as an insulating film corresponding to other regions. The portion of the first polysilicon layer in which the channel is formed in the first and second active layers 115a and 115b is electrically connected to the first, second, third, and fourth active contact holes 123a, 123b, 123c, and 123d are protected by the interlayer insulating film 122, the conventional active layer is not damaged by dry etching or the like. At this time, the portions where the first, second, third and fourth active contact holes 123a, 123b, 123c, and 123d are formed are not substantially formed, and therefore, no problem occurs.

Then, the strip process is performed to remove the fourth photoresist pattern 194.

11H, the substrate 101 having the interlayer insulating film 122 having the opening h and the first, second, third, and fourth active contact holes 123a, 123b, 123c, and 123d is formed. ) May be subjected to buffered oxide etchant (BOE) cleaning. This is because the surfaces of the first and second active layers 115a and 115b of the pure polysilicon exposed through the first, second, third and fourth active contact holes 123a, 123b, 123c and 123d are exposed to the air To completely remove the natural oxide film (not shown).

If the buffer layer 102 exposed through the opening OA is made of silicon oxide (SiO ₂ ) as in the third modification example of the first embodiment in the course of performing the BOE cleaning, And is thinner than other regions by being removed by reacting with the BOE. At this time, the thickness of the buffer layer 102 exposed through the opening h can be controlled by adjusting the BOE cleaning time.

Next, as shown in FIG. 11I, first, second, third and fourth active contact holes 123a, 123b, and 123c exposing the first and second active layers 115a and 115b of the pure polysilicon correspondingly, Doped amorphous silicon is deposited on the entire surface of the interlayer insulating film 122 serving as an etch stopper to the central portion of the first and second active layers 115a and 115b of the pure polysilicon to form an amorphous silicon film. A second impurity amorphous silicon layer (not shown) having a thickness of about 300 ANGSTROM is formed.

On the other hand, before the second impurity-amorphous silicon layer (not shown) is formed on the interlayer insulating film 122 having the first, second, third and fourth active contact holes 123a, 123b, 123c and 123d, The barrier layer (not shown) having a thickness of about 50 Å to 300 Å may be further formed by depositing pure amorphous silicon on the entire surface. The reason for forming the barrier layer (not shown) made of pure amorphous silicon is that the barrier layer (not shown) is formed between the active layer 115 of the pure polysilicon and the second impurity amorphous silicon layer (not shown) So as to improve the bonding force between these two layers (not shown). That is, the bonding strength of the pure polysilicon to the first and second active layers 115a and 115b is higher than that of the impurity amorphous silicon. However, the barrier layer (not shown) made of the pure amorphous silicon is not necessarily formed and can be omitted.

Next, a second metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy, chromium (Cr), molybdenum (Mo), etc. is formed on the second impurity- Or a molybdenum alloy including molybdenum (Mo) and molybdenum (MoTi) is continuously deposited to form a single layer or a second metal layer (not shown) having a multilayer structure or more. For convenience, the second metal layer (not shown) has a single-layer structure.

Next, the second metal layer (not shown) and a second impurity amorphous silicon layer (not shown) located below the second metal layer (not shown) are patterned by performing a masking process so as to form data on the boundary of each pixel region P on the interlayer insulating film 122 (Not shown) and a power supply wiring (not shown) are formed therebetween.

At the same time, first and second source and drain electrodes 133a and 136a are formed on the interlayer insulating layer 122 in the switching region SA. The first source and drain electrodes 133a and 136a are formed under the first source and drain electrodes 133a and 136a. Thereby forming a first ohmic contact layer 127a made of impurity amorphous silicon. At this time, the first ohmic contact layer 127a is brought into contact with the first active layer 115a of the pure polysilicon through the first and second active contact holes 123a and 123b, respectively.

In the driving region DA, second source and drain electrodes 133b and 136b are formed on the interlayer insulating layer 122 and the second source and drain electrodes 133b and 136b are spaced apart from each other. A second ohmic contact layer 127b made of an impurity amorphous silicon is formed. At this time, the second ohmic contact layer 127b is brought into contact with the second active layer 115b of the pure polysilicon through the third and fourth active contact holes 123c and 123d, respectively.

At this time, the second source electrode 133b is formed to extend to the storage region StgC to form the second storage electrode 137. In this case, the first storage electrode 121, the interlayer insulating layer 122, and the second storage electrode 137 sequentially stacked in the storage region StgC form a storage capacitor StgC.

On the other hand, when the barrier layer (not shown) made of pure amorphous silicon is formed, the first ohmic contact layer 127a spaced from the first active layer 115a and the first active layer 115a of the pure polysilicon, The first and second ohmic contact layers 127a and 127b are formed in the same planar shape as the first and second ohmic contact layers 127a and 127b between the second ohmic contact layer 127b and the second active layer 115b of the pure polysilicon, (Not shown) is formed.

The first source electrode 133a and the data line (not shown) formed in the switching region SA are formed to be connected to each other and are formed under the source and drain electrodes 133 and 136, respectively, The ohmic contact layer 127 has the same planar shape and planar shape as the source and drain electrodes 133 and 136, and is completely overlapped.

A dummy pattern (not shown) made of an impurity amorphous silicon is formed under the data line (not shown) by the process as described above.

On the other hand, in the case of the third modification of the first embodiment of the present invention, the data line (not shown), the first and second source and drain electrodes 133a, 136a, 133b and 136b, In the process of forming the ohmic contact layers 127a and 127b, the first and second active layers 115a and 115b of pure polysilicon in which channels are formed in the on state of the thin film transistors (DTr and STr in FIG. 14J) Since the interlayer insulating film 122 serving as an etch stopper is formed in correspondence with the central portion of the first and second source and drain electrodes 133a and 136a and 133b and 136b, The first and second active layers 115a and 115b of the pure polysilicon are not affected at all during the dry etching for patterning the second ohmic contact layers 127a and 127b.

Therefore, it can be seen that the surface damage of the active layer in the portion where the channel is formed by the dry etching process for patterning the ohmic contact layer, which is a problem mentioned in the related art, does not occur.

On the other hand, the first gate electrode 105a, the gate insulating film 109, the first active layer 115a of pure polysilicon, and the second gate electrode 105a, which are sequentially stacked in the switching region TrA, The first interlayer insulating film 122 and the first ohmic contact layer 127a of the impurity amorphous silicon and the first source and drain electrodes 133a and 136a constitute a switching thin film transistor STr, The second gate electrode 105b, the gate insulating film 109, the second active layer 115b of pure polysilicon, the interlayer insulating film 122 and the second ohmic contact layer of impurity amorphous silicon And the second source and drain electrodes 133b and 136b constitute a driving thin film transistor DTr.

When a barrier layer (not shown) is formed between each of the first and second ohmic contact layers 127a and 127b and the first and second active layers 115a and 115b of pure polysilicon together, (Not shown) to form the switching and driving thin film transistors STr and DTr.

Next, as shown in Fig. 11J, the first and second source and drain electrodes are formed on the substrate 101 on which the data line (not shown) and the power source line (not shown) and the switching and driving thin film transistors STr and DTr are formed. a drain electrode ((133a, 136a), ( 133b, 136b)) over the insulating material, for example oxidation of silicon (SiO ₂₎ or silicon nitride (SiNx), etc. of the inorganic insulating material is deposited, or benzocyclobutene (BCB) or photo acryl the a protective layer 140 is formed on the entire surface of the substrate 101 by applying an organic insulating material such as photo acryl.

Then, a mask process is performed on the protective layer 140 to form first and second drain contact holes 152a and 152b for exposing the first and second drain electrodes 136a and 136b, respectively, by patterning the mask layer At the same time, the gate contact hole 153 exposing the gate assist pattern 120 is formed by simultaneously patterning the passivation layer 140 and the interlayer insulating film 122.

At this time, the same step as forming the interlayer insulating film corresponding to the opening OA is performed. That is, a photoresist pattern for patterning the insulating material layer for forming the protective layer is formed on the opening OA The opening may or may not be selectively formed for the protective layer depending on whether the protective layer is formed correspondingly or not.

In the case of the first embodiment and the first modification thereof, the photoresist pattern is formed so as to correspond to the opening, so that the protection layer is formed in correspondence with the opening. In the second embodiment and the third modification of the first embodiment The photoresist pattern is not formed corresponding to the opening, so that the protective layer is removed and an opening is formed to expose the interlayer insulating film or the buffer layer on the lower portion.

11K, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the passivation layer 140, A conductive material layer (not shown) is formed by depositing a molybdenum alloy (Mo Alloy) such as moly titanium (MoTi), and the mask process is performed on the conductive material layer to form the second drain contact hole The first drain contact hole 152a and the gate contact hole 153 are formed on the passivation layer 140. The pixel electrode 170 is formed in contact with the second drain electrode 136b through the passivation layer 152b, The connection pattern 172 contacting the first drain electrode 136a and the gate assistant pattern 120 is formed through the first contact hole 120a and the second contact hole 120b to complete the array substrate 101 according to the third modification example of the first embodiment of the present invention .

12A to 12B are cross-sectional views illustrating steps of manufacturing a pixel region in an array substrate according to a second modification of the second embodiment of the present invention constituting an organic electroluminescent device. For convenience of explanation, a region where the switching thin film transistor ST is formed in the pixel region P is referred to as a switching region SA, a region where the driving thin film transistor DTr is formed is referred to as a driving region DA, Area is defined as a storage area (StgA).

The manufacturing method of the array substrate according to the second modification of the second embodiment of the present invention is substantially the same as the third modification of the first embodiment until the step of forming the data line, the power supply line and the first and second source and drain electrodes A portion where the data wiring, the power source wiring, the first and second source and drain electrodes are formed will be briefly described, and the data wiring, the power source wiring and the first and second source and drain The following description will focus on the steps after forming the electrodes. For the sake of convenience, the same reference numerals as in the first embodiment are assigned to the same components by adding 100 to them.

11A through 11I shown in the third modification of the first embodiment, the first and second source and drain electrodes ((( 233a, 236a, 233b, 236b), a data line (not shown), and a power line (not shown).

At this time, the portion where the second embodiment is different from the third modification of the first embodiment is in the step of forming the interlayer insulating film 222. [ That is, in the third modification of the first embodiment, in the step of forming the interlayer insulating film 222, the first and second active layers 215a and 215b of the pure polysilicon are exposed first, Only the opening h for exposing the active contact holes 223a, 223b, 223c and 223d and the buffer layer 202 is formed. In the case of the second modification of the second embodiment, in the step of patterning the interlayer insulating film 222, The gate contact holes 253 forming the first, second, third and fourth active contact holes 223a, 223b, 223c and 223d and the opening h and exposing the gate assist patterns 220 are formed Feature. The first, second, third and fourth active contact holes 223a, 223b, 223c and 223d and the opening h are formed in the interlayer insulating film 222 and the gate contact hole 253 is formed in the interlayer insulating film 222 The protective layer is not formed at a later stage due to the characteristics of the second embodiment of the present invention.

 Next, as shown in FIG. 12B, a conductive material (not shown) is formed on the first and second source and drain electrodes 233a, 236a, 233b, and 236b, data wiring The first and second source and drain electrodes 233a, 236a, 233b, and 236b may be formed by depositing a transparent conductive material such as indium tin oxide (ITO) or indium-zinc-oxide (IZO) 233a, 233b, and 236b) having a very high selectivity with respect to the first and second source and drain electrodes 233a, 236a, 233b, and 236b) To form a layer (not shown). For example, when the first and second source and drain electrodes 233a, 236a, 233b and 236b are made of aluminum (Al) or an aluminum alloy (AlNd), the etchant component is completely different during wet etching, The conductive material layer (not shown) may be formed of molybdenum (Mo) or moly titanium (MoTi), which may be etched.

Thereafter, a masking process is performed on the conductive material layer (not shown) and patterned to form a pixel electrode 270 directly contacting one end of the second drain electrode 236b for each pixel region P, At the same time, a connection pattern 272 is formed which is in contact with the gate assist pattern 220 through one end of the first drain electrode 236a and the gate contact hole 253, so that the second modification of the second embodiment of the present invention The array substrate 201 according to the example can be completed.

In the case of the second embodiment, the buffer layer 202 may be formed to have the above-described structure by not forming the opening h in the step of forming the interlayer insulating film 222. In the case of the first modification of the second embodiment, (SiNx), benzocyclobutene (BCB), and photo acryl, which are not silicon oxide (SiO ₂ ), are not affected by BOE cleaning, a buffer layer 202 of the same thickness is formed .

In the case of the second embodiment and the first and second modifications thereof, a protective layer is formed in comparison with the first embodiment and the first through third modifications thereof, and the first and second drain contact holes are formed in the protective layer It is possible to omit one masking process for reducing the number of masking processes in the first embodiment.

101: array substrate 105a, 105b: first and second gate electrodes
109: gate insulating film 115a, 115b: first and second active layers
119: gate wiring 120: gate assist pattern
121: first storage electrode 122: interlayer insulating film
123a, 123b, 123c, 123d: first, second, third and fourth active contact holes
127a, 127b: first and second ohmic contact layers
133a and 133b: first and second source electrodes
136a, 136b: first and second drain electrodes
137: second storage electrode 140: protective layer
152a and 152b: first and second drain contact holes
153: gate contact hole 170: pixel electrode
172: connection electrode DA: driving area
DTr: driving thin film transistor h: opening
OA: opening SA: switching area
StgA: Storage area StgC: Storage capacitor
STr: switching thin film transistor

Claims (14)

A buffer layer formed on a front surface of a substrate having a pixel region and a switching region, a driving region, and a storage region defined in the pixel region;
First and second gate electrodes formed in the switching region and the driving region on the buffer layer, the first and second gate electrodes being formed of a high melting point metal material in an island shape;
A gate insulating layer formed on the first and second gate electrodes to expose one end of each of the first and second gate electrodes in an island shape;
First and second active layers of pure polysilicon formed on the gate insulation layer in correspondence with the first and second gate electrodes, respectively, and exposing edges of the respective gate insulation layers;
A gate wiring formed in contact with the first gate electrode exposed to the outside of the gate insulating film and formed at a boundary of a pixel region and a gate auxiliary pattern formed in contact with the second gate electrode;
First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced from each other, An interlayer insulating film formed on the entire surface of the substrate, the interlayer insulating film serving as an etch stopper for the central portion of each layer;
A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A second ohmic contact layer of impurity amorphous silicon in contact with the second active layer through the third and fourth active contact holes;
A first source and drain electrode spaced apart from the first ohmic contact layer and spaced apart from the first ohmic contact layer, and a second source and drain electrode spaced apart from the second ohmic contact layer,
A data line formed on the interlayer insulating film and connected to the first source electrode at a boundary of the pixel region;
A protective layer formed on the data line with first and second drain contact holes exposing the first and second drain electrodes, respectively, and a gate contact hole exposing the gate assist pattern;
A pixel electrode formed in contact with the second drain electrode through the second drain contact hole in each pixel region on the protective layer;
A first drain contact hole and a gate contact hole, and a contact pattern formed in contact with the first drain electrode and the gate assist pattern through the first drain contact hole and the gate contact hole,
And an opening is formed in each of the pixel regions.
The method according to claim 1,
Wherein the opening has the interlayer insulating film removed.
3. The method of claim 2,
Wherein the opening has a buffer layer having a thickness smaller than that of the other region by removing a predetermined thickness of the upper surface of the buffer layer.
The method according to claim 1,
Wherein the opening has the protective layer and the interlayer insulating film removed.
5. The method of claim 4,
Wherein the opening has a buffer layer having a thickness smaller than that of the other region by removing a predetermined thickness of the upper surface of the buffer layer.
The method according to claim 1,
The opening may be formed by selectively removing only the interlayer insulating layer in each pixel region, removing a thickness of a part of the interlayer insulating layer and the buffer layer, removing the protective layer and the interlayer insulating layer, Wherein a portion of the upper surface of the buffer layer is removed to have a different opening structure.
A buffer layer formed on a front surface of a substrate having a pixel region and a switching region, a driving region, and a storage region defined in the pixel region;
First and second gate electrodes formed in the switching region and the driving region on the buffer layer, the first and second gate electrodes being formed of a high melting point metal material in an island shape;
A gate insulating layer formed on the first and second gate electrodes to expose one end of each of the first and second gate electrodes in an island shape;
First and second active layers of pure polysilicon formed on the gate insulation layer in correspondence with the first and second gate electrodes, respectively, and exposing edges of the respective gate insulation layers;
A gate wiring formed in contact with the first gate electrode exposed to the outside of the gate insulating film and formed at a boundary of a pixel region and a gate auxiliary pattern formed in contact with the second gate electrode;
First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced apart from each other, and gate contact An interlayer insulating layer formed on the entire surface of the substrate, the interlayer insulating layer serving as an etch stopper for the central portion of each of the first and second active layers;
A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A second ohmic contact layer of impurity amorphous silicon in contact with the second active layer through the third and fourth active contact holes;
A first source and drain electrode spaced apart from the first ohmic contact layer and spaced apart from the first ohmic contact layer, and a second source and drain electrode spaced apart from the second ohmic contact layer,
A data line formed on the interlayer insulating film and connected to the first source electrode at a boundary of the pixel region;
A pixel electrode formed in the pixel region in contact with the second drain electrode over the interlayer insulating film;
And a contact hole formed on the interlayer insulating film to contact the gate assist pattern through the first drain electrode and the gate contact hole,
And an opening is formed in each of the pixel regions.
8. The method of claim 7,
Wherein the opening has the interlayer insulating film removed.
9. The method of claim 8,
Wherein the opening has a buffer layer having a thickness smaller than that of the other region by removing a predetermined thickness of the upper surface of the buffer layer.
Forming a buffer layer on a front surface of a substrate having a pixel region having an opening and a switching region, a driving region, and a storage region defined in the pixel region;
Forming first and second gate electrodes with a high melting point metal material in an island form in the switching region and the driving region over the buffer layer;
Forming a gate insulating layer on the first and second gate electrodes to expose one end of each of the first and second gate electrodes, respectively, in an island shape;
Forming first and second active layers of pure polysilicon to expose respective edges of the gate insulating layer to the upper portion of the gate insulating layer in correspondence with the first and second gate electrodes;
Forming a gate interconnection in contact with the first gate electrode exposed to the outside of the gate insulating film and formed in a boundary of a pixel region and a gate assist pattern in contact with the second gate electrode;
First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced from each other, Forming an interlayer insulating film serving as an etch stopper at the center of each of the first and second active layers;
A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A first source formed in contact with the second active layer through the third and fourth active contact holes and spaced apart from the second ohmic contact layer of the impurity amorphous silicon and the first ohmic contact layer spaced apart from the first active contact layer, Drain electrode, a second source and drain electrode spaced apart from the second ohmic contact layer and spaced apart from each other, and a data line connected to the first source electrode at the boundary of the pixel region on the interlayer insulating layer Wow;
Forming a protective layer over the data line, the protective layer having first and second drain contact holes exposing the first and second drain electrodes, respectively, and a gate contact hole exposing the gate assist pattern;
A pixel electrode which is in contact with the second drain electrode through the second drain contact hole in each of the pixel regions on the protective layer, and a second drain electrode which is in contact with the first drain electrode and the gate auxiliary Forming a connection pattern simultaneously contacting the pattern
Wherein the substrate is a substrate.
11. The method of claim 10,
The step of forming the protective layer may include:
And forming a second opening exposing a buffer layer corresponding to the first opening formed in the interlayer insulating film in the pixel region.
Forming a buffer layer on a front surface of a substrate having a pixel region having an opening and a switching region, a driving region, and a storage region defined in the pixel region;
Forming first and second gate electrodes with a high melting point metal material in an island form in the switching region and the driving region over the buffer layer;
Forming a gate insulating layer on the first and second gate electrodes to expose one end of each of the first and second gate electrodes, respectively, in an island shape;
Forming first and second active layers of pure polysilicon to expose respective edges of the gate insulating layer to the upper portion of the gate insulating layer in correspondence with the first and second gate electrodes;
Forming a gate interconnection in contact with the first gate electrode exposed to the outside of the gate insulating film and formed in a boundary of a pixel region and a gate assist pattern in contact with the second gate electrode;
First and second active contact holes exposing the first active layer and spaced apart from each other, third and fourth active contact holes exposing the second active layer and spaced apart from each other, Forming an interlayer insulating film having a gate contact hole exposing the gate assistant pattern and serving as an etch stopper for the central portion of each of the first and second active layers;
A first ohmic contact layer of an impurity amorphous silicon which contacts and separates from the first active layer through the first and second active contact holes over the interlayer insulating film in the switching region; A first source formed in contact with the second active layer through the third and fourth active contact holes and spaced apart from the second ohmic contact layer of the impurity amorphous silicon and the first ohmic contact layer spaced apart from the first active contact layer, Drain electrode, a second source and drain electrode spaced apart from the second ohmic contact layer and spaced apart from each other, and a data line connected to the first source electrode at the boundary of the pixel region on the interlayer insulating layer Wow;
Forming a connection pattern in contact with the gate auxiliary pattern through the gate contact hole and simultaneously contacting the first drain electrode;
Wherein the substrate is a substrate.
13. The method according to any one of claims 10 to 12,
Before forming the first and second ohmic contact layers,
The first, second, third, and fourth active contacts are cleaned using BOE (Buffered Oxide Etchant) while the first and second active layers are exposed through the first, second, third, and fourth active contact holes, Removing the oxide film on the surfaces of the first and second active layers exposed through the hole and reducing the thickness of the upper surface of the buffer layer exposed through the first opening.
13. The method according to any one of claims 10 to 12,
Wherein the first and second openings are selectively formed in the respective pixel regions.

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