KR20110063022A - Array substrate and methode of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate and a method for manufacturing the same are provided to improve the productivity reducing the thickness of an active layer and shortening time required for a depositing operation. CONSTITUTION: A buffer layer(102) composed of an inorganic insulating material is formed on the front surface of an array substrate(101). A first gate electrode(107a) is formed on the buffer layer. A second gate electrode(107b) is expanded to a storage region. A gate insulating film(109) is formed on the first gate electrode and the second gate electrode. A first active layer(115a) and a second active layer(115b) are formed on the gate insulating film. An interlayer insulating film(122) includes active contact holes(123a to 123d). A first ohmic contact layer(127a) based on amorphous silicon is formed on the interlayer insulating film.

Description

Array substrate and method of manufacturing the same {Array substrate and methode of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate. In particular, a thin film transistor having an active layer having excellent mobility characteristics and suppressing the occurrence of surface damage of the active layer by dry etching is provided, and the drain electrode is used as the pixel electrode. An array substrate for an organic light emitting device, and a method of manufacturing the same.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of adjusting the on / off voltage of each pixel, has a resolution and a moving picture. Its outstanding implementation ability attracts the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each of the pixel areas on and off. In the light emitting device, a driving thin film transistor for driving an organic light emitting diode in addition to the switching thin film transistor is provided in each pixel region of the array substrate.

1 is a cross-sectional view of a pixel region including a driving thin film transistor in a conventional array substrate constituting an organic light emitting device. In this case, a region in which the driving thin film transistor is formed for convenience of description is defined as a driving region.

As illustrated, the gate electrode 15 is disposed in the driving region TrA in the plurality of pixel regions P, which are defined by crossing a plurality of gate lines (not shown) and data lines 33 on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 that are sequentially stacked may form a driving thin film transistor Tr. Although not shown in the drawing, the pixel region has the same shape as the driving thin film transistor Tr, is connected to the driving thin film transistor Tr, the gate line (not shown), and the data line 33 and is a switching thin film transistor. (Not shown) is being formed.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the driving region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the second thickness t2 of the portion where the spaced ohmic contact layer 26 is formed and the first thickness t1 of the exposed portion are differently formed by removing the ohmic contact layer 26. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, and the characteristic difference of the thin film transistor (Tr) occurs due to the thickness difference (t1 ≠ t2) of the active layer 22. have.

2 is a cross-sectional view illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

As shown, a pure amorphous silicon layer (not shown) is formed on the substrate 11, and an impurity amorphous silicon layer (not shown) and a metal layer (not shown) are sequentially formed on top of the substrate 11, and patterned thereon. A source drain pattern (not shown) is formed as a metal material, and an impurity amorphous silicon pattern (not shown) and an active layer (not shown) are formed below.

Subsequently, the source and drain electrodes 36 and 38 spaced apart from each other are formed by etching and removing a central portion of the source drain pattern. In this case, the impurity amorphous silicon pattern (not shown) is exposed between the source and drain electrodes 36 and 398.

Next, the impurity exposed between the source and drain electrodes 36 and 38 by dry etching the impurity amorphous silicon pattern (not shown) exposed in the separation region between the source and drain electrodes 36 and 38. By removing the amorphous silicon pattern (not shown), ohmic contact layers 26 spaced apart from each other are formed under the source and drain electrodes 36 and 38.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (not shown) exposed between the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (not shown) Even a portion of the active layer 22 disposed under the predetermined thickness etch occurs in a portion where the impurity amorphous silicon pattern (not shown) is removed. Therefore, a difference (t1 ≠ t2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (not shown) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22 to form a thin film transistor. This is to prevent this because the characteristics are degraded.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer (not shown) forming the active layer 22 is sufficiently thick in consideration of the thickness of the active layer 22 being etched and removed during the dry etching process for forming the ohmic contact layer 26. Since the deposition to have a thickness, the deposition time is increased, resulting in a decrease in productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier is low at 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the fabrication of the array substrate 51 including the thin film transistor Tr, which is used as 55), the n + region 55b including high concentration of impurities in both sides of the first region 55a in the semiconductor layer 55 made of polysilicon. Or p + region (not shown). Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

An object of the present invention is to provide an array substrate in which the active layer is not exposed to dry etching and thus no damage occurs on the surface thereof, thereby improving the characteristics of the thin film transistor.

Further, another object of the present invention is to provide an array substrate having a thin film transistor capable of improving a mobility characteristic while forming a semiconductor layer made of polysilicon and without requiring a doping process.

According to one or more embodiments of the present invention, an array substrate includes: a gate electrode formed in an island shape in a pixel area and the device area on a substrate in which the device area is defined within the pixel area; A gate insulating film having the same planar area as the gate electrode and completely overlapping the gate electrode; An active layer of pure polysilicon formed while exposing an edge of the gate insulating layer over the gate insulating layer; An interlayer insulating layer having first and second active contact holes spaced apart from each other and exposing the active layer and acting as an etch stopper for a central portion of each of the first and second active layers and formed of an inorganic insulating material on the entire surface of the substrate; ; An ohmic contact layer of impurity amorphous silicon contacting and spaced apart from the active layer through the first and second active contact holes in the device region, respectively, over the interlayer insulating layer; Source and drain electrodes having a triple layer structure formed on the first ohmic contact layer spaced apart from each other, the intermediate layer being made of a transparent conductive material; A data line formed on a boundary of the pixel region over the interlayer insulating layer, the data line having a same triple layer structure as that of the source and drain electrodes; A pixel electrode extending from the drain electrode of the triple layer structure in the pixel region over the interlayer insulating film; A protective layer having a gate contact hole exposing the gate electrode over the source and drain electrodes and a data line and a first opening exposing the pixel electrode; A gate wiring formed over the passivation layer to contact the gate electrode through the gate contact hole and crossing the data line to define the pixel area, wherein the pixel electrode corresponds to the first opening; The upper layer of the uppermost part of the triple layer forming is removed to form a double layer structure of the intermediate layer and the lower layer made of the transparent conductive material.

In this case, the lower layer and the upper layer is made of aluminum (Al) or silver (Ag), respectively, and the intermediate layer is characterized in that made of indium-tin-oxide (ITO).

In addition, the gate electrode is preferably made of impurity polysilicon having a thickness of 500 kPa to 1000 kPa, or a metal material having a melting point of 800 kC or more having a thickness of 100 kPa to 1000 kPa. The material is characterized in that any one of molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu).

An array substrate according to still another embodiment of the present invention may include a first region formed in an island form in a pixel region, the switching region and a driving region on a substrate in which a switching region, a driving region, and a storage region are defined in the pixel region; A second gate electrode; A gate insulating film formed on the first and second gate electrodes, respectively; First and second active layers of pure polysilicon formed on the gate insulating layer to expose an edge of the gate insulating layer corresponding to the first and second gate electrodes; First and second active contact holes exposing the first active layer and spaced apart from each other, and third and fourth active contact holes exposing the second active layer and spaced apart from each other; An interlayer insulating film serving as an etch stopper for the central portion of each layer and formed of an inorganic insulating material on the entire surface of the substrate; A first ohmic contact layer of impurity amorphous silicon in contact with and spaced apart from the first active layer through the first and second active contact holes, respectively, in the switching region and the interlayer insulating layer in the driving region, respectively. A second ohmic contact layer of impurity amorphous silicon in contact with and spaced apart from the second active layer through the third and fourth active contact holes; The first source and drain electrodes each having a three-layer structure made of a transparent conductive material, the intermediate layer being spaced apart from the spaced apart first ohmic contact layer, and the intermediate layer spaced apart from the spaced apart second ohmic contact layer. A second source and drain electrode having a triple layer structure made of a dielectric material; A pixel electrode extending from the second drain electrode of the triple layer structure in the pixel region over the interlayer insulating film; A data line connected to the first source electrode at a boundary of the pixel region on the interlayer insulating layer, the data line having a same triple layer structure as the first source electrode; A protective layer having a first gate contact hole exposing the first gate electrode over the data line and a first opening exposing the pixel electrode; A gate wiring formed over the passivation layer and contacting the first gate electrode through the first gate contact hole and crossing the data wiring to define the pixel region, wherein the pixel electrode corresponds to the first opening; The upper layer of the uppermost part of the triple layer forming the second drain electrode is removed to form a double layer structure of an intermediate layer and a lower layer made of the transparent conductive material.

The protective layer may include a second gate contact hole exposing the second gate electrode, a drain contact hole exposing the first drain electrode, and a power contact hole exposing the second source electrode. A connection pattern contacting the second gate electrode through the second gate contact hole and contacting the drain electrode through the drain contact hole; A power supply wiring in contact with the second source electrode is formed, and has a second opening exposing the pixel electrode over the gate wiring, and a bank having a flat surface is formed at a boundary between the device region and the pixel region. An organic emission layer is formed on the pixel electrode to correspond to the second opening of each pixel region surrounded by a bank. It is characterized by gwangcheung and the bank is formed above the first electrode to the substrate.

In addition, the lower and upper layers are made of aluminum (Al) or silver (Ag), respectively, and the intermediate layer is made of indium tin oxide (ITO).

In addition, the first and second gate electrodes are made of impurity polysilicon having a thickness of 500 kPa to 1000 kPa, or a metal material having a melting point of 800 kC or more having a thickness of 100 kPa to 1000 kPa, wherein the melting point is 800 The metal material having a temperature higher than or equal to about ℃ may be one of molybdenum (Mo), molybdenum alloy (MoTi), and copper (Cu).

 The substrate may further include a buffer layer formed under the first and second gate electrodes on the front surface of the substrate and formed of an inorganic insulating material.

In addition, the second gate electrode extends to the storage region to form a first storage electrode, and the second source electrode extends to the storage region to form a second storage electrode, thereby sequentially stacking the storage region. The first storage electrode, the gate insulating film, the interlayer insulating film, and the second storage electrode constitute a storage capacitor, and the second source electrode extends further from the storage area to be parallel to the data line to form the power electrode. Is characteristic.

In addition, a barrier pattern formed of pure amorphous silicon is formed under the first and second ohmic contact layers to have the same planar area as those ohmic contact layers and completely overlap.

A method of manufacturing an array substrate according to an exemplary embodiment of the present invention may include a first pixel in an island form in each of a switching region and a driving region on a substrate in which a switching region, a driving region, and a storage region are defined in a pixel region and the pixel region. And forming a second gate electrode, forming a gate insulating film having the same planar area over the first and second gate electrodes, and simultaneously exposing an edge of the gate insulating film over the gate insulating film, respectively. And forming a second active layer; First and second active contact holes exposing the first active layer and spaced apart from each other, and third and fourth active contact holes exposing the second active layer and spaced apart from each other; Forming an interlayer insulating film serving as an etch stopper for the central portion of each layer; A first ohmic contact layer of impurity amorphous silicon in contact with and spaced apart from the first active layer through the first and second active contact holes in the switching region, respectively, and in the driving region, above the interlayer insulating layer Contacting and spaced apart from the second active layer through the third and fourth active contact holes to form a second ohmic contact layer of impurity amorphous silicon, and spaced apart from the spaced apart first ohmic contact layer, respectively, A first source and drain electrode having a triple layer structure made of a transparent conductive material, and a second source and drain electrode having a triple layer structure formed of a transparent conductive material, the intermediate layer being spaced apart from the spaced apart second ohmic contact layer, respectively; And a first source electrode connected to a boundary of the pixel area over the interlayer insulating layer, and connected to the first source electrode. It forms the same data line 3 is formed having a layered structure, comprising the steps of: in the form of the second drain electrode extends in the pixel regions over the interlayer insulating film forming the pixel electrode of the three-layer structure; Forming a protective layer having a first gate contact hole exposing the first gate electrode and a first opening exposing the pixel electrode over the data line; Removing an upper layer of an uppermost layer of the triple layer structure pixel electrode exposed through the first opening to expose an intermediate layer made of a transparent conductive material to form a double layer pixel electrode; Forming a gate line on the passivation layer through the first gate contact hole and contacting the first gate electrode and crossing the data line to define the pixel area.

In this case, the forming of the protective layer having the first opening may include a second gate contact hole exposing the second gate electrode, a drain contact hole exposing the first drain electrode, and a power source exposing the second source electrode. And forming a contact hole, wherein forming the gate line is in contact with the second gate electrode through the second gate contact hole over the passivation layer and in contact with the drain electrode through the drain contact hole. Forming a power supply wiring spaced apart from the connection pattern to be parallel to the gate wiring and contacting the second source electrode through the power contact hole, and exposing the pixel electrode over the gate wiring; Forming a bank having a flat surface at a boundary between the device region and the pixel region; Forming an organic emission layer over the pixel electrode of the double layer structure exposed to the second opening of each pixel region surrounded by the bank; And forming a first electrode on an entire surface of the substrate above the organic light emitting layer and the bank.

In addition, the lower layer and the upper layer of the triple layer is made of aluminum (Al) or silver (Ag), respectively, and the intermediate layer is characterized in that made of indium-tin-oxide (ITO).

The forming of the first and second gate electrodes and the gate insulating layer in an island form in the switching region and the first and second active layers of pure polysilicon exposing the edges of the gate insulating layer may be performed on the substrate. Forming a buffer layer; Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; By patterning the pure polysilicon layer, the first inorganic insulating layer and the impurity polysilicon layer, the first gate electrode, the gate insulating layer, and the first pure polysilicon pattern are formed to have the same planar shape in the switching region and completely overlap with each other. Forming the second gate electrode, the gate insulating layer, and a second pure polysilicon pattern in the driving region, the second gate electrode, the gate insulating layer, and the second pure polysilicon pattern in a completely overlapped form; Patterning the first and second pure polysilicon patterns to form first and second active layers exposing edges of the gate insulating layer, respectively.

In this case, the solid phase crystallization process is preferably an alternating magnetic field crystallization using a crystallization or alternating magnetic field crystallization (AMFC) device through a heat treatment of 600 ℃ to 800 ℃.

In addition, the first and second active layer of the pure polysilicon is characterized in that it is formed to have a thickness of about 300 kPa to 1000 kPa.

In the array substrate according to the present invention, the array substrate according to the present invention has an effect of preventing the active layer from being exposed to dry etching so that surface damage does not occur and thus the thin film transistor characteristics are deteriorated.

In addition, since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

An array substrate according to the present invention has a mobility compared to an array substrate having a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the properties tens to several hundred times.

Since the active layer of polysilicon is used as a semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In addition, since the drain electrode itself is used as the pixel electrode, the mask process for forming the pixel electrode is omitted, thereby simplifying the manufacturing process.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

4 is a cross-sectional view of one pixel area including a switching and driving thin film transistor in an array substrate according to an embodiment of the present invention constituting an organic light emitting display device. In this case, for convenience of description, the area in which the driving thin film transistor is formed is defined as the driving area DA and the area in which the switching thin film transistor is formed as the switching area SA. In this case, although the portion where the pixel electrode is formed has a larger area than the driving area DA and the switching area SA, in the drawing, the pixel electrode corresponding to the opening is relatively formed due to the limitation of expression in writing. It is smaller than the switching area SA and the driving area DA.

As illustrated, a buffer layer 102 made of an inorganic insulating material is formed on the entire surface of the array substrate 101 according to the embodiment of the present invention.

A first gate electrode 107a made of impurity polysilicon or a first metal material is formed in the switching area SA on the buffer layer 102, and the impurity polysilicon or first metal material is formed in the driving area DA. A second gate electrode 107b is formed. In this case, the second gate electrode 107b extends to the storage region StgA to form the first storage electrode 106.

In addition, a gate insulating film 109 is formed as an inorganic insulating material on the first and second gate electrodes 107a and 107b of the impurity polysilicon, and the switching region is formed on the gate insulating film 109. The first active layer 115a and the second active layer 115b of pure polysilicon are formed corresponding to each of the first and second gate electrodes 107a and 107b positioned in the SA and the driving area DA. have.

In addition, the first and second active layers may be disposed on both sides of the first and second active layers 115a and 115b on both sides of the first and second active layers 115a and 115b, respectively. An interlayer insulating film 122 having first, second, third and fourth active contact holes 123a, 123b, 123c, and 123d exposing 115a and 115b is formed.

In addition, the impurity amorphous silicon is in contact with the first active layer 115a and spaced apart from each other through the first and second active contact holes 123a and 123b on the interlayer insulating layer 122. The first ohmic contact layer 127a is formed, and the first source and drain electrodes 133a and 136a are spaced apart from each other and have a triple layer structure.

In addition, the impurity amorphous silicon is in contact with the second active layer 115b and spaced apart from each other through the third and fourth active contact holes 123c and 123d on the interlayer insulating layer 122. The second ohmic contact layer 127b is formed, and the second source and drain electrodes 133b and 136b spaced apart from each other and having a triple layer structure are formed thereon. In this case, the second source electrode 133b extends to the storage region StgA to form the second storage electrode 138, and further extends in one direction to form a power electrode (not shown).

In this case, the first gate electrode 107a of polysilicon sequentially stacked on the switching area SA, the gate insulating layer 109, the first active layer 115a of pure amorphous silicon, and the first and second active contact holes The first source and drain electrodes 133a and 136a spaced apart from the first ohmic contact layer 127a of impurity amorphous silicon spaced apart from each other and the interlayer insulating film 122 having the surfaces 123a and 123b are switched thin film transistors STr. To achieve.

In addition, the second gate electrode 107b of polysilicon sequentially stacked in the driving region DA, the gate insulating layer 109, the second active layer 115b of pure amorphous silicon, and the third and fourth active contact holes. The interlayer insulating film 122 having 123c and 123d and the second ohmic contact layer 127b of impurity amorphous silicon spaced apart from each other and the second source and drain electrodes 133b and 136b spaced apart from each other are driven thin film transistor DTr. To achieve.

Although not shown in the drawings, a data line (not shown) having a triple layer structure is formed on the interlayer insulating layer 122 to be connected to the first source electrode 133a of the switching thin film transistor STr and extend in one direction. .

At this time, the most characteristic of the exemplary embodiment of the present invention is that the second drain electrode 136b of the driving thin film transistor DTr extends to the pixel electrode 160 in each pixel region P. Is fulfilling. In this case, the pixel electrode 160 has a double layer structure of a lower layer 129 and an intermediate layer 131 from which the uppermost layer 132 of the triplet layer constituting the second drain electrode 136b is removed.

Meanwhile, the lower layer 129 has excellent reflection efficiency in the first source and drain electrodes 133a and 136a, the second source and drain electrodes 133b and 136b, and the data line (not shown) having a triple layer structure. The metal layer is made of silver (Ag) or aluminum (Al), and the intermediate layer 131 is made of indium tin oxide (ITO), a transparent conductive material having a relatively high work function value, and the upper layer 132 ) Is made of silver (Ag) or aluminum (Al), which is a low-resistance metal material.

In addition, the pixel electrode 160 formed by extending the second drain electrode 136b is a metal material having excellent reflection efficiency by removing the upper layer 132 located at the top of the triple layer structure of the second drain electrode 136b. A lower layer 129 made of phosphorus silver (Ag) or aluminum (Al), and an intermediate layer 131 made of indium tin oxide (ITO), a transparent conductive material having a relatively high work function value thereon. It is characterized by losing. In this case, the pixel electrode 160 serves as an anode electrode because the intermediate layer 131 in contact with the organic light emitting layer 170 formed on the pixel electrode 160 is made of a material having a relatively large work function value.

Meanwhile, an extension 106 of the second gate electrode and an extension 138 of the second source electrode overlapping the gate insulating layer 109 and the interlayer insulating layer 122 with each other in the storage region StgA. The storage capacitor StgC is formed.

In addition, a protective layer 140 made of an inorganic insulating material is formed on the switching and driving thin film transistors STr and DTr having the above-described configuration. In this case, the passivation layer 140 may include a first gate contact hole 142a exposing the first gate electrode 107a of the switching thin film transistor STr and a second gate electrode 107b of the driving thin film transistor DTr. ) Is provided with a second gate contact hole 142b for exposing the second gate contact hole 142b, and a first drain contact hole 152 for exposing the first drain electrode 136a is provided, and in the pixel region P An opening oa exposing the pixel electrode 160 is provided.

Next, the protective layer 140 contacts the first gate electrode 107a through the first gate contact hole 142a and intersects the pixel area P by crossing the data line (not shown). A gate wiring 145 is defined, and contacts the second gate electrode 107b through the second gate contact hole 142b and the second drain electrode through the first drain contact hole 152. The connection pattern 147 which contacts 136b is formed.

In this case, although not shown in the figure, a power line (not shown) is formed to be spaced apart from the gate line 145. In this case, the power line (not shown) is connected to the power electrode (not shown) through the power contact hole (not shown).

In addition, a bank 165 having an opening oA for exposing the pixel electrode 160 of each pixel region P is formed on the gate line 145 to complete the array substrate 101 according to the present invention. It is becoming.

Although not shown, an organic emission layer 170 is formed on the pixel electrode 160 in an area surrounded by the bank 165 in each pixel area P. The organic emission layer 170 and the organic emission layer 170 are formed on the pixel electrode 160. The first electrode 175 is formed on the front surface of the substrate to cover the bank 165 and has a low work function value, for example, aluminum (Al) or aluminum alloy (AlNd). The first electrode 175 is formed of a material having a relatively low work function, and thus serves as a cathode. In this case, the pixel electrode 160, the organic emission layer 170, and the first electrode 175 sequentially stacked in each pixel region P form an organic light emitting diode OLED.

In the array substrate 101 according to the present invention having the above-described configuration, the interlayer insulating film 122 serves as an etch stopper for the central portions of the first and second active layers 115a and 115b in which the channel regions are formed. Since the change in thickness does not occur, the characteristics of the thin film transistor due to the change in the thickness of the channel region of the active layer can be prevented.

In addition, since the active layer of polysilicon is used as a semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, new equipment for the doping process is not required. Therefore, the initial investment cost can be reduced. Since the pixel electrode 160 itself is used as the pixel electrode 160, it is not necessary to form a separate pixel electrode by different layers from the second drain electrode 136b, thereby simplifying the manufacturing process by eliminating at least one mask process. It has the advantage to do it.

Hereinafter, a method of manufacturing an array substrate according to an exemplary embodiment of the present invention will be described.

5A to 5K are cross-sectional views illustrating manufacturing steps of one pixel region including a switching and driving region of an array substrate according to the present invention. In this case, for convenience of description, the area in which the driving thin film transistor is formed is defined as the driving area DA and the area in which the switching thin film transistor is formed as the switching area SA. In this case, although the portion where the pixel electrode is formed has a larger area than the driving area DA and the switching area SA, in the drawing, the pixel electrode corresponding to the opening is relatively formed due to the limitation of expression in writing. It is smaller than the switching area SA and the driving area DA.

First, as illustrated in FIG. 5A, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on a transparent insulating substrate 101, for example, a glass substrate. To form. This is a feature of the present invention proceeds to a solid phase crystallization (Solid Phase Crystallization (SPC)) process in a later process, such a solid phase crystallization (SPC) process requires a high temperature of 600 ℃ to 800 ℃, in this case the substrate ( By exposure of 101 to a high temperature atmosphere, alkali ions can be eluted from the surface of the substrate 101, thereby degrading the properties of the component made of polysilicon. Therefore, in order to prevent such a problem, the buffer layer 102 is formed.

Next, the first impurity amorphous silicon layer 105 is sequentially deposited on the buffer layer 102 by sequentially depositing impurity amorphous silicon, an inorganic insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiNx), or pure amorphous silicon. And the first inorganic insulating layer 108 and the pure amorphous silicon layer 111 are formed.

In this case, the pure amorphous silicon layer 111 is etched by exposing the portion where the channel is formed to dry etching proceeding to form an ohmic contact layer spaced apart from each other in the related art so that some thickness is removed from the surface thereof. Although formed to a thickness of 1000 Å or more, in the embodiment of the present invention, the channels of the first and second active layers (115a and 115b of FIG. 5K) of pure polysilicon finally implemented through the pure amorphous silicon layer 111 Since the formed region is not exposed to dry etching by the interlayer insulating film (122 of FIG. 5K) serving as an etch stopper, a problem such that its thickness becomes thin due to the dry etching does not occur, thereby serving as an active layer later. It can be formed to a thickness of 300 kPa to 1000 kPa.

On the other hand, as a modification, the melting point in place of the first impurity amorphous silicon layer 105 on the buffer layer 102, that is, the temperature during the solid phase crystallization process, that is, during the crystallization process of the metal material higher than 800 ℃ Metal materials that do not generate voids therein (hereinafter referred to as gate metal materials), for example, molybdenum (Mo), molybdenum alloy (MoTi), and copper (Cu) may be formed to have a thickness of about 100 kV to 1000 kPa. It may be.

The metal material having a melting point lower than 800 ° C., which is a temperature required for the crystallization process, may be melted during the solid phase crystallization process to cause the metal material to diffuse into the first inorganic insulating layer 108 disposed thereon. In addition, some metal materials among the metal materials having a melting point higher than 800 ° C. are not melted, but a large number of voids are generated therein, thereby preventing the driving failure of the thin film transistor due to the difference in the self resistance of each pixel region P. This causes problems such as increasing the deterioration rate of the thin film transistor due to the voids generated therein and reducing the life of the thin film transistor.

On the other hand, although it is not a characteristic of the metal material itself, even if the metal material has a melting point of 800 ° C. or more and no voids are formed therein, it should not cause deformation of the substrate itself by contraction-expansion when exposed to a high temperature environment. Since the internal resistance per area should be at least equal to that of impurity polysilicon, the thickness of the gate metal layer (not shown) made of the gate metal material having a high melting point is preferably 100 kPa to 1000 kPa, more preferably 100 kPa to 500 kPa.

In view of the specific conditions under which such a metal material can be used as the gate electrode, in the modification of the embodiment of the present invention, the gate metal layer has a melting point higher than the solid phase crystallization process temperature, for example, so that the gate metal layer does not cause the aforementioned problem. Molybdenum alloys such as molybdenum (Mo), molybdenum (MoTi), and copper (Cu) is formed of any one or two or more materials having a thickness of 100 kPa to 1000 kPa.

Since the subsequent process for manufacturing the array substrate according to this modification proceeds in the same manner as the embodiment will be described based on the embodiment.

Next, as shown in FIG. 5B, the pure amorphous silicon layer (111 of FIG. 5B) is subjected to a solid phase crystallization (SPC) process to improve the mobility characteristics of the pure amorphous silicon layer (111 of FIG. 5B). The crystallization is performed to form the pure polysilicon layer 112.

In this case, the solid phase crystallization (SPC) process is an example of alternating magnetic field crystallization in a temperature atmosphere of 600 ℃ to 700 ℃ using a thermal crystallization (Thermal Crystallization) or alternating magnetic field crystallization apparatus in an atmosphere of 600 ℃ to 800 ℃ ( Alternating Magnetic Field Crystallization) process is preferable.

Meanwhile, as the solid phase crystallization (SPC) process proceeds, not only the pure amorphous silicon layer 112 but also the first impurity amorphous silicon layer (105 in FIG. 5A) is crystallized to form the impurity polysilicon layer 106. In a variant, the gate metal layer is not crystallized and only the pure amorphous silicon layer (111 in FIG. 5A) is crystallized.

Next, as shown in FIG. 5C, the switching region is patterned by patterning the pure polysilicon layer (112 in FIG. 5B), the first inorganic insulating layer (108 in FIG. 5B), and the impurity polysilicon layer (106 in FIG. 5B). The first gate electrode 107a, the gate insulating layer 109, and the first pure polysilicon pattern 113a are formed in the SA in the same planar area, completely overlapped, and sequentially stacked, and at the same time, the driving region DA is formed. And a second gate electrode 107b, a gate insulating layer 109, and a second pure polysilicon pattern 113b having the same planar area, completely overlapping, and sequentially stacked in the storage region StgA. In this case, a portion of the second gate electrode 107b formed in the storage region StgA forms the first storage electrode 104.

Next, as shown in FIG. 5D, the first and second pure polysilicon patterns (113a and 113b of FIG. 5C) are patterned to form pure polysilicon at the center of the gate insulating layer 109 of the switching area SA. The first active layer 115a is formed, and the second active layer 115b of pure polysilicon is formed in the center of the gate insulating layer 109 of the driving region DA. In this case, the second pure polysilicon pattern (113b of FIG. 5C) is removed from the storage area StgA.

Next, as shown in FIG. 5E, one of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the first and second active layers 115a and 115b of the pure polysilicon. Forming an interlayer insulating film 122 and patterning the first interlayer insulating film 122 to form both sides of the first and second active layers 115a and 115b of the pure polysilicon. First, second, third and fourth active contact holes 123a, 123b, 123c and 123d exposing each of the layers 115a and 115b are formed. In this case, the interlayer insulating layer 122 may correspond to a central portion of each of the first and second active layers 115a and 115b of the pure polysilicon, respectively, of the first and second active layers 115a and 115b of the pure polysilicon. It serves as an etch stopper for covering the film, and serves as an insulating layer in correspondence with other areas.

In this case, the interlayer insulating layer 122 formed on the first and second active layers 115a and 115b of the pure polysilicon may have the first, second, third and fourth active contact holes 123a, 123b, 123c, and 123d. In addition to the gate insulating layer 109 exposed to the outside of the first and second active layers 115a and 115b of the polysilicon, respectively, the first and second holes 124a and 124b are formed. It is characteristic to make it possible. As such, exposing the gate insulating layer 109 positioned on each of the first and second gate electrodes 107a and 107b to the interlayer insulating layer 122 will be described later. This is to shorten the formation time of the first and second gate contact holes (142a and 142b of FIG. 5K) for exposing 107b).

However, the first and second holes 124a and 124b may further include the interlayer insulating layer 122 and the gate insulating layer together with the protective layer (140 in FIG. 5K) in the later patterning of the protective layer (140 in FIG. 5K). The first and second gate contact holes (142a and 142b of FIG. 5K) may be omitted when all of the first and second gate electrodes 107a and 107b are directly removed by removing all the parts 109.

Next, as shown in FIG. 5F, an impurity amorphous silicon is deposited on the entire surface of the interlayer insulating film 122 including the first, second, third and fourth active contact holes 123a, 123b, 123c, and 123d to form a second layer. An impurity amorphous silicon layer (not shown) is formed.

Continuously forming a first metal layer (not shown) by depositing a first metal material having excellent reflectivity, for example, aluminum (Al) or silver (Ag), on the second impurity amorphous silicon layer (not shown), and the continuous Thereby depositing a transparent conductive material having a relatively large work function value, for example indium tin oxide (ITO), over the first metal layer (not shown) to form a transparent conductive material layer (not shown). The first metal material is deposited on the to form a second metal layer (not shown).

Subsequently, the second metal layer (not shown), the transparent conductive material layer (not shown), the first metal layer (not shown), and the second impurity amorphous silicon layer (not shown) are patterned on the interlayer insulating film 122. A data line (not shown) having a triple layer structure extending in one direction and having a lower layer 129 made of a first metal material, an intermediate layer 131 made of a transparent conductive material, and an upper layer 132 made of a first metal material is formed. .

At the same time, in the switching area SA, the first ohmic contact layer contacting the first active layer 115a through the first and second active contact holes 123a and 123b and spaced apart from each other made of impurity amorphous silicon. 127a and first source and drain electrodes 133a and 136a having a triple layer 129, 131, and 132 in contact with the first ohmic contact layer 127a spaced from each other and spaced apart from each other.

In the driving area DA, a second ohmic contact made of impurity amorphous silicon is formed in contact with the second active layer 115b through the third and fourth active contact holes 123c and 123d, respectively, and spaced apart from each other. The second source and drain electrodes 133b and 136b of the third layer 129, 131, and 132 which are spaced apart from each other in contact with the layer 127b and the second ohmic contact layer 127b spaced apart from each other. To form. In this case, the second source electrode 133b having a triple layer 129, 131, and 132 structure extends to the storage region StgA to form the second storage electrode 138, and at the same time, the data line (not shown). It extends in parallel to form a power electrode (not shown).

In this case, a dummy pattern (not shown) made of the impurity amorphous silicon may be formed under the data line (not shown) and the power electrode (not shown) having the triple layer 129, 131, and 132 structures.

In the pixel region P, the second drain electrode 136b having the triple layer 129, 131, and 132 structure formed in the driving region DA is extended so that the second drain electrode 136b is extended at this stage. The pixel electrode 159 having the triple layer 129, 131, and 132 structure is formed as shown in FIG. In this case, the first dummy pattern 128 made of impurity amorphous silicon is formed under the pixel electrode 159 of the triple layer 129, 131, and 132 structure.

Although not shown in the drawings, the first and second ohmic contact layers 127a and 127b and the first, second, third and fourth active contact holes 123a, 123b, 123c and 123d are exposed. A barrier pattern (not shown) of pure amorphous silicon having the same shape as each of the first and second ohmic contact layers 127a and 127b and completely overlapping the first and second active layers 115a and 115b is further formed. May be

A barrier pattern (not shown) of pure amorphous silicon may first form a second pure amorphous silicon layer (not shown) before forming the second impurity amorphous silicon layer (not shown) on the interlayer insulating film 122, This may be formed by patterning the second impurity amorphous silicon layer (not shown), the second metal layer (not shown), the transparent conductive material layer (not shown), and the first metal layer (not shown). In this case, a second dummy pattern of pure amorphous silicon (not shown) is disposed below the first dummy pattern 128 of impurity amorphous silicon even under the pixel electrode 159 having the triple layer 129, 131, and 132 structures. Will be formed.

On the other hand, the reason for forming a barrier pattern (not shown) made of pure amorphous silicon, the bonding strength of the pure polysilicon with the first and second active layer (115a, 115b) is better than pure amorphous silicon than impurity amorphous silicon. Therefore, the barrier pattern (not shown) is interposed between the first and second active layers 115a and 115b of the pure polysilicon and the impurity amorphous silicon layer (not shown). 115b), not shown) to improve the bonding strength and further lower the contact resistance.

Meanwhile, before forming the first and second ohmic contact layers 127a and 127b or the barrier layer of pure amorphous silicon (not shown) on the interlayer insulating layer 122, a cleaning process using a buffered oxide etchant (BOE) is used. (Hereinafter referred to as BOE washing) is preferably performed first.

The first and second active layers 115a and 115b of the pure polysilicon have a temperature of 600 ° C. to 800 ° C. with no material layer formed on the pure amorphous silicon layer (111 in FIG. 5A) before solid phase crystallization. An oxide film (not shown) is naturally formed on the surface by exposure to the solid state crystallization (SPC) process having an atmosphere, and the oxide film (not shown) is formed of the first and second active layers 115a and 115b of pure polysilicon. And the first and second ohmic contact layers 127a and 127b or the first and second active layers 115a and 115b of pure polysilicon. The barrier pattern (not shown) acts as an element to reduce the ohmic characteristics.

Accordingly, oxide films (not shown) on surfaces of the first and second active layers 115a and 115b of the pure polysilicon exposed through the first, second, third and fourth active contact holes 123a, 123b, 123c, and 123d are exposed. ) Is preferably removed, and the BOE cleaning is performed before forming the first and second ohmic contact layers 127a and 127b or the barrier layer (not shown).

Meanwhile, in the exemplary embodiment of the present invention, the data line (not shown), the first and second source and drain electrodes 133a, 133b, and 136a and 136b and the first and second ohmic contact layers 127a are provided. 127b), an interlayer insulating film 122 serving as an etch stopper is formed to correspond to the central portions of the first and second active layers 115a and 115b of the pure polysilicon forming the channel region. Etching for patterning the first and second ohmic contact layers 127a and 127b, for example, the first and second active layers 115a and 115b of the pure polysilicon are not affected at all during dry etching. .

Therefore, it can be seen that the surface damage of the active layer due to the dry etching process, which is a problem mentioned in the related art, does not occur.

In this case, the first gate electrode 107a of the impurity polysilicon, the gate insulating layer 109, the first active layer 115a of pure polysilicon, and the interlayer insulating layer 122, the first ohmic contact layer 127a of impurity amorphous silicon, and the first source and drain electrodes 133a and 136a, which are spaced apart from each other, form a switching thin film transistor STr.

In addition, the second gate electrode 107b of the impurity polysilicon, the gate insulating film 109, the second active layer 115b of pure polysilicon, and the interlayer insulating film sequentially stacked in the driving region DA 122, the second ohmic contact layer 127b of impurity amorphous silicon, and the second source and drain electrodes 133b and 136b, which are spaced apart from each other, form a driving thin film transistor DTr, and the storage region StgA. ), The first storage electrode 104, the gate insulating film 109, the interlayer insulating film 122, and the second storage electrode 138, which are sequentially stacked, form a storage capacitor StgC.

Next, as shown in FIG. 5G, the first and second source and drain electrodes 133a, 133b, and 136a and 136b having the triple layer 129, 131, and 132 structures and the data wiring (not shown). And an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), are deposited on the second storage electrode 138 to form a protective layer 140, and a mask process is performed to form the protective layer ( 140 and the interlayer insulating film 122 and the gate insulating film 109 located thereunder to pattern the first and second gates outside the first and second active layers 115a and 115b of the pure polysilicon, respectively. First and second gate contact holes 142a and 142b exposing the electrodes 107a and 107b, respectively, are formed.

In addition, a power electrode contact hole (not shown) exposing the power electrode (not shown) and a first drain contact hole 143 exposing the first drain electrode 136a are formed.

In this case, the first and second gate contact holes 142a and 142b exposing the first and second gate electrodes 107a and 107b, respectively, are respectively formed in the interlayer insulating film 122 and the gate insulating film 109. And when the second holes 124a and 124b are formed, the second holes 124a and 124b are formed to be positioned inside the first and second holes 124a and 124b. In this case, corresponding to the first and second holes 124a and 124b, the entire thickness of the interlayer insulating film 122 and a portion of the gate insulating film 109 are already removed, so that the protective layer 140 and the Since only a part of the gate insulating layer 109 needs to be removed, the dry etching time for forming the first and second gate contact holes 142a and 142b is relatively reduced.

At the same time, in each pixel area P, the protective layer 140 is dry-etched and removed to form a first opening oA1 exposing the pixel electrode 159 of FIG. 5F having a triple layer structure.

In this process, as described above, the first and second gate contact holes 142a and 142b, the power electrode contact hole (not shown), and the first drain contact hole 143 are formed.

Next, as shown in FIG. 5H, by wet etching the upper layer (132 of FIG. 5G) of the pixel electrode 160 made of the first metal material exposed through the first opening oa1. The intermediate layer 131 made of a transparent conductive material is exposed. As a result, the pixel electrode 160 having the double layer structure of the lower layer 129 and the intermediate layer 131 is formed in the pixel region P to correspond to the portion exposed through the first opening oa1.

In this case, the first and second gate electrodes exposed through the first and second gate contact holes 142a and 142b in the process of removing the upper layer 132 of FIG. 5G from the pixel electrode 159 of FIG. 5G. 107a 107b) are not typically affected.

In the embodiment and the modification of the present invention, the first and second gate electrodes 107a and 107b are made of impurity polysilicon or made of molybdenum (Mo), molybdenum alloy (MoTi), or copper. Accordingly, the etching solution for removing the upper layer (132 of FIG. 5G) of the pixel electrode (159 of FIG. 5G) made of aluminum (Al) or silver (Ag) may be formed of the impurity polysilicon, molybdenum (Mo), molybdenum alloy (MoTi) or the like. Since it does not react with copper (Cu) at all, problems such as loss of the first and second gate electrodes 107a and 107b do not occur.

Next, as shown in FIG. 5I, the portions exposed to the first openings oa of each pixel region P are formed on the substrate 101 on which the pixel electrodes 160 having the double layer 129 and 131 structures are formed. A second metal material having low resistance on the pixel electrode 160 and the protective layer 140, for example, any one of aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, and chromium (Cr) Or depositing two or more to form a third metal layer (not shown).

Subsequently, the third metal layer (not shown) is patterned by performing a mask process so as to contact the first gate electrode 107a through the first gate contact hole 142a and cross the data line (not shown). A gate line 145 defining each pixel area P is formed, and simultaneously the first drain electrode 136a and the first through the second gate contact hole 142b and the first drain contact hole 143. The connection pattern 147 in contact with the two gate electrodes 107b is formed. In this case, the gate wiring 145 and the connection pattern 147 are illustrated as a single layer for convenience.

In addition, although not shown in the drawing, a power wiring (not shown) is formed through the power electrode contact hole (not shown) to be in contact with the power electrode (not shown) and to be spaced apart from the gate wiring 145. .

Next, as illustrated in FIG. 5J, an organic insulating material, for example, benzocyclobutene (BCB) or photo acryl, is coated on the gate wiring 145 and the connection pattern 147 to form an organic insulating layer ( And forming a bank 165 having a second opening oa exposing the pixel electrode 160 having the double layer 129 and 131 structure in each pixel region P. .

Next, as shown in FIG. 5K, an organic light emitting layer 170 that sequentially emits red, green, and blue light is formed in the second opening oA in each pixel region P exposed between the banks 165. The first electrode 175 is formed by depositing a metal material having a low work function value, for example, aluminum (Al) or aluminum alloy (AlNd), over the bank 165 and the organic emission layer 170. The array substrate 101 for an organic light emitting device according to the embodiment and the modification of the present invention is completed.

Meanwhile, the pixel electrode 160, the organic light emitting layer 170, and the first electrode 175 sequentially stacked in each pixel area P form an organic light emitting diode OLED. In this case, the pixel electrode 160 serves as an anode electrode, and the first electrode 175 serves as a cathode electrode.

In the organic light emitting device (not shown) having the array substrate 101 having the above-described configuration, the organic light emitting layer is formed because the lower layer 129 of the pixel electrodes 160 having the double layer 129 and 131 functions as a reflecting plate. By reflecting all the light generated from the 170 to the upper side where the first electrode 175 is located to improve the luminous efficiency, the pixel electrode 160 is formed by extending the second drain electrode 136b Compared to a conventional array substrate in which a pixel electrode connected to the second drain electrode and the contact hole is formed on a layer other than the layer on which the second drain electrode is formed, the mask process can be simplified by omitting one mask process. to be.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.

2 is a cross-sectional view illustrating a process of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;

3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor having a polysilicon semiconductor layer in the related art.

4 is a cross-sectional view of one pixel area including a switching and driving thin film transistor in an array substrate according to an exemplary embodiment of the present invention constituting an organic light emitting display device.

5A through 5K are cross-sectional views of manufacturing steps for one pixel region including a switching and driving region of an array substrate according to the present invention.

<Description of Symbols for Main Parts of Drawings>

101: array substrate 102: buffer layer

104: first storage electrode 107a, 107b: first and second gate electrodes

109: gate insulating film 115a, 115b: first and second active layers

122: interlayer insulating film

123a, 123b, 123c, 123d: first, second, third and fourth active contact holes

124a: 124b: first and second holes

127a and 127b: first and second ohmic contact layers 129 and lower layers

131: middle layer 132: upper layer

133a, 133b: first and second source electrodes

136a, 136b: first and second drain electrodes

138: second storage electrode 140: protective layer

142a and 142b: first and second gate contact holes

145: gate wiring 147: connection pattern

152: first drain contact hole 160: pixel electrode

165: bank 170: organic light emitting layer

175: first electrode

DTr: Driving Thin Film Transistor DA: Driving Area

OLED: organic light emitting diode SA: switching area

StgA: Storage Area StgC: Storage Capacitor

STr: Switching Thin Film Transistor

Claims (18)

A gate electrode formed in an island form in the pixel region and the element region on the substrate in which the element region is defined within the pixel region; A gate insulating film having the same planar area as the gate electrode and completely overlapping the gate electrode; An active layer of pure polysilicon formed while exposing an edge of the gate insulating layer over the gate insulating layer; An interlayer insulating layer having first and second active contact holes spaced apart from each other and exposing the active layer and acting as an etch stopper for a central portion of each of the first and second active layers and formed of an inorganic insulating material on the entire surface of the substrate; ; An ohmic contact layer of impurity amorphous silicon contacting and spaced apart from the active layer through the first and second active contact holes in the device region, respectively, over the interlayer insulating layer; Source and drain electrodes having a triple layer structure formed on the first ohmic contact layer spaced apart from each other, the intermediate layer being made of a transparent conductive material; A data line formed on a boundary of the pixel region over the interlayer insulating layer, the data line having a same triple layer structure as that of the source and drain electrodes; A pixel electrode extending from the drain electrode of the triple layer structure in the pixel region over the interlayer insulating film; A protective layer having a gate contact hole exposing the gate electrode over the source and drain electrodes and a data line and a first opening exposing the pixel electrode; A gate wiring formed on the protective layer to contact the gate electrode through the gate contact hole and to define the pixel area crossing the data wiring; And the pixel electrode forming a double layer structure of an intermediate layer and a lower layer of the transparent conductive material by removing an upper layer of an uppermost layer of the triple layer forming the drain electrode corresponding to the first opening. The method of claim 1, The lower layer and the upper layer are each made of aluminum (Al) or silver (Ag), The intermediate layer is an array substrate, characterized in that consisting of indium-tin-oxide (ITO). The method of claim 1, The gate electrode is made of an impurity polysilicon having a thickness of 500 kPa to 1000 kPa, or an array substrate, characterized in that the melting point having a thickness of 100 kPa to 1000 kPa made of a metal material of 800 ℃ or more. The method of claim 3, wherein The metal material having the melting point of 800 ℃ or more is an array substrate, characterized in that any one of molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu). First and second gate electrodes formed in an island shape in the switching region and the driving region on the pixel region and the substrate in which the switching region, the driving region, and the storage region are defined; A gate insulating film formed on the first and second gate electrodes, respectively; First and second active layers of pure polysilicon formed on the gate insulating layer to expose an edge of the gate insulating layer corresponding to the first and second gate electrodes; First and second active contact holes exposing the first active layer and spaced apart from each other, and third and fourth active contact holes exposing the second active layer and spaced apart from each other; An interlayer insulating film serving as an etch stopper for the central portion of each layer and formed of an inorganic insulating material on the entire surface of the substrate;  A first ohmic contact layer of impurity amorphous silicon in contact with and spaced apart from the first active layer through the first and second active contact holes in the switching region, respectively, and in the driving region, above the interlayer insulating layer A second ohmic contact layer of impurity amorphous silicon in contact with and spaced apart from the second active layer through the third and fourth active contact holes; The first source and drain electrodes each having a three-layer structure made of a transparent conductive material, the intermediate layer being spaced apart from the spaced apart first ohmic contact layer, and the intermediate layer spaced apart from the spaced apart second ohmic contact layer. A second source and drain electrode having a triple layer structure made of a dielectric material; A pixel electrode extending from the second drain electrode of the triple layer structure in the pixel region over the interlayer insulating film; A data line connected to the first source electrode at a boundary of the pixel region on the interlayer insulating layer, the data line having a same triple layer structure as the first source electrode; A protective layer having a first gate contact hole exposing the first gate electrode over the data line and a first opening exposing the pixel electrode; A gate line formed in contact with the first gate electrode through the first gate contact hole and crossing the data line to define the pixel area over the passivation layer; Wherein the pixel electrode forms a double layer structure of an intermediate layer and a lower layer formed of the transparent conductive material by removing an upper layer of an uppermost layer of the triple layer forming the second drain electrode corresponding to the first opening. . The method of claim 5, A second gate contact hole exposing the second gate electrode, a drain contact hole exposing the first drain electrode and a power contact hole exposing the second source electrode are formed in the passivation layer, A connection pattern contacting the second gate electrode through the second gate contact hole and contacting the drain electrode through the drain contact hole, and the power contact hole spaced apart from the gate wiring; Through the power source wiring is formed in contact with the second source electrode, A bank having a second opening that exposes the pixel electrode over the gate line and having a flat surface at a boundary between the device region and the pixel region; An organic emission layer is formed on the pixel electrode to correspond to the second opening of each pixel region surrounded by the bank;  And an electrode formed on the entire surface of the organic light emitting layer and the bank. The method of claim 6, The lower layer and the upper layer are each made of aluminum (Al) or silver (Ag), The intermediate layer is an array substrate, characterized in that consisting of indium-tin-oxide (ITO). The method of claim 6, And the first and second gate electrodes are made of impurity polysilicon having a thickness of 500 kPa to 1000 kPa, or a metal material having a melting point of 800 ° C. or more having a thickness of 100 kPa to 1000 kPa. The method of claim 8, The metal material having the melting point of 800 ℃ or more is an array substrate, characterized in that any one of molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu). The method of claim 6,  An array substrate on a front surface of the substrate, the buffer layer being formed under the first and second gate electrodes and made of an inorganic insulating material. The method of claim 6,  The second gate electrode extends to the storage region to form a first storage electrode. The second source electrode extends to the storage area to form a second storage electrode, so that the first storage electrode, the gate insulating film, the interlayer insulating film, and the second storage electrode are sequentially stacked in the storage area. Made up,  And the second source electrode extends further from the storage area to be parallel to the data line to form the power electrode. The method of claim 6,  And a barrier pattern formed of pure amorphous silicon in the form of completely overlapping with the same planar area as those of the ohmic contact layers and below the first and second ohmic contact layers. First and second gate electrodes are formed in an island form in each of the switching region and the driving region on the pixel region and the substrate in which the switching region, the driving region, and the storage region are defined. Forming a gate insulating film having the same planar area over the gate electrode, and simultaneously forming first and second active layers of pure polysilicon in such a manner as to expose an edge of the gate insulating film over the gate insulating film, respectively; First and second active contact holes exposing the first active layer and spaced apart from each other, and third and fourth active contact holes exposing the second active layer and spaced apart from each other; Forming an interlayer insulating film serving as an etch stopper for the central portion of each layer;  A first ohmic contact layer of impurity amorphous silicon in contact with and spaced apart from the first active layer through the first and second active contact holes in the switching region, respectively, and in the driving region, above the interlayer insulating layer Contacting and spaced apart from the second active layer through the third and fourth active contact holes to form a second ohmic contact layer of impurity amorphous silicon, and spaced apart from the spaced apart first ohmic contact layer, respectively, A first source and drain electrode having a triple layer structure made of a transparent conductive material, and a second source and drain electrode having a triple layer structure formed of a transparent conductive material, the intermediate layer being spaced apart from the spaced apart second ohmic contact layer, respectively; And a first source electrode connected to a boundary of the pixel area over the interlayer insulating layer, and connected to the first source electrode. It forms the same data line 3 is formed having a layered structure, comprising the steps of: in the form of the second drain electrode extends in the pixel regions over the interlayer insulating film forming the pixel electrode of the three-layer structure; Forming a protective layer having a first gate contact hole exposing the first gate electrode and a first opening exposing the pixel electrode over the data line; Removing an upper layer of an uppermost layer of the triple layer structure pixel electrode exposed through the first opening to expose an intermediate layer made of a transparent conductive material to form a double layer pixel electrode; Forming a gate line on the passivation layer to contact the first gate electrode through the first gate contact hole and cross the data line to define the pixel area; Method of manufacturing an array substrate comprising a. The method of claim 13, The forming of the protective layer having the first opening may include a second gate contact hole exposing the second gate electrode, a drain contact hole exposing the first drain electrode, and a power contact hole exposing the second source electrode. Forming a step; The forming of the gate wiring may include a connection pattern contacting the second gate electrode through the second gate contact hole and contacting the drain electrode through the drain contact hole on the passivation layer. Forming power wirings spaced apart from each other to be in contact with the second source electrode through the power contact hole; Forming a bank having a second opening over the gate wiring to expose the pixel electrode, the bank having a flat surface at a boundary between the device region and the pixel region; Forming an organic emission layer over the pixel electrode of the double layer structure exposed to the second opening of each pixel region surrounded by the bank;  Forming a first electrode on an entire surface of the substrate above the organic light emitting layer and the bank; Method of manufacturing an array substrate comprising a. The method of claim 13, The lower and upper layers of the triple layer are made of aluminum (Al) or silver (Ag), respectively. The intermediate layer is a method of manufacturing an array substrate, characterized in that consisting of indium-tin-oxide (ITO). The method of claim 13, Forming first and second gate electrodes and a gate insulating layer in an island shape in the switching region, and first and second active layers of pure polysilicon exposing edge portions of the gate insulating layer; Forming a buffer layer on the substrate; Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; By patterning the pure polysilicon layer, the first inorganic insulating layer and the impurity polysilicon layer, the first gate electrode, the gate insulating layer, and the first pure polysilicon pattern are formed to have the same planar shape in the switching region and completely overlap with each other. Forming the second gate electrode, the gate insulating layer, and a second pure polysilicon pattern in the driving region, the second gate electrode, the gate insulating layer, and the second pure polysilicon pattern in a completely overlapped form; Patterning the first and second pure polysilicon patterns to form first and second active layers exposing edges of the gate insulating layer, respectively; Method of manufacturing an array substrate comprising a. The method of claim 16, The solid phase crystallization process is characterized in that the crystallization or alternating magnetic field crystallization using alternating magnetic field crystallization (AMFC) device through a heat treatment of 600 ℃ to 800 ℃. The method of claim 13, And the first and second active layers of the pure polysilicon are formed to have a thickness of about 300 kPa to about 1000 kPa.

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