CN108305879A - Thin-film transistor array base-plate and production method and display device - Google Patents
Thin-film transistor array base-plate and production method and display device Download PDFInfo
- Publication number
- CN108305879A CN108305879A CN201810095754.8A CN201810095754A CN108305879A CN 108305879 A CN108305879 A CN 108305879A CN 201810095754 A CN201810095754 A CN 201810095754A CN 108305879 A CN108305879 A CN 108305879A
- Authority
- CN
- China
- Prior art keywords
- contact hole
- layer
- electrode
- thin
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 4
- 238000003851 corona treatment Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 133
- 239000011241 protective layer Substances 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of production methods of thin-film transistor array base-plate, including step：Scan line and grid are made on substrate, cover the first insulating layer, active layer is made on the first insulating layer, data line is made on active layer, source electrode and drain electrode, cover second insulating layer, and the first contact hole is made at source electrode or drain electrode, cover flatness layer, and the second contact hole is made at the first contact hole, depositing first conductive layer, first etching is not taken to first conductive layer, metal electrode is made on first conductive layer, the first conductive layer is performed etching again, and expose source electrode or drain electrode, cover third insulating layer, and third contact hole is made at the second contact hole, pixel electrode is made on third insulating layer, the pixel electrode is connect with source electrode or drain contact.The present invention also provides a kind of thin-film transistor array base-plates being made by the above method and a kind of display device including the thin-film transistor array base-plate.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin-film transistor array base-plate and production method and
Display device.
Background technology
With the development of science and technology, LCD (Liquid Crystal Display, liquid crystal display) and OLED
(Organic Light-Emitting Diode, Organic Light Emitting Diode) display has replaced bulky CRT monitor, increasingly
Go deep into daily life, especially LCD display, since it is with small, light-weight, thickness is thin, low in energy consumption, nothing
The features such as radiation, is developed by leaps and bounds in recent years, occupies leading position in the current flat panel display market, each
It is widely used on the product of the big-and-middle small size of kind, almost covers the primary electron product of current information-intensive society, such as
LCD TV, computer, mobile phone, PDA, GPS, car-mounted display, Projection Display, video camera, digital camera, electronic watch, calculator,
The multiple fields such as electronic instrument and meter, public display and illusory display.
In image display process, each liquid crystal pixel point is all by being integrated in TFT thin film transistor (TFT)s in LCD panel
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) in array substrate drives, then coordinates the peripheral driver electric
Road realizes that image is shown；Active matrix drive type OLED (Active Matrix Organic Light Emission
Display, abbreviation AMOLED) in display by corresponding OLED pixel in the TFT driving oled panels in TFT substrate, then match
Peripheral drive circuit is closed, realizes that image is shown.In aforementioned display device, TFT is the luminous switch of control, is to realize that LCD is shown
Device and the large-sized key of OLED display, are directly related to the developing direction of Performance Monitor.
Currently, in existing TFT production methods, it may appear that the protective layer under flatness layer occurs to weaken and flatness layer covers not
Good problem.To solve the weakening of flatness layer lower protective layer, it is readily apparent that and changes the methods of protective layer film quality and film thickness, but is this
Method cannot be fully solved the weakening of protective layer.The mode of flatness layer lower protective layer elder generation trepanning is usually taken in the prior art,
It can solve the problems, such as that protective layer weakens, but source/drain can expose.Since public electrode resistance is larger, it will usually with common electrical
A metal electrode extremely in parallel, when being performed etching to the metal electrode, can lead to the source/drain exposed for reducing its resistance
Missing, while also resulting in flatness layer cracking.So as to cause display by put do not work be changed into it is a little bad.
Invention content
In order to overcome shortcoming and defect existing in the prior art, the purpose of the present invention is to provide a kind of thin film transistor (TFT)s
The production method of array substrate had both solved the problems, such as that flatness layer lower protective layer weakened, had caused when also solving post-order process trepanning
The problem of source electrode or drain electrode missing and flatness layer are cracked in hole.
The purpose of the invention is achieved by the following technical solution：
The present invention provides a kind of production method of thin-film transistor array base-plate, which includes the following steps：
The first metal layer is made on substrate, which includes scan line and grid；
Deposition covers the first insulating layer of the first metal layer over the substrate；
Active layer is made on first insulating layer；
Second metal layer is made on first insulating layer, which includes data line, source electrode and drain electrode, the source
Pole and the drain electrode are connect with the active layer respectively；
Deposition covers the second insulating layer of the second metal layer on first insulating layer, and is made in the second insulating layer
Make the first contact hole；
Flatness layer is deposited in the second insulating layer, and makes the second contact hole in the flatness layer, and wherein this second connects
Contact hole is corresponding with position at first contact hole；
The depositing first conductive layer on the flatness layer, first conductive layer cover second contact hole, first not to this
One conductive layer performs etching；
Metal electrode is made on first conductive layer；
It is etched after forming the metal electrode, then to first conductive layer, which forms after the etching
Public electrode；
The third insulating layer of deposition the covering metal electrode and the public electrode, and make third in the third insulating layer
Contact hole, wherein the third contact hole are corresponding with the second contact hole site；
Deposit second conductive layer and be made as pixel electrode on the third insulating layer, wherein the pixel electrode insert this
Three contact holes are connect in second contact hole and with the source electrode of the second metal layer or drain contact.
Further, which is less than first contact hole, and the flatness layer is made to insert in first contact hole simultaneously
Cover the surrounding side wall of first contact hole.
Further, the hole heart of first contact hole, second contact hole and the third contact hole is on same center line.
Further, the region on the public electrode other than pixel openings area is all covered with the metal electrode.
Further, the metal electrode directly with the common electrode contact.
Further, further include that corona treatment is carried out to the second insulating layer before forming the flatness layer.
The present invention also provides a kind of thin-film transistor array base-plates, and the thin-film transistor array base-plate is using as described above
Production method makes to be formed.
Further, which is less than first contact hole, and the flatness layer is made to insert in first contact hole simultaneously
Cover the surrounding side wall of first contact hole.
Further, the region on the public electrode other than pixel openings area is all covered with the metal electrode.
The present invention also provides a kind of display device, which includes thin-film transistor array base-plate as described above.
Advantageous effect of the present invention：In the production method of the thin-film transistor array base-plate, deposition first is led on flatness layer
Electric layer, the first conductive layer cover the second contact hole, and first etching technics is not taken to the first conductive layer；Then in the first conductive layer
Upper deposition third metallic film is etched making metal electrode to the third metallic film, to the third metallic film into
When row etching makes metal electrode, since the first conductive layer filling is covered in the second contact hole, the first conductive layer can be utilized
As etching barrier layer, protect the source electrode in the second contact hole or drain electrode, solve source electrode in the prior art or drain electrode missing and
The problem of flatness layer is cracked；It is etched after forming metal electrode, then to the first conductive layer.
Description of the drawings
Fig. 1 a to Fig. 1 j are the manufacturing process schematic diagrames of thin-film transistor array base-plate in first embodiment of the invention；
Fig. 2 is the flow chart of the production method of thin-film transistor array base-plate in first embodiment of the invention；
Fig. 3 is the flow chart of the production method of thin-film transistor array base-plate in second embodiment of the invention.
Specific implementation mode
It is of the invention to reach the technological means and effect that predetermined goal of the invention is taken further to illustrate, below in conjunction with
Attached drawing and preferred embodiment, to specific implementation mode, structure, feature and its effect of the present invention, detailed description are as follows：
First embodiment
Fig. 1 j are the partial schematic diagram of thin-film transistor array base-plate in first embodiment of the invention, provided in this embodiment
Thin-film transistor array base-plate includes substrate 101, is formed on substrate 101 the first metal layer, covering are on the first metal layer
The first insulating layer 103, be formed on the first insulating layer 103 active layer 104, be formed on the first insulating layer 103 second
Metal layer, the second insulating layer 107 being covered in second metal layer, the flatness layer 108 being formed in second insulating layer 107, shape
At on flatness layer 108 public electrode 111, be formed on public electrode 111 third metal layer, be covered in public electrode
111 and the third insulating layer 112 on third metal layer and the pixel electrode 113 that is formed on third insulating layer 112.
Further, the first metal layer includes scan line and grid 102, and second metal layer includes data line, 106 and of source electrode
Drain electrode 105, third metal layer include metal electrode 110, and the first insulating layer 103 is gate insulating layer, and second insulating layer 107 is to cover
The protective layer of lid source electrode 106 and drain electrode 105, insulation of the third insulating layer 112 between public electrode 111 and pixel electrode 113
Layer, and the first contact hole 201 is equipped in second insulating layer 107, the second contact hole 202, third insulation are equipped in flatness layer 108
Third contact hole 203 is equipped in layer 112.Metal electrode 110 is formed on public electrode 111 and directly with public electrode 111 and connects
It touches, to reduce the resistance of public electrode 111 and increase the electric conductivity of public electrode 111.Pixel electrode 113 passes through the second contact hole
202 and third contact hole 203 and source electrode 106 or drain electrode 105 connect, in the present embodiment, pixel electrode 113 passes through second and contacts
Hole 202 and third contact hole 203 are connect with drain electrode 105.
Second contact hole 202 is less than the first contact hole 201, so that flatness layer 108 is inserted in the first contact hole 201 and covers the
The surrounding side wall of one contact hole 201, to enable flatness layer 108 to cover all second insulating layer 107 (i.e. protective layer), solution
The problem of certainly protective layer weakens；
Further, the hole heart of the first contact hole 201, the second contact hole 202 and third contact hole 203 is located at same center
On line.
Region on the public electrode 111 other than pixel openings area is all covered with the metal electrode 110.
Substrate 101 can be glass substrate or plastic base.First insulating layer 103, second insulating layer 107 and third insulation
Layer 112 is, for example, silica (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiONx).Scan line, grid 102, data line,
Source electrode 106, drain electrode 105 and metal electrode 110 are, for example, the metal or alloy such as Cr, W, Ti, Ta, Mo, Al, Cu, or more
The laminated film that layer metallic film is constituted.Active layer 104 can be non-crystalline silicon (a-Si), polysilicon (p-Si), metal oxide
Semiconductor (such as IGZO, ITZO).Public electrode 111 is electrically conducting transparent material such as tin indium oxide with pixel electrode 113
(ITO), indium zinc oxide (IZO) or aluminum zinc oxide etc..
The present invention also provides a kind of display devices, including above-mentioned thin-film transistor array base-plate, as display device
Refer to the prior art for other structures, and which is not described herein again.
The present invention also provides the production method of above-mentioned thin-film transistor array base-plate, Fig. 1 a to Fig. 1 j are the thin of the present embodiment
The manufacturing process schematic diagram of film transistor array substrate, Fig. 2 are the manufacturing process of the thin-film transistor array base-plate of the present embodiment
Flow chart, which includes the following steps：
The step S1 for please referring to Fig. 1 a and Fig. 2, deposits the first metallic film on substrate 101, uses the first mask pair
First metallic film is etched making the first metal layer, which includes scan line and grid 102, grid 102
Connect with scan line or grid 102 be scan line a part；
The step S2 for please referring to Fig. 1 b and Fig. 2, deposition covers the first insulating layer of the first metal layer on the substrate 101
103, i.e. the first insulating layer 103 covers scan line and grid 102, and active layer film is deposited on the first insulating layer 103, uses the
Two masks, which are etched 104 film of active layer, makes active layer 104, and active layer 104 can be non-crystalline silicon (a-Si), more
Crystal silicon (p-Si), metal-oxide semiconductor (MOS) (such as IGZO, ITZO)；
The step S3 for please referring to Fig. 1 c and Fig. 2 is deposited the second metallic film on the first insulating layer 103, is covered using third
Masterplate is etched making second metal layer to second metallic film, the second metal layer include source electrode 106 and drain electrode 105,
Source electrode 106 and drain electrode 105 are connect with active layer 104 respectively；
The step S4 for please referring to Fig. 1 d and Fig. 2, the second of the deposition covering second metal layer is exhausted on the first insulating layer 103
Edge layer 107 is etched the second insulating layer 107 using the 4th mask, to make first in the second insulating layer 107
Contact hole 201, the first contact hole 201 and corresponding, first contact hole in the present embodiment of one of source electrode 106, drain electrode 105
201 is corresponding with drain electrode 105, protective layer of the second insulating layer 107 as source electrode 106 and drain electrode 105；
The step S5 for please referring to Fig. 1 e and Fig. 2 deposits flatness layer 108 in second insulating layer 107, uses the 5th mask
The flatness layer 108 is exposed and is developed, to make the second contact hole 202 in the flatness layer 108, second contact hole
202 is corresponding with 201 position of the first contact hole, and the hole heart of second contact hole 202 and first contact hole 201 is positioned at same
On center line, which is less than first contact hole 201, and the flatness layer 108 is made to insert first contact hole 201
In and cover the surrounding side wall of first contact hole 201, to enable the flatness layer 108 to cover all the second insulating layer
107 (i.e. protective layers) solve the problems, such as that protective layer weakens；After forming second contact hole 202, source electrode 106 or drain electrode 105
(being drain electrode 105 in the present embodiment) is exposed by second contact hole 202；
The step S6 for please referring to Fig. 1 f and Fig. 2, the depositing first conductive layer 109 on flatness layer 108, the first conductive layer 109
Second contact hole 202 is covered, etching technics is not first taken to first conductive layer 109 so that be located at second contact hole
Source electrode 106 or drain electrode 105 (being drain electrode 105 in the present embodiment) in 202 are covered by the first conductive layer 109 without exposure；
The step S7 for please referring to Fig. 1 g and Fig. 2 deposits third metallic film on the first conductive layer 109, is covered using the 6th
Masterplate is etched the third metallic film and makes metal electrode 110.Making gold is being etched to the third metallic film
Belong to electrode 110 when, since the first conductive layer 109 is filled in the second contact hole 202, can using the first conductive layer 109 as
Etching barrier layer is protected the source electrode 106 in the second contact hole 202 or drain electrode 105 (being drain electrode 105 in the present embodiment), is solved
The problem of source electrode 106 or 105 missing of drain electrode and flatness layer 108 are cracked in the prior art；
The step S8 for please referring to Fig. 1 h and Fig. 2, after forming metal electrode 110, reuse the 7th mask to this first
Conductive layer 109 is etched, which forms public electrode 111 after the etching, and makes the source electrode of second metal layer
106 or drain electrode 105 (in the present embodiment for drain electrode 105) exposed by the second contact hole 202, the metal electrode 110 is public with this
The fitting contact of electrode 111 can reduce the resistance of public electrode 111 and increase the electric conductivity of public electrode 111, to reduce signal
The delay of transmission reduces and shows mura problems；
The region on the public electrode 111 other than pixel openings area is all covered with this in one of the embodiments,
Metal electrode 110；
Please refer to the step S9 of Fig. 1 i and Fig. 2, the third insulating layer of overlying deposited metal electrode 110 and public electrode 111
112, and the third insulating layer 112 is performed etching using the 7th mask and is connect with making third in the third insulating layer 112
Contact hole 203, the third contact hole 203 is corresponding with 202 position of the second contact hole, first contact hole 201, second contact
The hole heart of hole 202 and the third contact hole 203 is located on same center line, the third contact hole 203 and second contact hole 202
Can be identical with size, so that the source electrode 106 of second metal layer or drain electrode 105 (being drain electrode 105 in the present embodiment) is contacted by second
Hole 202 and third contact hole 203 expose；
The step S10 of Fig. 1 j and Fig. 2 are please referred to, the deposit second conductive layer on third insulating layer 112 uses the 8th mask
Version, which performs etching second conductive layer, makes pixel electrode 113, which inserts the second contact hole 202 and third
Source electrode 106 in contact hole 203 and with second metal layer or drain electrode 105 connect, in the present embodiment pixel electrode 113 with
Drain electrode 105 connects.
Second embodiment
Fig. 1 a to Fig. 1 j are the manufacturing process schematic diagram of thin-film transistor array base-plate in first embodiment of the invention, Fig. 3
It is the flow chart of the production method of thin-film transistor array base-plate in second embodiment of the invention, such as Fig. 1 a to Fig. 1 j and Fig. 3 institutes
Show, the production method and the basic phase of above-mentioned first embodiment of the thin-film transistor array base-plate that second embodiment of the invention provides
Together, the difference is that：In the present embodiment, formed second insulating layer 107 step S4 and flatness layer 108 step S5 it
Between, further include step S41, corona treatment is carried out to the second insulating layer 107, then re-forms flatness layer 108, Gai Dengli
Daughter includes nitrogen gas plasma, and advantage is that solve the problems, such as that flatness layer 108 covers bad.
Term " formation " mentioned in the present invention and " making " should include broadly understanding, such as object may be used
The mode commonly used in the art such as physical vapor deposition, chemical vapor deposition, molecular beam epitaxy carries out.Due to the side of these formation films
There are many kinds of formulas, therefore no longer specifically notes to form the process of each film herein, because these methods are not this
Where the inventive point of invention.
The above described is only a preferred embodiment of the present invention, restriction in any form not is done to the present invention, though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention, any technology people for being familiar with this profession
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification,
For the equivalent embodiment of equivalent variations, as long as be without departing from technical solution of the present invention content, it is right according to the technical essence of the invention
Any simple modification, equivalent change and modification made by above example still fall within the protection domain of technical solution of the present invention
Within.
Claims (10)
1. a kind of production method of thin-film transistor array base-plate, which is characterized in that the production method includes step：
The first metal layer is made on substrate (101), which includes scan line and grid (102)；
Deposition covers the first insulating layer (103) of the first metal layer on the substrate (101)；
Active layer (104) is made on first insulating layer (103)；
Second metal layer is made on first insulating layer (103), which includes data line, source electrode (106) and leakage
Pole (105), the source electrode (106) and the drain electrode (105) are connect with the active layer (104) respectively；
Deposition covers the second insulating layer (107) of the second metal layer on first insulating layer (103), and in second insulation
The first contact hole (201) is made in layer (107)；
Flatness layer (108) is deposited in the second insulating layer (107), and the second contact hole is made in the flatness layer (108)
(202), wherein second contact hole (202) is corresponding with (201) position at first contact hole；
The depositing first conductive layer (109) on the flatness layer (108), first conductive layer (109) cover second contact hole
(202), first conductive layer (109) is not performed etching first；
Metal electrode (110) is made on first conductive layer (109)；
After forming the metal electrode (110), then first conductive layer (109) is etched, which exists
Public electrode (111) is formed after etching；
The third insulating layer (112) of deposition the covering metal electrode (110) and the public electrode (111), and insulate in the third
Third contact hole (203) is made in layer (112), the wherein third contact hole (203) is opposite with the second contact hole (202) position
It answers；
Deposit second conductive layer and it is made as pixel electrode (113), the wherein pixel electrode on the third insulating layer (112)
(113) insert in the third contact hole (203) and second contact hole (202) and with the source electrode of the second metal layer (106) or
Drain (105) contact connectio.
2. the production method of thin-film transistor array base-plate according to claim 1, which is characterized in that second contact hole
(202) be less than first contact hole (201), so that the flatness layer (108) is inserted in first contact hole (201) and cover this first
The surrounding side wall of contact hole (201).
3. the production method of thin-film transistor array base-plate according to claim 1, which is characterized in that first contact hole
(201), the hole heart of second contact hole (202) and the third contact hole (203) is on same center line.
4. the production method of thin-film transistor array base-plate according to claim 1, which is characterized in that the public electrode
(111) region on other than pixel openings area is all covered with the metal electrode (110).
5. the production method of thin-film transistor array base-plate according to claim 1, which is characterized in that the metal electrode
(110) it is directly contacted with the public electrode (111).
6. the production method of thin-film transistor array base-plate according to claim 1, which is characterized in that being formed, this is flat
Further include that corona treatment is carried out to the second insulating layer (107) before layer (108).
7. a kind of thin-film transistor array base-plate, which is characterized in that the thin-film transistor array base-plate uses claim 1 to 6
Any one of them production method makes to be formed.
8. thin-film transistor array base-plate according to claim 7, which is characterized in that second contact hole (202) is less than
First contact hole (201) makes the flatness layer (108) insert in first contact hole (201) and covers first contact hole
(201) surrounding side wall.
9. thin-film transistor array base-plate according to claim 7, which is characterized in that on the public electrode (111) in addition to
Region other than pixel openings area is all covered with the metal electrode (110).
10. a kind of display device, which is characterized in that the display device includes claim 7 to 9 any one of them film crystal
Pipe array substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810095754.8A CN108305879B (en) | 2018-01-31 | 2018-01-31 | Thin film transistor array substrate, manufacturing method and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810095754.8A CN108305879B (en) | 2018-01-31 | 2018-01-31 | Thin film transistor array substrate, manufacturing method and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108305879A true CN108305879A (en) | 2018-07-20 |
| CN108305879B CN108305879B (en) | 2020-12-29 |
Family
ID=62867337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810095754.8A Active CN108305879B (en) | 2018-01-31 | 2018-01-31 | Thin film transistor array substrate, manufacturing method and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108305879B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109541862A (en) * | 2018-12-03 | 2019-03-29 | 惠科股份有限公司 | Active switch and preparation method thereof, array substrate and display device |
| CN112420738A (en) * | 2020-10-29 | 2021-02-26 | 南京中电熊猫液晶显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN113454783A (en) * | 2020-12-10 | 2021-09-28 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN114023762A (en) * | 2021-10-18 | 2022-02-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151304A (en) * | 2012-11-02 | 2013-06-12 | 友达光电股份有限公司 | Array substrate of display panel and manufacturing method thereof |
| CN103474436A (en) * | 2013-09-18 | 2013-12-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105470195A (en) * | 2016-01-04 | 2016-04-06 | 武汉华星光电技术有限公司 | Fabrication method of thin film transistor (TFT) substrate |
| US20160126255A1 (en) * | 2014-10-31 | 2016-05-05 | Samsung Dispaly Co., Ltd. | Display substrate and method of manufacturing the same |
| CN106098614A (en) * | 2016-08-16 | 2016-11-09 | 昆山龙腾光电有限公司 | The manufacture method of opening contact hole on multi-layer insulation film |
-
2018
- 2018-01-31 CN CN201810095754.8A patent/CN108305879B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151304A (en) * | 2012-11-02 | 2013-06-12 | 友达光电股份有限公司 | Array substrate of display panel and manufacturing method thereof |
| CN103474436A (en) * | 2013-09-18 | 2013-12-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| US20160126255A1 (en) * | 2014-10-31 | 2016-05-05 | Samsung Dispaly Co., Ltd. | Display substrate and method of manufacturing the same |
| CN105470195A (en) * | 2016-01-04 | 2016-04-06 | 武汉华星光电技术有限公司 | Fabrication method of thin film transistor (TFT) substrate |
| CN106098614A (en) * | 2016-08-16 | 2016-11-09 | 昆山龙腾光电有限公司 | The manufacture method of opening contact hole on multi-layer insulation film |
Non-Patent Citations (1)
| Title |
|---|
| 杨虹等: "VGA TFT LCD的驱动电路设计 ", 《液晶与显示》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109541862A (en) * | 2018-12-03 | 2019-03-29 | 惠科股份有限公司 | Active switch and preparation method thereof, array substrate and display device |
| WO2020113599A1 (en) * | 2018-12-03 | 2020-06-11 | 惠科股份有限公司 | Active switch and manufacturing method thereof, and display device |
| CN112420738A (en) * | 2020-10-29 | 2021-02-26 | 南京中电熊猫液晶显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN113454783A (en) * | 2020-12-10 | 2021-09-28 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method thereof and display panel |
| WO2022120746A1 (en) * | 2020-12-10 | 2022-06-16 | 昆山龙腾光电股份有限公司 | Array substrate and manufacturing method therefor, and display panel |
| CN113454783B (en) * | 2020-12-10 | 2023-08-29 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN114023762A (en) * | 2021-10-18 | 2022-02-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108305879B (en) | 2020-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101325053B1 (en) | Thin film transistor substrate and manufacturing method thereof | |
| US9236405B2 (en) | Array substrate, manufacturing method and the display device thereof | |
| US9761731B2 (en) | Thin film transistor and its manufacturing method, array substrate and its manufacturing method, and display device | |
| CN103489826B (en) | Array base palte, preparation method and display unit | |
| US9324735B2 (en) | Array substrate and manufacturing method thereof, display panel and display device | |
| US9502570B2 (en) | Thin film transistor and manufacturing method thereof, an array substrate and a display device | |
| US8895334B2 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
| WO2021036840A1 (en) | Display substrate, manufacturing method thereof, and display device | |
| KR20080109998A (en) | Thin film transistor array panel and manufacturing method thereof | |
| TWI606283B (en) | Display device | |
| US20080197356A1 (en) | Thin film transistor substrate and method of manufacturing the same | |
| US20150123118A1 (en) | Array substrate and method of fabricating the same | |
| CN107968097B (en) | Display device, display substrate and manufacturing method thereof | |
| CN103681696A (en) | Electrode lead-out structure, array substrate and display device | |
| CN103367248A (en) | Array substrate, preparation method of array substrate and display device | |
| CN108305879A (en) | Thin-film transistor array base-plate and production method and display device | |
| KR101622733B1 (en) | Method of fabricating oxide thin film transistor | |
| US20200348784A1 (en) | Touch display substrate, method of manufacturing the same and display device | |
| KR101085451B1 (en) | Tft substrate for display apparatus and manufacturing method of the same | |
| KR20160086016A (en) | Thin film transistor array panel and manufacturing method therfor | |
| US20170003529A1 (en) | Array substrate, method for manufacturing the same and liquid crystal display device | |
| JP6440228B2 (en) | Method for manufacturing thin film transistor substrate | |
| CN104241296A (en) | Array substrate, manufacturing method thereof and display device | |
| CN107112367A (en) | Thin film transistor base plate, the manufacture method of thin film transistor base plate, liquid crystal display device | |
| CN203503657U (en) | Array substrate and display apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |