KR20160086016A - Thin film transistor array panel and manufacturing method therfor - Google Patents

Thin film transistor array panel and manufacturing method therfor Download PDF

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KR20160086016A
KR20160086016A KR1020150002974A KR20150002974A KR20160086016A KR 20160086016 A KR20160086016 A KR 20160086016A KR 1020150002974 A KR1020150002974 A KR 1020150002974A KR 20150002974 A KR20150002974 A KR 20150002974A KR 20160086016 A KR20160086016 A KR 20160086016A
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electrode
oxide semiconductor
etch stopper
forming
gate
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KR1020150002974A
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Korean (ko)
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서기성
조정연
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삼성디스플레이 주식회사
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
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    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract

Disclosed are a thin film transistor display panel and a manufacturing method thereof, in which resistance of an oxide semiconductor channel is reduced. The thin film transistor display panel according to the present invention includes a substrate, a first gate electrode positioned on the substrate, a gate insulating film positioned on the first gate, an oxide semiconductor positioned on the gate insulating film and including a channel region, at least one etch stopper positioned on the oxide semiconductor, a second gate electrode, a source electrode and a drain electrode which are positioned on the at least one of the etch stopper, a passivation film formed on the second gate electrode, the source electrode and the drain electrode; and a pixel electrode positioned on the passivation film and connected to the drain electrode, in which the oxide semiconductor includes an N+ region formed in a portion exposed by the at least one of the etch stopper. In addition, the manufacturing method of the thin film transistor display panel according to an embodiment of the present invention includes the steps of: forming a first gate electrode on a substrate; forming a gate insulating film on the first gate electrode; forming an oxide semiconductor including a channel region on the gate insulating film; forming at least one etch stopper on the oxide semiconductor; forming an N+ region at the oxide semiconductor; forming a second gate electrode, a source electrode, and a drain electrode on at least one of the etch stopper; and forming a passivation film on the second gate electrode, the source electrode, and the drain electrode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor (TFT)

The present invention relates to a thin film transistor panel and a method of manufacturing the same.

A flat panel display may be used as the display device, and various devices such as a liquid crystal display, an organic light emitting display, a plasma display, an electrophoretic display, and an electrowetting display may be used as the flat panel display.

A typical liquid crystal display device is one of the most widely used flat panel display devices, and includes two display panels having a field generating electrode such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween And a backlight unit for providing light to a display panel sandwiching these liquid crystal layers.

A liquid crystal display displays an image by applying a voltage to an electric field fish electrode to generate an electric field in the liquid crystal layer, thereby determining the direction of liquid crystal molecules in the liquid crystal layer and controlling the amount of light emitted by the backlight unit.

In general, a display device including a liquid crystal display device includes a thin film transistor display panel.

The thin film transistor display panel comprises a gate electrode which is a part of a gate wiring, a semiconductor layer which forms a channel, and a source electrode and a drain electrode which are part of the data wiring.

The thin film transistor is a switching element for transmitting or blocking an image signal transmitted through a data line to a pixel electrode in accordance with a scanning signal transmitted through a gate line.

The matters described in the background section are intended to enhance the understanding of the background of the invention and may include matters not previously known to those skilled in the art.

An object of the present invention is to provide a thin film transistor panel having excellent performance by reducing the resistance of an oxide semiconductor channel by forming N + regions in the entire region of the oxide semiconductor exposed by the etch stopper and a method of manufacturing the same.

A thin film transistor panel according to an exemplary embodiment of the present invention includes a substrate, a first gate electrode positioned on the substrate, a gate insulating film disposed on the first gate, an oxide semiconductor disposed on the gate insulating film and including a channel region, A protective film formed on the second gate electrode, the source electrode, and the drain electrode, the second gate electrode, the source electrode, and the drain electrode on the at least one etch stopper; And a pixel electrode connected to the drain electrode, wherein the oxide semiconductor includes an N + region formed in a portion exposed by the at least one etch stopper.

One side of the N + region is in contact with the gate insulating film, and the other side of the N + region is in contact with the source electrode or the drain electrode.

The N + region may include first and second N + regions located between the at least one etch stopper and located on both sides of the first gate electrode.

Wherein the at least one etch stopper includes first to third etch stoppers.

The first etch stopper is located on the first gate electrode, the second and third etch stoppers are formed on both sides with respect to the first etch stopper, and can make a certain contact with the oxide semiconductor.

The second and third etch stoppers may contact both ends of the oxide semiconductor and the gate insulating film.

The source electrode and the drain electrode may cover the second etch stopper and the third etch stopper, respectively.

Wherein the second gate electrode is formed to have a narrower width than the first gate electrode.

The oxide semiconductor may include a TIZO oxide composed of a combination of titanium (Ti), indium (In), and zinc (Zn).

Wherein at least one channel region of the oxide semiconductor includes a first channel region and a second channel region, a first channel region is located at an upper portion of the gate insulating film, and a second channel region is located at a lower portion of the first etch stopper Can be located.

The protective layer may include fluorine-containing silicon oxide (SiOF).

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor panel, including: forming a first gate electrode on a substrate; forming a gate insulating film on the first gate electrode; Forming at least one etch stopper over the oxide semiconductor, forming an N + region in the exposed oxide semiconductor, depositing a second gate electrode, a source electrode, and a drain on the at least one etch stopper, Forming an electrode, and forming a protective film on the second gate electrode, the source electrode, and the drain electrode.

The forming of the N + region may include forming a PR on the at least one etch stopper, forming an N + region using PR as a mask, the N + region being exposed by the at least one etch stopper As shown in Fig.

The step of forming the N + region may be performed by any one of an ion implantation method and an inductively coupled plasma (ICP) method.

The inductively coupled plasma method may form an N + region by implanting fluorine.

One side of the N + region is in contact with the gate insulating film, and the other side of the N + region is in contact with the source electrode or the drain electrode.

The N + region may include first and second N + regions located between the at least one etch stopper and located on both sides of the first gate electrode.

The forming of the source electrode and the drain electrode may include forming the source electrode and the drain electrode such that the source electrode and the drain electrode are in constant contact with the oxide semiconductor.

The step of forming the at least one etch stopper may include forming a first etch stopper on the oxide semiconductor and forming second and third etch stoppers on both sides of the first etch stopper .

And the step of forming the second and third etch stoppers may be formed so as to contact both ends of the oxide semiconductor and the gate insulating film.

According to the thin film transistor panel according to the embodiment of the present invention, by forming the N + region in the entire region of the oxide semiconductor exposed by the etch stopper, it is possible to reduce the resistance of the oxide semiconductor channel and to provide the display panel with excellent performance.

In addition, effects obtainable or predicted by the embodiments of the present invention will be directly or implicitly disclosed in the detailed description of the embodiments of the present invention. That is, various effects to be predicted according to the embodiment of the present invention will be disclosed in the detailed description to be described later.

1 is a cross-sectional view illustrating a structure of a thin film transistor panel according to an exemplary embodiment of the present invention.
FIGS. 2 to 4 are views showing a manufacturing process of a thin film transistor panel according to an embodiment of the present invention.
5 is a plan view schematically showing a structure of a display device according to an embodiment having the thin film transistor panel of FIG.
6 is a circuit diagram showing a pixel circuit included in the display device of FIG.
7 is a layout diagram showing one pixel of the display device of FIG.
8 is a cross-sectional view taken along the line IV-IV in Fig.
9 is a cross-sectional view taken along the line VV in Fig.
10 is a plan view schematically showing the structure of a display device according to another embodiment having the thin film transistor panel of FIG.
11 is a cross-sectional view taken along the line VI-VI in Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, where a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

Hereinafter, a thin film transistor display panel according to an embodiment of the present invention will be described with reference to FIG.

1 is a cross-sectional view illustrating a structure of a thin film transistor panel according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the thin film transistor display panel 100 has a first gate electrode 124a formed on an insulating substrate 110 made of transparent glass or plastic.

A gate insulating layer 140 made of an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxide (SiO) is formed on the first gate electrode 124a. The gate insulating layer 140 may be formed using a sputtering method or the like, and may have a double-layer structure.

A first oxide semiconductor 154a including a channel region is formed on the gate insulating layer 140. [ The first oxide semiconductor 154a is a metal oxide semiconductor and may be an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) In, gallium (Ga), tin (Sn), titanium (Ti) and oxides thereof.

For example, the first oxide semiconductor 154a may be at least one selected from the group consisting of zinc oxide (ZnO), indium oxide (InO), zinc tin oxide (ZTO), zinc-indium oxide (IGZO), titanium oxide (TiO) Zinc oxide (IGZO), and titanium-indium-zinc oxide (TIZO).

The first oxide semiconductor 154a includes a channel region. The channel region includes a first channel region and a second channel region. The first channel region is located above the gate insulating layer 140 and the second channel region is located below the first etch stopper 160a.

The first oxide semiconductor 154a is N + doped to a portion except for the area protected by an etch stopper 160 to be described later to form an N + region 157. [ The N + region 157 will be described in more detail below.

At least one etch stopper 160 is formed on the first oxide semiconductor 154a. The etch stopper 160 is composed of first to third etch stoppers 160a, 160b and 160c, and the first etch stopper 160a is formed on the first gate electrode 124a. That is, the first etch stopper 160a is formed on the channel region of the first oxide semiconductor 154a, and it is possible to prevent the channel region, which becomes a channel of the thin film transistor, from being damaged by an etchant or the like in a subsequent process.

In addition, the first etch stopper 160a can prevent diffusion of impurities such as hydrogen from an insulating layer such as a protective film 180 or a channel region from the outside, which will be described later, and prevent the channel region from changing its properties.

The second and third etch stoppers 160b and 160c are formed on both sides with respect to the first etch stopper 160a. The second and third etch stoppers 160b and 160c are in contact with a part of both ends of the first oxide semiconductor 154a and a part of the gate insulating film 140. [

At least one of the etch stopper 160, or the inorganic film containing at least one material selected from the group consisting of SiO x, SiN x, SiOC x , x or SiON, can be formed in the organic film comprising an organic material or a polymer organic material.

The at least one etch stopper 160 protects the first oxide semiconductor 154a when the N + region 157 is formed in the first oxide semiconductor 154a and the N + region 157 has at least one And may be formed in the region of the first oxide semiconductor 154a exposed by the etch stopper 160. [

More specifically, one side of the N + region 157 is in contact with the gate insulating film 140, and the other side of the N + region 157 is in contact with the first side of the first oxide semiconductor 154a, And is in contact with the source electrode 173a or the first drain electrode 175b. The N + region 157 includes first and second N + regions 157a and 157b. The first N + region 157a is formed between the first etch stopper 160a and the first etch stopper 160b And the second N + region 157b may be formed between the first etch stopper 160a and the third etch stopper 160c. At this time, the positions of the first to third etch stoppers 160 and the first and second N + regions 157 may be changed.

A second gate electrode 124b, a first source electrode 173a, and a first drain electrode 175a are formed on the at least one etch stopper 160, respectively.

The second gate electrode 124b is formed on the first etch stopper 160a and the first source electrode 173a is formed on the second etch stopper 160b and the first drain electrode 175b is formed on the third etch stopper And 160c, respectively.

The first source electrode 173a and the first drain electrode 175a cover the second etch stopper 160b and the third etch stopper 160c, respectively. At this time, the second gate electrode 124b may be narrower than the first gate electrode 124a. That is, the first source electrode 173a and the first drain electrode 173b are located on both sides of the channel region, and are separated from each other. The first source electrode 173a and the first drain electrode 175b may overlap the second gate electrode 124b or may not substantially overlap each other. The first source electrode 173a and the first drain electrode 175b are physically and electrically connected to the channel region and may have conductivity. The first source electrode 173a and the first drain electrode 175b overlap the first oxide semiconductor 154a forming the channel region. The first source electrode 173a and the first drain electrode 175a overlap the first oxide semiconductor 154a, The carrier concentration of the channel region is different from the carrier concentration of the channel region.

A passivation layer 180 is formed on the second gate electrode 124b, the first source electrode 173a, and the first drain electrode 175a. The protective film 180 is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, or a low dielectric constant insulating material. The dielectric constant of the organic insulating material and the low dielectric constant insulating material is preferably 4.0 or less. Examples of the low dielectric insulating material include fluorinated oxides (a-SiOF) formed by plasma chemical vapor deposition (PECVD) . Thus, the passivation layer 180 may be formed of an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOF), or the like.

A pixel electrode 191 is disposed on the passivation layer 180 and is connected to the first drain electrode 175a.

Hereinafter, a process for manufacturing the thin film transistor display panel 100 having the above-described structure will be described with reference to FIGS. 2 to 4. FIG.

FIGS. 2 to 4 are views showing a manufacturing process of the thin film transistor panel 100 according to the embodiment of the present invention, and a detailed description of the general manufacturing process will be omitted.

First, referring to FIG. 2, a first gate electrode 124a is formed on an insulating substrate 110 made of transparent glass or plastic.

Next, a gate insulating film 140 made of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxide (SiO) is formed on the first gate electrode 124a.

Next, an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) A first oxide semiconductor 154a made of a combination of a metal such as gallium (Ga), tin (Sn), and titanium (Ti) and an oxide thereof is formed. At this time, a first etch stopper 160a is formed on the protruding upper portion of the first oxide semiconductor 154a, and second and third etch stoppers 160b and 160c are formed on both ends of the first oxide semiconductor 154a . The second and third etch stoppers 160b and 160c are in contact with a part of both ends of the first oxide semiconductor 154a and a part of the gate insulating film 140. [

Next, referring to FIG. 3, a photoresist (PR) is formed on the first to third etch stoppers 160. Here, the photoresist is made of a polymer compound having photosensitivity, adhesiveness and corrosion resistance.

In an embodiment of the present invention, a negative resist will be described as an example. Such a negative resist is a type of photoresist that is not soluble in a developer upon receiving light.

A photoresist film is formed on the first oxide semiconductor 154a and the first to third etch stoppers 160, and then a photolithography process is performed using a mask disposed on the photoresist film. After the photolithography process, the photoresist on the first oxide semiconductor 154a is etched, and the photoresist on the first to third etch stoppers 160 is not etched.

Referring to FIG. 4, the N + region 157 is formed in the first oxide semiconductor 154a by doping N + using the photoresist remaining on the first to third etch stoppers 160 as a mask. At this time, the N + region 157 may be formed by using an ion implantation method and an inductively coupled plasma (ICP) method.

The ion implantation method may be performed under vacuum or at room temperature. An ion beam accelerated from several tens to several hundreds of keV is formed by ion implantation of N + ions into the first oxide semiconductor 154a, (157).

In addition, in the method using an inductively coupled plasma, a plasma state is generated electrically by flowing a mixture of an inert gas such as argon and a spraying sample along the axis of the high-frequency coil, thereby using the emitted light as a light source. The N + region 157 is formed by doping N + into the first oxide semiconductor 154a using such a light source.

At this time, the inductively coupled plasma method injects fluorine to form the N + region 157.

When the N + region 157 is formed in the first oxide semiconductor 154a in the above-described manner, the first oxide semiconductor 154a is removed from the first oxide semiconductor 154a except for the region where the first to third etch stoppers 160 are located N + is doped. The first oxide semiconductor 154a having the N + region 157 has excellent conductivity as a conductor.

Then, the photoresist is removed, and a second gate electrode 124b, a first source electrode 173a, and a first drain electrode 175a are formed on the first to third etch stoppers 160, respectively. The second gate electrode 124b is formed on the first etch stopper 160a and may have a narrower width than the first gate electrode 124a.

The first source electrode 173a and the first drain electrode 175a are formed on the second and third etch stoppers 160b and 160c and cover the second and third etch stoppers 160b and 160c.

Finally, a protective film 180 is formed on the top of the thin film transistor display panel 100. The passivation layer 180 may be formed of an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOF) Then, a pixel electrode 191 connected to the first drain electrode 175a is formed.

Hereinafter, a display device formed by using the thin film transistor display panel 100 manufactured as described above as a switching transistor will be described.

FIG. 5 is a plan view schematically showing the structure of a display device according to an embodiment having the thin film transistor panel of FIG. 1, FIG. 6 is a circuit diagram showing a pixel circuit of the display device of FIG. 5, 8 is a cross-sectional view taken along line IV-IV in Fig. 7, and Fig. 9 is a cross-sectional view taken along line VV in Fig.

As shown in Fig. 5, the display device includes a substrate main body 111 divided into a display area DA and a non-display area NA. A plurality of pixel regions PE are formed in the display region DA of the substrate main body 111 to display an image and one or more driving circuits 910 and 920 are formed in the non-display region NA. Here, the pixel region PE refers to an area where a pixel, which is the minimum unit for displaying an image, is formed. However, in one embodiment of the present invention, not all the driving circuits 910 and 920 are necessarily formed in the non-display area NA, and some or all of the driving circuits 910 and 920 may be omitted.

6, a display device according to an exemplary embodiment of the present invention includes an OLED (Organic Light Emitting Diode) 70, two thin film transistors 10 and 20 for each pixel region PE, And a capacitor (capacitor) 80 are disposed in the organic light emitting display device. However, the present invention is not limited to this embodiment. Accordingly, the display device may be an organic light emitting display device having a structure in which three or more thin film transistors and two or more capacitors are arranged in each pixel region (PE). In addition, the display device formed by using the thin film transistor panel 100 according to the exemplary embodiment of the present invention as a switching transistor is not limited to the organic light emitting display, and may be applied to a light emitting diode (LED).

Further, the display device may be formed to have various structures by further forming additional wiring. As such, the compensation circuit of one or more of the thin film transistors and capacitors formed additionally can be constituted.

The compensation circuit improves the uniformity of the organic light emitting element 70 formed for each pixel region PE and suppresses deviation in image quality. In general, the compensation circuit may comprise two to eight thin film transistors.

Further, the driving circuits 910 and 920 formed on the non-display area NA of the substrate main body 111 may also include additional thin film transistors.

The organic light emitting device 70 includes an anode electrode as a hole injection electrode, a cathode electrode as an electron injection electrode, and an organic light emitting layer disposed between the anode electrode and the cathode electrode.

Specifically, in one embodiment of the present invention, the display apparatus includes a first thin film transistor 10 and a second thin film transistor 20 for each pixel region (PE). The first thin film transistor 10 and the second thin film transistor 20 each include a gate electrode, a semiconductor, a source electrode, and a drain electrode.

6 shows a capacitor line CL together with a gate line GL, a data line DL and a common power line VDD. However, an embodiment of the present invention is not limited to the structure shown in FIG. 6 . Therefore, the capacitor line CL may be omitted in some cases.

A source electrode of the second thin film transistor 20 is connected to the data line DL and a gate electrode of the second thin film transistor 20 is connected to the gate line GL. The drain electrode of the second thin film transistor 20 is connected to the capacitor line CL through the capacitor 80. A node is formed between the drain electrode of the second thin film transistor 20 and the capacitor 80, and the gate electrode of the first thin film transistor 10 is connected. A common power supply line (VDD) is connected to the drain electrode of the first thin film transistor 10, and an anode electrode of the organic light emitting diode 70 is connected to the source electrode.

The second thin film transistor 20 is used as a switching element for selecting a pixel region PE to emit light. When the second thin film transistor 20 is momentarily turned on, the capacitor 80 is accumulated, and the amount of charge accumulated at this time is proportional to the potential of the voltage applied from the data line DL. When the second thin-film transistor 20 is turned off and a voltage-rising signal is applied to the capacitor line CL at one frame period, the gate potential of the first thin- The level of the voltage applied based on the potential rises along the voltage applied through the capacitor line CL. The first thin film transistor 10 is turned on when the gate potential exceeds the threshold voltage. Then, a voltage applied to the common power supply line VDD is applied to the organic light emitting element 70 through the first thin film transistor 10, and the organic light emitting element 70 emits light.

The configuration of the pixel region PE is not limited to the above-described structure, and various modifications can be made within a range that can easily be modified by those skilled in the art.

5 and 6, a display device having the thin film transistor display panel 100 of FIG. 1 as a switching transistor will be described in detail with reference to FIGS. 7 to 9. FIG.

A plurality of gate conductors including a plurality of gate lines 121 and a plurality of third gate electrodes 124c including a first gate electrode 124a are formed on an insulating substrate 110 made of transparent glass or plastic, .

The gate line 121 transmits the gate signal and extends mainly in the horizontal direction. Each gate line 121 includes a wide end portion 129 for connection to another layer or external drive circuitization and the first gate electrode 124a extends from the gate line 121 upward. In the case where a gate driving circuit (not shown) for generating a gate signal is integrated on the insulating substrate 110, the gate line 121 may extend and be directly connected to the gate driving circuit.

The third gate electrode 124c is separated from the gate line 121 and includes a storage electrode 127 extending downward and extending to the right for a while.

The gate conductors 121 and 124c may be formed of a metal such as aluminum (Al) or an aluminum alloy, a silver-based alloy such as silver or silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, molybdenum Molybdenum alloy, molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the two conductive films is made of a metal having low resistivity, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay or voltage drop. Alternatively, the other conductive film is made of a material having excellent physical, chemical and electrical contact properties with other materials, especially ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), such as molybdenum series metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium lower film aluminum (alloy) upper film and an aluminum (alloy) lower film molybdenum (alloy) upper film. However, the gate conductors 121 and 124c may be made of a variety of other metals or conductors.

The side surfaces of the gate conductors 121 and 124c are inclined with respect to the surface of the insulating substrate 110, and the inclination angle thereof is preferably about 30 to 80 degrees.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is disposed on the gate conductors 121 and 124c.

A first oxide semiconductor 154a of titanium-indium-zinc (TIZO) is extended in parallel with the gate line 121 so as to overlap with the gate electrode 124 on the gate insulating film 140.

Although the oxide semiconductor according to the embodiment of the present invention has been described by taking a semiconductor layer made of a titanium-indium-zinc (TIZO) oxide semiconductor as an example, it is not necessarily limited thereto. ), Tin (Sn) and titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) And it is possible to apply any oxide as long as it exhibits switching characteristics.

At least one etch stopper 160 is disposed on the first oxide semiconductor 154a. The at least one etch stopper 160 is composed of first to third etch stoppers 160a, 160b and 160c and the first etch stopper 160a is located at a protruding upper portion of the first oxide semiconductor 154a. The second and third etch stoppers 160b and 160c are overlapped with a portion of both ends of the first oxide semiconductor 154a with respect to the first etch stopper 160a. The first to third etch stoppers 160 protect the remaining part of the first oxide semiconductor 154a to form the N + region 157. [

The second and third etch stoppers 160b and 160c are located in a region where the first source electrode 173a and the first drain electrode 175a overlap with the first oxide semiconductor 154a. These second and third etch stoppers 160b and 160c facilitate the connection between the first gate electrode 124a and the second gate electrode 124b. The side surface of the first oxide semiconductor 154a is also inclined, and the inclination angle is 30 DEG to 80 DEG.

A plurality of data lines 171, a plurality of driving voltage lines 172, and a plurality of first and second drain electrodes 175a and 175b are formed on the first oxide semiconductor 154a and the at least one etch stopper 160, Data conductor is located.

The data line 171 carries a data signal and extends mainly in the vertical direction and crosses the gate line 121. Each data line 171 includes a first source electrode 173a extending toward the first gate electrode 124a and a wide end portion 179 for connection to another layer or an external driving circuit. When a data driving circuit (not shown) for generating a data signal is provided on the insulating substrate 110, the data line 171 may extend and be directly connected to the data driving circuit.

The driving voltage line 172 carries the driving voltage and mainly extends in the longitudinal direction and crosses the gate line 121. Each of the driving voltage lines 172 includes a plurality of second source electrodes 173b extending toward the third gate electrode 124c. The driving voltage line 172 overlaps with the sustain electrode 127 and can be connected to each other.

The first and second drain electrodes 175a and 175b are separated from each other and separated from the data line 171 and the driving voltage line 172. [ The first source electrode 173a and the first drain electrode 175a face each other with respect to the first gate electrode 124a and the first etch stopper 160a and the second source electrode 173b and the second drain electrode 175a face each other, The first gate electrode 175b faces the third gate electrode 124c.

A second gate electrode 124b is located on the first etch stopper 160a. The second gate electrode 124b and the first etch stopper 160a have a similar planar shape when viewed in a plan view. In particular, the width of the second gate electrode 124b is smaller than the width of the first etch stopper 160a.

The second gate electrode 124b is similar to the planar shape of the first gate electrode 124a as shown in FIG. 8, but has a smaller width than the first gate electrode 124a.

The second gate electrode 124b is formed at the same time as the first source electrode 173a and the first drain electrode 175a and does not overlap with the first gate electrode 124a in a smaller shape than the first etch stopper 160a, ). Therefore, the second gate electrode 124b does not form a separate storage capacitor Cst.

The first gate electrode 124a and the second gate electrode 124b are connected through the contact hole 21 and can receive the same voltage. However, it is needless to say that the first gate electrode 124a and the second gate electrode 124c can receive a voltage independently.

The data conductors 171, 172, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof. The refractory metal film (not shown) ≪ / RTI >

Examples of the multilayer structure include a double film of a chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a molybdenum (alloy) lower film, an aluminum (alloy) intermediate film and a molybdenum (alloy) upper film. However, the data conductors 171, 172, 175a, 175b and the second gate electrode 124b may be made of various other metals or conductors.

Similarly to the gate conductors 121 and 124c, the data conductors 171, 172, 175a, and 175b and the second gate electrode 124b are formed such that the sides thereof are inclined at an angle of about 30 ° to 80 ° with respect to the substrate 110 It is preferable to be inclined.

A resistive contact member (not shown) is only present between the underlying oxide semiconductors 154a, 154b and the data conductors 171, 172, 175a, 175b thereon, and lowers the contact resistance.

The first oxide semiconductor 154a is provided with data conductors 171 and 172 between the first etch stopper 160a and the second etch stopper 160b and between the first etch stopper 160a and the third etch stopper 160c. 175a, and 175b.

An N + region 157 may be formed between the first etch stopper 160a and the second etch stopper 160b and between the first etch stopper 160a and the third etch stopper 160c.

A protective film 180 is formed on the portions of the data conductors 171, 172, 175a, and 175b and the exposed first oxide semiconductor 154a. The protective film 180 may be made of an inorganic insulating material, an organic insulating material, a low dielectric constant insulating material, and may be, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON) . The surface of the protective film 180 may be flat. However, the protective layer 180 may have a bilayer structure of the lower inorganic layer and the upper organic layer so that the oxide semiconductor 154a and 154b are not damaged at the same time while taking advantage of the excellent insulating property of the organic layer.

The protective film 180 is formed with a plurality of contact holes 182, 185a and 185b for exposing the end portion 179 of the data line 171 and the first and second drain electrodes 175a and 175b, 180 and the gate insulating film 140 are formed with a plurality of contact holes 181 and 184 that respectively expose the end portion 129 of the gate line 121 and the third gate electrode 124c.

A plurality of pixel electrodes 191, a plurality of connecting members 85 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the second drain electrode 175b through the contact hole 185b and the connecting member 85 is electrically connected to the third gate electrode 124c And the first drain electrode 175a.

The contact assistants 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact assistants 81 and 82 complement and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device.

A partition (partition) 361 is formed on the protective film 180. The barrier rib 361 surrounds the edge of the pixel electrode 191 as a bank and defines an opening 365 and is made of an organic insulating material or an inorganic insulating material. Further, the barrier ribs 361 may be made of a photosensitive material containing a black pigment. In this case, the barrier ribs 361 serve as a light shielding member, and the forming process is simple.

An organic light emitting member 370 is formed in the opening 365 on the pixel electrode 191 defined by the barrier rib 361. The organic light emitting member 370 is made of an organic material that uniquely emits light of any one of basic colors such as red, green, and blue. The organic electroluminescence display device displays a desired image with a spatial sum of basic color light emitted by the organic light emitting members 370. [

The organic light emitting member 370 may have a multi-layer structure including an emission layer (not shown) for emitting light and an auxiliary layer (not shown) for improving the light emitting efficiency of the light emitting layer. An electron transport layer (not shown) and a hole transport layer (not shown) for balancing electrons and holes, an electron injecting layer for enhancing the injection of sperm and holes, (Not shown) and a hole injecting layer (not shown).

A common electrode 270 is formed on the organic light emitting member 370. The common electrode 270 receives a common voltage Vss and is formed of a reflective metal such as Ca, Ba, Mg, Al, Ag or ITO or ITO or IZO Of transparent conductive material.

In this organic light emitting display device, the first gate electrode 124a and the second gate electrode 124b connected to the gate line 121, the first source electrode 173a connected to the data line 171, The drain electrode 175a forms a switching TFT Qs together with the first oxide semiconductor 154a and a channel of the switching TFT Qs is connected to the first source electrode 173a and the first Drain electrodes 175a in the first oxide semiconductor 154a. A third gate electrode 124c connected to the first drain electrode 175a, a second source electrode 173b connected to the driving voltage line 172, and a second drain electrode connected to the pixel electrode 191 And the channel of the driving thin film transistor Qd constitutes a driving thin film transistor Qd between the second source electrode 173b and the second drain electrode 175b And is formed in the second oxide semiconductor 154b. The pixel electrode 191, the organic light emitting member 370 and the common electrode 270 form an organic light emitting diode (LD), and the pixel electrode 191 serves as a cathode and the common electrode 270 serves as an anode. The sustain electrode 127 and the drive voltage line 172 overlapping each other constitute a storage capacitor Cst.

The OLED display emits light upward or downward from the insulating substrate 110 to display an image. The opaque pixel electrode 191 and the transparent common electrode 270 are applied to a top emission type organic light emitting display in which an image is displayed in an upward direction of the substrate 110. The transparent pixel electrode 191, The opaque common electrode 270 is applied to an organic light emitting display device of a botton emission type in which an image is displayed in a downward direction of the substrate 110.

Since the first gate electrode 124a and the second gate electrode 124b do not overlap with the first source electrode 173a or the first drain electrode 175a in the display apparatus according to an embodiment of the present invention, It is possible to prevent the parasitic storage capacitance that may occur between the gate electrode 124a and the second gate electrode 124b and the first source electrode 173a or the first drain electrode 175a. Therefore, it is possible to prevent a signal delay caused by such a parasitic storage capacitance.

Hereinafter, a display apparatus according to another embodiment including a thin film transistor panel according to an embodiment of the present invention will be described.

However, the same reference numerals are applied to the same structures as those of the display device according to the embodiment of the present invention.

FIG. 10 is a plan view schematically showing a structure of a display device according to another embodiment having the thin film transistor panel of FIG. 1, and FIG. 11 is a sectional view taken along the line VI-VI of FIG.

10 and 11, a liquid crystal display (LCD) including a thin film transistor display panel 100 according to an embodiment of the present invention includes a thin film transistor panel 100, an upper panel 200, And a liquid crystal layer 3 disposed on the two display panels 100 and 200. A backlight unit 300 is disposed under the thin film transistor display panel 100. [

In addition, the backlight unit 300 is not limited to the position facing the thin film transistor display panel 100, and may be disposed at a position facing the upper panel 200.

Here, the thin film transistor display panel 100 of the liquid crystal display device according to another embodiment of the present invention is the same as that of FIG. 1, and a detailed description thereof will be omitted.

Next, the upper panel 200 will be described with reference to FIG.

A light shielding member 220 is placed on an upper insulating substrate 210 made of transparent glass or plastic. The light shielding member 220 covers the light leakage between the pixel electrodes 191 and defines an opening area facing the pixel electrode 191.

A plurality of color filters 230 are disposed on the upper insulating substrate 210 and the light shielding member 220. The color filter 230 is mostly present in a region surrounded by the light shielding member 220 and can be elongated along the column of the pixel electrode 191.

Each color filter 230 may display one of the primary colors, such as the three primary colors of red, green, and blue.

The light shielding member 220 and the color filter 230 are disposed on the upper panel 200 in the display device according to another embodiment of the present invention. However, at least one of the light shielding member 220 and the color filter 230 Or may be located in the thin film transistor display panel 100. [

An overcoat 250 is disposed on the color filter 230 and the light shielding member 220. The cover film 250 can be made of (organic) insulation and prevents the color filter 230 from being exposed and provides a flat surface. The cover film 250 may be omitted.

A common electrode 270 is disposed on the cover film 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO, and receives the common voltage Vcom.

The liquid crystal layer 3 between the thin film transistor display panel 100 and the upper panel 200 includes liquid crystal molecules having a negative dielectric constant anisotropy and the long axis of the liquid crystal molecules is parallel to the two display panels 100, 200 in a direction perpendicular to the surface of the substrate.

The pixel electrode 191 and the common electrode 270 together with the portion between the liquid crystal side 30 and the pixel electrode 191 maintain the applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the sustain electrode line (not shown) to form a storage capacitor, thereby enhancing the voltage holding capability of the liquid crystal capacitor.

The backlight unit 300 of the display device according to another embodiment of the present invention as shown in FIG. 11 may include a light source and a light guide plate, and supplies light.

Although the display device using the thin film transistor display panel 100 according to the embodiment of the present invention has been described above, the description of the thin film transistor display panel 100 may be applied to any other display device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

100: Thin film transistor display panel
110: insulating substrate
124: gate electrode
140: gate insulating film
154: oxide semiconductor
160: etch stopper
173: source electrode
175: drain electrode
180: Shield
157: N + region

Claims (20)

  1. Board,
    A first gate electrode located on the substrate,
    A gate insulating film located above the first gate,
    An oxide semiconductor located on the gate insulating film and including at least one channel region,
    At least one etch stopper positioned over the oxide semiconductor,
    A second gate electrode, a source electrode, and a drain electrode located above the at least one etch stopper,
    A protective film formed on the second gate electrode, the source electrode, and the drain electrode, and
    A pixel electrode disposed on the passivation layer and connected to the drain electrode,
    / RTI >
    Wherein the oxide semiconductor comprises an N + region formed in a portion exposed by the at least one etch stopper.
  2. The method according to claim 1,
    One side of the N + region is in contact with the gate insulating film,
    And the other side of the N + region is in contact with the source electrode or the drain electrode.
  3. 3. The method of claim 2,
    And the N + region includes first and second N + regions located between the at least one etch stopper and positioned at both sides with respect to the first gate electrode.
  4. The method according to claim 1,
    Wherein the at least one etch stopper includes first to third etch stoppers.
  5. 5. The method of claim 4,
    The first etch stopper is located above the first gate electrode,
    Wherein the second and third etch stoppers are formed on both sides with respect to the first etch stopper, and are in constant contact with the oxide semiconductor.
  6. 6. The method of claim 5,
    And the second and third etch stoppers are in contact with both ends of the oxide semiconductor and the gate insulating film.
  7. 5. The method of claim 4,
    Wherein the source electrode and the drain electrode cover the second etch stopper and the third etch stopper, respectively.
  8. The method according to claim 1,
    Wherein the second gate electrode is formed to have a narrower width than the first gate electrode.
  9. The method according to claim 1,
    Wherein the oxide semiconductor comprises a TIZO oxide comprising a combination of titanium (Ti), indium (In), and zinc (Zn).
  10. The method according to claim 1,
    Wherein at least one channel region of the oxide semiconductor comprises a first channel region and a second channel region,
    Wherein the first channel region is located above the gate insulating film and the second channel region is located below the first etch stopper.
  11. The method according to claim 1,
    Wherein the protective film comprises silicon oxide (SiOF) containing fluorine.
  12. Forming a first gate electrode over the substrate,
    Forming a gate insulating film on the first gate electrode,
    Forming an oxide semiconductor including a channel region on the gate insulating film,
    Forming at least one etch stopper on the oxide semiconductor,
    Forming an N + region in the exposed oxide semiconductor;
    Forming a second gate electrode, a source electrode, and a drain electrode on the at least one etch stopper; and
    Forming a protective film on the second gate electrode, the source electrode, and the drain electrode,
    And forming a thin film transistor on the substrate.
  13. 13. The method of claim 12,
    The step of forming the N < + >
    Forming a PR on the at least one etch stopper, forming an N + region using PR as a mask,
    And the N + region is formed in a portion of the oxide semiconductor exposed by the at least one etch stopper.
  14. 13. The method of claim 12,
    The step of forming the N < + >
    An ion implantation method, and an inductively coupled plasma (ICP) method.
  15. 15. The method of claim 14,
    The inductively coupled plasma method
    And implanting fluorine to form an N + region.
  16. 13. The method of claim 12,
    One side of the N + region is in contact with the gate insulating film,
    And the other side of the N + region is in contact with the source electrode or the drain electrode.
  17. 17. The method of claim 16,
    And the N + regions are located between the at least one etch stopper and include first and second N + regions located on both sides with respect to the first gate electrode.
  18. 13. The method of claim 12,
    The step of forming the source electrode and the drain electrode includes
    And the source electrode and the drain electrode are formed so as to be in constant contact with the oxide semiconductor.
  19. 13. The method of claim 12,
    The step of forming the at least one etch stopper
    Forming a first etch stopper on the oxide semiconductor, and
    Forming second and third etch stoppers on both sides with respect to the first etch stopper,
    Wherein the method further comprises the steps of:
  20. 20. The method of claim 19,
    Wherein the step of forming the second and third etch stoppers is formed to contact both ends of the oxide semiconductor and the gate insulating film.
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