CN203503657U

CN203503657U - Array substrate and display apparatus

Info

Publication number: CN203503657U
Application number: CN201320385292.6U
Authority: CN
Inventors: 成军; 宁策; 孙宏达; 杨维; 王珂
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2013-07-01
Filing date: 2013-07-01
Publication date: 2014-03-26
Anticipated expiration: 2023-07-01

Abstract

The utility model belongs to the display technical field and more specifically refers to an array substrate and a display apparatus. The array substrate comprises a substrate and a plurality of grid lines and a plurality of data lines arranged on the substrate. The grid lines and the data lines are intersected and divide the substrate into a plurality of pixel areas; thin film transistors are arranged in the pixel areas and comprise grid electrodes, source electrodes and drain electrodes; the grid electrodes are in electric connection with the grid lines; the source electrodes are in electric connection with the data lines; wherein the grid electrodes, the grid lines and the data lines are arranged on a same layer; the data lines are disconnected in the areas intersecting with the grid lines; the disconnected lines are in electric connection through number-number connecting lines which are not on a same layer with the data lines. The beneficial effects are that in the array substrate, an active layer is formed by employing metal-oxide semiconductor materials; a whole array substrate can be completed only by employing four composition processes; the grid lines and the data lines are formed by a same metal layer forming the grid electrodes, which simplifies processes, greatly raises production power and reduces cost.

Description

Array base palte and display unit

Technical field

The utility model belongs to Display Technique field, is specifically related to a kind of array base palte and display unit.

Background technology

Along with scientific and technical development, panel display apparatus has replaced heavy CRT (Cathode Ray Tube, cathode ray tube) display unit to be goed deep in daily life day by day.Plasma display system) and OLED(Organic Light-Emitting Diode liquid crystal indicator), PDP(Plasma Display Panel at present, conventional panel display apparatus comprises LCD(Liquid Crystal Display::: Organic Light Emitting Diode) display unit.Especially OLED display unit, compares with LCD, has the plurality of advantages such as self-luminous, the wide visual angle of fast response time, can be used for flexible demonstration, transparent demonstration, the multiple application such as 3D demonstration.

In imaging process, LCD and active matrix drive type OLED(Active Matrix Organic Light Emission Display, abbreviation AMOLED) each pixel in display unit is all driven by the thin-film transistor (Thin Film Transistor: be called for short TFT) being integrated in array base palte, thereby realize image, shows.Each thin-film transistor can independently be controlled a pixel, and can other pixels not caused and be crosstalked.Thin-film transistor, as luminescence control switch, is the key that realizes LCD and the demonstration of OLED display unit, is directly connected to the developing direction of high-performance display device.

Thin-film transistor mainly comprises grid, gate insulation layer, active layer, source electrode and drain electrode.At present, active layer adopts material or metal oxide semiconductor material to form conventionally.

Adopt metal oxide semiconductor material as active layer, thin-film transistor has good ON state current, switching characteristic, and mobility is high, and good uniformity does not need to increase compensating circuit, in number of masks and manufacture difficulty, all has superiority; When having elevated oxygen level, metal oxide semiconductor material can show good characteristic of semiconductor, while having compared with low oxygen content, there is lower resistivity, therefore can be used as transparency electrode uses, be enough to be used in the fast application of response and larger electric current of needs, as be applied to high frequency, high-resolution, in large-sized LCD and OLED display unit.Meanwhile, the manufacture craft that metal oxide semiconductor material forms active layer is simple, adopts the methods such as sputter, good with existing LCD product line matching, easily transition, does not need to increase extra equipment, has cost advantage.

But, adopt metal oxide semiconductor material as active layer, the preparation technology of thin-film transistor generally need adopt above composition technique six times, and production capacity is lower.As shown in Figure 1, a kind of typical structure that available technology adopting metal oxide semiconductor material forms the thin-film transistor of active layer is: grid 2a is set on substrate 1, gate insulation layer 3 is set on grid 2a, it is metal oxide semiconductor layer that active layer 4(is set on gate insulation layer 3), etching barrier layer 5 is set on active layer 4, source electrode 6a and drain electrode 6b are set on etching barrier layer 5, on source electrode 6a and drain electrode 6b, passivation layer 7 is set, it is ito transparent electrode layer that pixel electrode 8(is set on passivation layer 7).

Accordingly, the preparation method of the thin-film transistor of said structure is: on substrate 1, deposit gate metal material, adopt composition technique for the first time to form grid 2a; On grid 2a, deposit gate insulation layer 3, on gate insulation layer 3, deposit active layer 4, adopt for the second time composition technique to form trench area and source electrode, drain contact region; Deposition-etch barrier film on active layer 4, adopts composition technique for the third time to form etching barrier layer 5; Deposit metallic material on etching barrier layer 5, adopts the 4th composition technique to form source electrode 6a and drain electrode 6b; Deposit passivation layer film on source electrode 6a and drain electrode 6b, adopts the 5th composition technique to form the via hole in passivation layer 7 and passivation layer 7; On passivation layer 7, deposit ito transparent electrode material, adopt the 6th composition technique to form pixel electrode 8, pixel electrode 8 is connected with drain electrode 6b by via hole.

Utility model content

Technical problem to be solved in the utility model is for above shortcomings in prior art, a kind of array base palte and display unit are provided, this array base palte only needs to adopt four composition techniques to have prepared, and grid line and data wire are formed by the same layer metal level that forms grid, have simplified technique.

The technical scheme that solution the utility model technical problem adopts is this array base palte, comprise substrate and be arranged at many grid lines and many data wires on described substrate, described grid line and described data wire are arranged in a crossed manner and described substrate is divided into a plurality of pixel regions, in described pixel region, be provided with thin-film transistor, described thin-film transistor comprises grid, source electrode and drain electrode, described grid is electrically connected to described grid line, described source electrode is electrically connected to described data wire, wherein, described grid, described grid line and described data wire arrange with layer, described data wire disconnects in the region intersecting with described grid line, the described data wire disconnecting is electrically connected to by the number-number connecting line with described data wire different layers.

Preferably, in described pixel region, be also provided with pixel electrode, described number-number connecting line, described source electrode, described drain electrode and described pixel electrode arrange with layer, and described number-number connecting line is arranged at corresponding described data wire with the areas of disconnection of described grid line and is connected with the described data wire of disconnection.

Preferably, described array base palte also comprises gate insulation layer and active layer, and described gate insulation layer is arranged between described grid and described source electrode and described drain electrode; Described active layer and described grid be over against setting, and be positioned at described gate insulation layer away from a side of described grid; Described source electrode and described drain electrode are close to described active layer and are arranged at the two ends of corresponding described active layer and partly overlap in orthographic projection direction with described grid.

A kind of preferred structure is, described array base palte also comprises etching barrier layer,

Described grid, described grid line and described data wire are arranged on described substrate with layer;

Described gate insulation layer is arranged at the top of described grid, described grid line and described data wire, and cover described grid, described grid line and described data wire completely, the region that described gate insulation layer described data wire in correspondence offers the first connecting line via hole and first source-number connecting line via hole;

Described active layer is arranged at the top that described gate insulation layer correspondence described grid, and covers the region that described grid correspondence completely;

Described etching barrier layer is arranged at the top of described active layer, one end that described etching barrier layer correspondence described active layer offers source electrode via hole, the other end that described etching barrier layer correspondence described active layer offers drain via, and the region that described etching barrier layer correspondence described data wire offers the second connecting line via hole and second source-number connecting line via hole;

Described number-number connecting line, described source electrode, described drain electrode and described pixel electrode are arranged at the top of described etching barrier layer with layer, described source electrode embeds described source electrode via hole and contacts with described active layer, described source electrode is electrically connected to by described first source-number connecting line via hole and described second source-number connecting line via hole with described data wire, and described number-number connecting line is electrically connected to by described the first connecting line via hole and described the second connecting line via hole many described data wires that disconnect; Described drain electrode embeds described drain via and contacts with described active layer, and described drain electrode is electrically connected to described pixel electrode.

A kind of preferred structure is, described array base palte also comprises passivation layer,

Described active layer is arranged on described substrate;

Described gate insulation layer is arranged at the top of described active layer, and the described active layer relative two ends parallel with described grid line are not covered by described gate insulation layer;

Described grid, described grid line and described data wire are arranged at the top of described gate insulation layer with layer, and the area of described grid in orthographic projection direction is less than the area of described active layer;

Described passivation layer is arranged at the top of described grid, described grid line and described data wire, and cover described grid, described grid line and described data wire completely, described passivation layer correspondence one end that described active layer do not cover by described gate insulation layer and is offered source electrode via hole, described passivation layer correspondence the other end that described active layer do not cover by described gate insulation layer and is offered drain via, and the region that described passivation layer correspondence described data wire offers connecting line via hole and source-number connecting line via hole;

Described number-number connecting line, described source electrode, described drain electrode and described pixel electrode are arranged at the top of described passivation layer with layer, described source electrode embeds described source electrode via hole and contacts with described active layer, described source electrode is electrically connected to by source-number connecting line via hole with described data wire, and described number-number connecting line is electrically connected to by connecting line via hole many described data wires that disconnect; Described drain electrode embeds described drain via and contacts with described active layer, and described drain electrode is electrically connected to described pixel electrode.

Preferably, described grid, described grid line and described data wire adopt identical material and form in same composition technique.

Further preferably, described grid, described grid line and described data wire all adopt molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium, chromium or copper to form; Described grid, described grid line and described data wire are single or multiple lift composite lamainated structure, and the thickness range of described grid, described grid line and described data wire is 100-3000nm.

Preferably, described number-number connecting line, described source electrode, described drain electrode and described pixel electrode adopt indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form;

Described active layer adopts metal oxide semiconductor material to form;

Described gate insulation layer is single or multiple lift composite lamainated structure, and described gate insulation layer adopts Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide or aluminum oxide to form;

Described etching barrier layer is single or multiple lift composite lamainated structure, adopts Si oxide, silicon nitride, hafnium oxide or aluminum oxide to form.

Described passivation layer is single or multiple lift composite lamainated structure, adopts Si oxide, silicon nitride, hafnium oxide or aluminum oxide to form.

A display unit, comprises above-mentioned array base palte.

The beneficial effects of the utility model are: in array base palte of the present utility model, active layer adopts metal oxide semiconductor material to form, whole array base palte only needs to adopt four composition techniques to have prepared, and grid line and data wire are formed by the same layer metal level that forms grid, simplified technique, greatly improve production capacity, saved cost.

Accompanying drawing explanation

Fig. 1 is the cutaway view of array base palte in prior art;

Fig. 2-1,2-2 are the structural representation of array base palte in the embodiment of the present invention 1;

Wherein,

Fig. 2-1 is the plane graph of array base palte;

Fig. 2-2 be shown in Fig. 2-1 along D-D to cutaway view;

Fig. 3-1 is the preparation flow figure of array base palte in the embodiment of the present invention 1 to 3-8;

Wherein:

Fig. 3-1 is the plane graph that composition technique formation for the first time comprises the figure of grid, grid line and data wire;

Fig. 3-2 be shown in Fig. 3-1 along A-A to cutaway view;

Fig. 3-3 are the plane graph that composition technique formation for the second time comprises the figure of gate insulation layer, active layer;

Fig. 3-4 be shown in Fig. 3-3 along B-B to cutaway view;

Fig. 3-5 are the plane graph that composition technique formation for the third time comprises the figure of etching barrier layer;

Fig. 3-6 be shown in Fig. 3-5 along C-C to cutaway view;

Fig. 3-7 are that the 4th composition technique forms the plane graph that comprises the figure of counting-count connecting line, source electrode, drain electrode and pixel electrode;

Fig. 3-8 be shown in Fig. 3-7 along D-D to cutaway view;

Fig. 4-1,4-2 are the structural representation of array base palte in the embodiment of the present invention 2;

Wherein:

Fig. 4-1 is the plane graph of array base palte;

Fig. 4-2 be shown in Fig. 4-1 along D-D to cutaway view;

Fig. 5-1 is the preparation flow figure of array base palte in the embodiment of the present invention 2 to 5-8;

Wherein:

Fig. 5-1 is that composition technique forms the plane graph that comprises active layer, gate insulation layer for the first time;

Fig. 5-2 be shown in Fig. 5-1 along A-A to cutaway view;

Fig. 5-3 are the plane graph that composition technique formation for the second time comprises the figure of grid, grid line and data wire;

Fig. 5-4 be shown in Fig. 5-3 along B-B to cutaway view;

Fig. 5-5 are the plane graph that composition technique formation for the third time comprises the figure of passivation layer;

Fig. 5-6 be shown in Fig. 5-5 along C-C to cutaway view;

Fig. 5-7 are that the 4th composition technique forms the plane graph that comprises the figure of counting-count connecting line, source electrode, drain electrode and pixel electrode;

Fig. 5-8 be shown in Fig. 5-7 along D-D to cutaway view;

Fig. 6-1,6-2 are for adopting photoresist mask to carry out the schematic diagram of composition technique in corresponding Fig. 5-1,5-2;

Reference numeral: 1-substrate; 2a-grid; 2b-grid line; 2c-data wire; 2d-public electrode wire; 3-gate insulation layer; 30-gate insulation layer film; 4-active layer; 40-active layer film; 41-photoresist mask; 5-etching barrier layer; 6a-source electrode; 6b-drain electrode; 7-passivation layer; 7a-source electrode via hole; 7b-drain via; 7c-connecting line via hole; 71c-the first connecting line via hole; 72c-the second connecting line via hole; 7d-source-number connecting line via hole; 71d-first source-number connecting line via hole; 72d-second source-number connecting line via hole; 8-pixel electrode; 9-number-number connecting line.

Embodiment

For making those skilled in the art understand better the technical solution of the utility model, below in conjunction with the drawings and specific embodiments, the utility model array base palte and display unit are described in further detail.

A kind of array base palte, comprise substrate and be arranged at many grid lines and many data wires on substrate, described grid line and described data wire are arranged in a crossed manner and described substrate is divided into a plurality of pixel regions, in described pixel region, be provided with thin-film transistor, described thin-film transistor comprises grid, source electrode and drain electrode, described grid is electrically connected to described grid line, described source electrode is electrically connected to described data wire, wherein, grid, grid line and data wire arrange with layer, data wire disconnects in the region intersecting with grid line, the data wire disconnecting is electrically connected to by the number-number connecting line with data wire different layers.

A kind of display unit that comprises above-mentioned array base palte.

Embodiment 1:

As shown in Fig. 2-1 and Fig. 2-2, array base palte comprises that the grid 2a that is cascadingly set on substrate 1 and data wire 2c(are also provided with grid line 2b with layer, not shown in Fig. 2-2), gate insulation layer 3, active layer 4, etching barrier layer 5 and a source electrode 6a who arranges with layer, drain electrode 6b, pixel electrode 8 and number-number connecting line 9.Wherein, grid 2a is electrically connected to grid line 2b, and data wire 2c is electrically connected to source electrode 6a, and grid line 2b and data wire 2c are arranged in a crossed manner and substrate 1 is divided into a plurality of pixel regions.

In the present embodiment, data wire 2c disconnects in the region intersecting with grid line 2b, and the data wire 2c of disconnection is electrically connected to by the number-number connecting line 9 with data wire 2c different layers; Number-number connecting lines 9 are arranged at corresponding data wire 2c with the areas of disconnection of grid line 2b and are connected with the data wire 2c of disconnection.In addition, gate insulation layer 3 is arranged between grid 2a and source electrode 6a and drain electrode 6b; Active layer 4 over against setting, and is positioned at gate insulation layer 3 away from a side of grid 2a with grid 2a; Source electrode 6a and drain electrode 6b next-door neighbour active layer 4 are arranged at the two ends of corresponding active layer 4 and partly overlap in orthographic projection direction with grid 2a.

Concrete, as shown in Fig. 2-1 and Fig. 2-2, the structure of array base palte is as follows:

Grid 2a, grid line 2b and data wire 2c are arranged on substrate 1 with layer;

Gate insulation layer 3 is arranged at the top of grid 2a, grid line 2b and data wire 2c, and complete cover gate 2a, grid line 2b and data wire 2c, the region that gate insulation layer 3 data wire 2c in correspondence offer the first connecting line via hole 71c(correspondence Fig. 2-1 in below the second connecting line via hole 72c, in Fig. 2-2, do not specifically illustrate) and first source-number connecting line via hole 71d(correspondence in Fig. 2-1 second source-number connecting line via hole 72d below, in Fig. 2-2, do not specifically illustrate);

Active layer 4 is arranged at the top that gate insulation layer 3 correspondences grid 2a, and the region that cover gate 2a correspondence completely;

Etching barrier layer 5 is arranged at the top of active layer 4, one end that etching barrier layer 5 correspondences active layer 4 offers source electrode via hole 7a, the other end that etching barrier layer 5 correspondences active layer 4 offers drain via 7b, and the region that etching barrier layer 5 correspondences data wire 2c offers the second connecting line via hole 72c and second source-number connecting line via hole 72d;

Number-number connecting line 9, source electrode 6a, drain electrode 6b and pixel electrode 8 are arranged at the top of etching barrier layer 5 with layer, source electrode 6b embeds source electrode via hole 7a and contacts with active layer 4, source electrode 6a is electrically connected to by first source-number connecting line via hole 71d and second source-number connecting line via hole 72d with data wire 2c, and number-number connecting line 9 is electrically connected to by the first connecting line via hole 71c and the second connecting line via hole 72c many data wire 2c that disconnect; Drain electrode 6b embeds drain via 7b and contacts with active layer 4, and drain electrode 6b is electrically connected to pixel electrode 8.

Preferably, grid 2a, grid line 2b and data wire 2c all adopt molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminium (Al), aluminium neodymium alloy (AlNd), titanium (Ti), chromium (Cr) or copper (Cu) to form, and are preferably molybdenum, aluminium or containing the alloy of molybdenum, aluminium; Grid 2a, grid line 2b and data wire 2c are single or multiple lift composite lamainated structure, and the thickness range of grid 2a, grid line 2b and data wire 2c is 100-3000nm.

Source electrode 6a, drain electrode 6b, pixel electrode 8 and number-number connecting line 9 adopt indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (ITO), indium oxide gallium tin or indium gallium zinc oxide (ITZO) to form.In the present embodiment, source electrode 6a, drain electrode 6b, pixel electrode 8 and number-number connecting line 9, can select the transparent conductive materials such as tin indium oxide, indium oxide gallium zinc, indium zinc oxide, indium gallium zinc oxide to form.

Active layer 4 adopts metal oxide semiconductor material to form, comprise by the material that comprises the elements such as indium (In), gallium (Ga), zinc (Zn), oxygen (O), tin (Sn) and making, wherein must comprise two or more element of oxygen element and other, as indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (InSnO) or indium oxide gallium tin (InGaSnO).

Gate insulation layer 3 is single or multiple lift composite lamainated structure, and gate insulation layer 3 adopts Si oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon nitrogen oxide (SiON) or aluminum oxide (AlOx) to form.

Etching barrier layer 5 is single or multiple lift composite lamainated structure, adopts Si oxide (SiOx), silicon nitride (SiNx), hafnium oxide (SiON) or aluminum oxide (AlOx) to form.

Accordingly, the preparation method of above-mentioned array base palte, be included in and on substrate, form many grid lines and many data wires substrate is divided into the step of a plurality of pixel regions, also be included in the step that forms thin-film transistor in pixel region, thin-film transistor comprises grid, source electrode and drain electrode, grid is electrically connected to grid line, source electrode is electrically connected to data wire, wherein, grid, grid line and data wire adopt same composition technique to be formed on layer, data wire disconnects in the region intersecting with grid line, the data wire disconnecting is electrically connected to data wire by being formed on number-number connecting line of different layers.

Before concrete elaboration, it should be understood that in the utility model, composition technique, can only include photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.Can be according to the corresponding composition technique of formed structure choice in the utility model.

Concrete, the method comprises the steps:

Step S1: adopt one time composition technique, form the figure comprise grid, grid line and data wire on substrate, data wire is in the region disconnection intersecting with grid line.

In this step, as shown in Fig. 3-1, Fig. 3-2, on substrate 1, form electrode metal film, adopt composition technique to form to comprise in grid 2a, grid line 2b(Fig. 3-2 not shown) and the figure of data wire 2c, data wire 2c is in the region disconnection intersecting with grid line 2b.Known from this step, grid 2a, grid line 2b, data wire 2c adopt same layer electrode metal film formed.

Wherein, adopt the method for deposition, sputter or thermal evaporation to form electrode metal film on substrate 1.

Further, at the non-pixel region of array base palte, form when comprising the figure of grid 2a, grid line 2b and data wire 2c, also be formed with public electrode wire 2d, public electrode wire 2d waits until in subsequent technique and forms after public electrode, is electrically connected to public electrode, no longer describes in detail here.

Wherein, cutaway view 3-2 be along A-A in plane graph 3-1 to cutaway view.Here, for illustrating more highlightedly the cross-section structure of array base palte in preparation process in the present embodiment, the ratio setting of cutaway view 3-2 and plane graph 3-1 is slightly different, following cutaway view and each plane graph therewith with.

Step S2: adopt one time composition technique, on the substrate of completing steps S1, form the figure comprise gate insulation layer, and gate insulation layer correspondence grid above form the figure that comprises active layer.

In this step, as shown in Fig. 3-3, Fig. 3-4, on the substrate 1 of completing steps S1, form gate insulation layer film (FGI Deposition), above grid 2a, grid line 2b and data wire 2c, form gate insulation layer film; Then above gate insulation layer film, form active layer film (Active Deposition).Adopt a composition technique to form the figure that comprises gate insulation layer 3 and active layer 4, the region that gate insulation layer 3 correspondences data wire 2c is formed with the first connecting line via hole 71c and first source-number connecting line via hole 71d simultaneously.

Wherein, using plasma strengthens chemical vapour deposition technique (Plasma Enhanced Chemical Vapor Deposition: be called for short PECVD) and forms gate insulation layer film, adopts the methods such as deposition, sputter or thermal evaporation to form active layer film.

Here, because the general transparent material (Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide, aluminum oxide) that adopts of gate insulation layer 3 forms, to the observation of plane graph, can not cause obstruction, therefore in the floor map of Fig. 3-3, omit the signal of gate insulation layer 3, only the corresponding connecting line via hole wherein offered and the position of source-number connecting line via hole of illustrating; Meanwhile, for ease of the position relationship between each layer of structure and each layer in understanding pixel region, each layer in plane graph 3-3 is set to have certain transparency, and following plane graph is same therewith.

Step S3: adopt one time composition technique, form the figure that comprises etching barrier layer on the substrate of completing steps S2.

In this step, as shown in Fig. 3-5, Fig. 3-6, on the substrate of completing steps S2, form etching barrier layer film, adopt a composition technique to form the figure that comprises etching barrier layer 5.One end that etching barrier layer 5 correspondences active layer 4 is formed with source electrode via hole 7a, the other end that etching barrier layer 5 correspondences active layer 4 is formed with drain via 7b, and the region that etching barrier layer 5 correspondences data wire 2c is formed with the second connecting line via hole 72c and second source-number connecting line via hole 72d.

Wherein, adopt deposition, sputter, thermal evaporation or form etching barrier layer film by methods such as special PECVD.The feature of etch stop layer film is that rete contains lower hydrogen content and has good surface characteristic.

Step S4: adopt one time composition technique, comprise the figure of number-number connecting line, source electrode, drain electrode and pixel electrode in the substrate formation of completing steps S3.

In this step, as shown in Fig. 3-7, Fig. 3-8, on the substrate 1 of completing steps S3, form transparency electrode metallic film, adopt one end of composition technique corresponding active layer 4 on etching barrier layer 5 to form source electrode 6a, the other end of active layer 4 in correspondence forms drain electrode 6b, and the region that data wire 2c in correspondence forms number-number connecting line 9, simultaneously, in the side near drain electrode 6b, form pixel electrode 8, pixel electrode 8 is electrically connected to drain electrode 6b.

Wherein: source electrode 6a embeds source electrode via hole 7a and contacts with active layer 4, source electrode 6a and data wire 2c by first source-number connecting line via hole 71d(in Fig. 3-7 corresponding second source-number connecting line via hole 72d below) and second source-number connecting line via hole 72d electrical connection, number-number connecting line 9 by the first connecting line via hole 71c(in Fig. 3-7 corresponding the second connecting line via hole 72c below) and the second connecting line via hole 72c make many data wire 2c electrical connections of disconnection, the data wire 2c of disconnection is linked together; Drain electrode 6b embeds drain via 7b and contacts with active layer 4, and drain electrode 6b is electrically connected to pixel electrode 8.

Wherein, adopt the method for deposition, sputter or thermal evaporation to form electrode metal film, the thickness range of electrode metal film is 20-150nm.Electrode metal film in the present embodiment adopts metal-oxide semiconductor (MOS), concrete can be: indium oxide gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (ITO) or indium oxide gallium tin (InGaSnO) form, for example: adopt tin indium oxide (ITO) material as electrode metal, and the technique that adopts spatter film forming forms amorphous transparency electrode metallic film, then make it crystallization by annealing.In the present embodiment, owing to forming the active layer of thin-film transistor, adopt metal oxide semiconductor material, the electron mobility between source electrode and drain electrode is increased, therefore can obtain the electron mobility between good source electrode and drain electrode.

In the present embodiment, the transparency electrode metallic film that forms pixel electrode has also formed for connecting number-number connecting line of the data wire of disconnection simultaneously, number-number connecting line, by the first connecting line via hole, first source-number connecting line via hole and the second connecting line via hole of offering in etching barrier layer, the second source-number connecting line via hole offered in gate insulation layer, makes the multiple segment data line disconnecting be connected into complete data wire.

As long as it should be understood that here between the data wire 2c that number-number connecting line 9 can make to disconnect and be electrically connected to mutually, the width of logarithm-number connecting line 9 does not limit; Meanwhile, for the position relationship of data wire 2c and the second connecting line via hole 72c is shown preferably, in Fig. 3-7, the width of number-number connecting line 9 is slightly less than the width of data wire 2c.But in actual production technique, the width of number-number connecting line 9 is typically designed to the width that is not less than data wire 2c, to guarantee conduction good between data wire 2c.

The array base palte of the present embodiment, while adopting metal-oxide semiconductor (MOS) as active layer compared to existing technology, need to adopt the preparation that six times composition technique could form array base palte, the present embodiment only needs four preparations that composition technique can complete array base palte, greatly simplify technological process, saved the process time.

A display unit, comprises above-mentioned array base palte.Display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.

Embodiment 2:

In the present embodiment, the thin-film transistor in array base palte is top gate type structure.

As shown in Fig. 4-1 and Fig. 4-2, in the present embodiment, the structure of array base palte is specific as follows:

Active layer 4 is arranged on substrate 1;

Gate insulation layer 3 is arranged at the top of active layer 4, and the active layer 4 relative two ends parallel with grid line 2b are not covered by gate insulation layer 3;

Grid 2a, grid line 2b and data wire 2c are arranged at the top of gate insulation layer 3 with layer, and the area of grid 2a in orthographic projection direction is less than the area of active layer 4;

Passivation layer 7 is arranged at the top of grid 2a, grid line 2b and data wire 2c, and complete cover gate 2a, grid line 2b and data wire 2c, passivation layer 7 correspondences one end that active layer 4 do not cover by gate insulation layer 3 and are offered source electrode via hole 7a, passivation layer 7 correspondences the other end that active layer do not cover by gate insulation layer 3 and are offered drain via 7b, and the region that passivation layer 7 correspondences data wire 2c offers connecting line via hole 7c and source-number connecting line via hole 7d;

Number-number connecting line 9, source electrode 6a, drain electrode 6b and pixel electrode 8 are arranged at the top of passivation layer 7 with layer, source electrode 6a embeds source electrode via hole 7a and contacts with active layer 4, source electrode 6a is electrically connected to by source-number connecting line via hole 7d with data wire 2c, and number-number connecting line 9 is electrically connected to by connecting line via hole 7c many data wire 2c that disconnect; Drain electrode 6b embeds drain via 7b and contacts with active layer 4, and drain electrode 6b is electrically connected to pixel electrode 8.

Accordingly, if Fig. 5-1 is to as shown in 5-8, the preparation method of above-mentioned array base palte specifically comprises the steps:

Step S1: adopt one time composition technique, form the figure that comprises active layer on substrate, and form the figure that comprises gate insulation layer above active layer, the active layer relative two ends parallel with grid line are not covered by gate insulation layer.

In this step, as shown in Fig. 5-1, Fig. 5-2, adopt metal oxide semiconductor material above substrate 1, to form active layer film, metal oxide semiconductor material comprises indium oxide gallium zinc (IGZO), indium oxide (In ₂o ₃), zinc oxide (ZnO) or tin indium oxide zinc (ITZO) etc.

In the present embodiment, on substrate 1, successively form active layer film and gate insulation layer film.Adopt composition technique for the first time to form the figure that comprises active layer 4 and gate insulation layer 3.Wherein, the active layer 4 relative two ends parallel with grid line 2b are not covered by gate insulation layer 3, so that the contacting of active layer 4 and source electrode 6a and drain electrode 6b in subsequent technique.

As a kind of example, as shown in Fig. 6-1, Fig. 6-2, this step more specifically step is as follows:

Step S11: utilize the metal oxide semiconductor films that magnetron sputtering mode deposit thickness scope is 30-50nm (as the active layer film 40 in Fig. 6-1), then utilize the gate insulation layer film that PECVD mode deposit thickness scope is 200-400nm (as the gate insulation layer film 30 in Fig. 6-1);

Step S12: apply one deck photoresist above gate insulation layer film 30, and adopt gray mask plate or half-tone mask plate to photoresist expose, developing process, remove part photoresist completely, go back part reserve part photoresist (concrete removal part completely and part reserve part are determined by the figure of active layer and gate insulation layer) simultaneously, form photoresist mask 41, as in Figure 6-1; Then under the protection of photoresist mask 41, by wet-etching technique, form the figure that comprises active layer 4; And by dry carving technology for the first time, form the part figure that comprises gate insulation layer 3.

Step S13: pass through cineration technics; continuation exposes, develops photoresist, removes the photoresist that part retains, as shown in Fig. 6-2; change the protection range of photoresist mask 41, then by dry carving technology formation for the second time, comprise the full graphics of gate insulation layer 3.

Step S2: adopt one time composition technique, form the figure comprise grid, grid line and data wire on the substrate of completing steps S1, data wire is in the region disconnection intersecting with grid line, and the area of grid in orthographic projection direction is less than the area of active layer.

In this step, as shown in Fig. 5-3, Fig. 5-4, utilize the electrode metal film that magnetron sputtering mode deposit thickness scope is 200-300nm, adopt composition technique for the second time to form the figure that comprises grid 2a, grid line 2b and data wire 2c.

In the present embodiment, electrode metal preferably copper (Cu), the while is aluminium (Al) preferably, the materials such as molybdenum (Mo).

Step S3: adopt one time composition technique, form the figure that comprises passivation layer on the substrate of completing steps S2.

In this step, as shown in Fig. 5-5, Fig. 5-6, adopt the method for deposition, sputter or thermal evaporation to form passivation layer film.Concrete, can utilize the passivation layer film that PECVD mode deposit thickness scope is 200-400nm, then form the figure that comprises passivation layer 7.Wherein, passivation layer 7 correspondences one end that active layer 4 do not cover by gate insulation layer 3 and are formed with source electrode via hole 7a, and passivation layer correspondence the other end that active layer 4 do not cover by gate insulation layer 3 and is formed with drain via 7b; In passivation layer 7, the region of corresponding data wire 2c is formed with connecting line via hole 7c and source-number connecting line via hole 7d.

In the present embodiment, passivation layer 7 is single or multiple lift composite lamainated structure, adopts Si oxide (SiOx), silicon nitride (SiNx), hafnium oxide (SiON) or aluminum oxide (AlOx) to form.

Here, because the general transparent material (Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide, aluminum oxide) that adopts of passivation layer 7 forms, to the observation of plane graph, can not cause obstruction, therefore in the floor map of Fig. 5-5, omit the signal of passivation layer 7, the only corresponding position that source electrode via hole, drain via, data wire via hole and the source-number connecting line via hole wherein offered are shown; Meanwhile, for ease of the position relationship between each layer of structure and each layer in understanding pixel region, each layer in plane graph 5-5 is set to have certain transparency, and following plane graph is same therewith.

In this step, as shown in Fig. 5-7, Fig. 5-8, utilize the transparency electrode metallic film that magnetron sputtering mode deposit thickness scope is 30-200nm, adopt the 4th composition technique to form the figure that comprises number-number connecting line 9, source electrode 6a, drain electrode 6b and pixel electrode 8.

Wherein, source electrode 6a embeds source electrode via hole 7a and contacts with active layer 4, source electrode 6a is electrically connected to by source-number connecting line via hole 7d with data wire 2c, and number-number connecting line 9 is electrically connected to by connecting line via hole 7c many data wire 2c that disconnect, and the data wire 2c of disconnection is linked together; Drain electrode 6b embeds drain via 7b and contacts with active layer 4, and drain electrode 6b is electrically connected to pixel electrode 8.

Adopt the array base palte in the utility model, can form easily TN(Twisted Nematic, twisted-nematic) pattern, VA(Vertical Alignment, vertical orientated) liquid crystal indicator of pattern, can also form OLED display unit.

Simultaneously, as a kind of modification, those skilled in the art will readily appreciate that, on the basis of the utility model array base palte, below transparent pixel electrode or above, adding transparent electrode metal film to form public electrode, is also ADS(ADvanced Super Dimension Switch, senior super dimension field switch technology) other patterns such as pattern.Wherein, ADS pattern is: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal molecule operating efficiency and increased light transmission efficiency.Should be appreciated that equally and be, in the array base palte of modification, pixel electrode can for tabular can be also slit-shaped, corresponding, public electrode can also can be for tabular for slit-shaped, as long as guarantee that the electrode in top is that slit-shaped, the electrode in below are tabular.A senior super dimension switch technology can improve the picture quality of LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).

In array base palte of the present utility model, active layer adopts metal oxide semiconductor material to form, whole array base palte only needs to adopt four composition techniques to have prepared, and grid line and data wire are formed by the same layer metal level that forms grid, simplified technique, greatly improve production capacity, saved cost.

Be understandable that, above execution mode is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection range of the present utility model.

Claims

1. an array base palte, comprise substrate and be arranged at many grid lines and many data wires on described substrate, described grid line and described data wire are arranged in a crossed manner and described substrate is divided into a plurality of pixel regions, in described pixel region, be provided with thin-film transistor, described thin-film transistor comprises grid, source electrode and drain electrode, described grid is electrically connected to described grid line, described source electrode is electrically connected to described data wire, it is characterized in that, described grid, described grid line and described data wire arrange with layer, described data wire disconnects in the region intersecting with described grid line, the described data wire disconnecting is electrically connected to by the number-number connecting line with described data wire different layers.

2. array base palte according to claim 1, it is characterized in that, in described pixel region, be also provided with pixel electrode, described number-number connecting line, described source electrode, described drain electrode and described pixel electrode arrange with layer, and described number-number connecting line is arranged at corresponding described data wire with the areas of disconnection of described grid line and is connected with the described data wire of disconnection.

3. array base palte according to claim 2, is characterized in that, described array base palte also comprises gate insulation layer and active layer, and described gate insulation layer is arranged between described grid and described source electrode and described drain electrode; Described active layer and described grid be over against setting, and be positioned at described gate insulation layer away from a side of described grid; Described source electrode and described drain electrode are close to described active layer and are arranged at the two ends of corresponding described active layer and partly overlap in orthographic projection direction with described grid.

4. array base palte according to claim 3, is characterized in that, described array base palte also comprises etching barrier layer,

5. array base palte according to claim 3, is characterized in that, described array base palte also comprises passivation layer,

Described active layer is arranged on described substrate;

6. according to the array base palte described in any one in claim 3-5, it is characterized in that, described grid, described grid line and described data wire adopt identical material and form in same composition technique.

7. array base palte according to claim 6, is characterized in that, described grid, described grid line and described data wire all adopt molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium, chromium or copper to form; Described grid, described grid line and described data wire are single or multiple lift composite lamainated structure, and the thickness range of described grid, described grid line and described data wire is 100-3000nm.

8. array base palte according to claim 7, is characterized in that, described number-number connecting line, described source electrode, described drain electrode and described pixel electrode adopt indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form; Described active layer adopts metal oxide semiconductor material to form.

9. array base palte according to claim 4, is characterized in that, described gate insulation layer is single or multiple lift composite lamainated structure, and described gate insulation layer adopts Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide or aluminum oxide to form;

10. array base palte according to claim 5, is characterized in that, described gate insulation layer is single or multiple lift composite lamainated structure, and described gate insulation layer adopts Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide or aluminum oxide to form;

11. 1 kinds of display unit, is characterized in that, comprise the array base palte described in claim 1-10 any one.