CN103236440B - Thin-film transistor, array base palte and manufacture method thereof, display unit - Google Patents

Thin-film transistor, array base palte and manufacture method thereof, display unit Download PDF

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Publication number
CN103236440B
CN103236440B CN201310126140.9A CN201310126140A CN103236440B CN 103236440 B CN103236440 B CN 103236440B CN 201310126140 A CN201310126140 A CN 201310126140A CN 103236440 B CN103236440 B CN 103236440B
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substrate
photoresist
reserve area
electrode
film
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CN103236440A (en
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高涛
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201310126140.9A priority Critical patent/CN103236440B/en
Priority to US14/368,308 priority patent/US9711544B2/en
Priority to PCT/CN2013/080646 priority patent/WO2014166181A1/en
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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/321—After treatment
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    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
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    • H01L29/772—Field effect transistors
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    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The embodiment of the invention discloses a kind of thin-film transistor (TFT) and manufacture method thereof, comprise array base palte and the manufacture method thereof of this TFT, and be provided with the display unit of this array base palte, belong to Display Technique field, make Cgs and the Cgd in TFT to reach 0.This TFT comprises substrate, and is arranged at gate electrode, source electrode and the drain electrode on substrate, and the projection of the space between source electrode with drain electrode on substrate overlaps with the projection of gate electrode on substrate.The manufacture method of this TFT comprises: using gate electrode as mask plate, exposes and develop from the back side of substrate to the photoresist substrate, and after development, remaining photoresist is corresponding with the position of gate electrode; Sedimentary origin drain metal film on substrate; Peel off remaining photoresist, also peel off the source-drain electrode metallic film on photoresist simultaneously; Substrate is formed source electrode and drain electrode.The present invention can be applicable to the display unit such as liquid crystal panel, oled panel.

Description

Thin-film transistor, array base palte and manufacture method thereof, display unit
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of thin-film transistor and manufacture method thereof, comprise array base palte and the manufacture method thereof of this thin-film transistor, and be provided with the display unit of this array base palte.
Background technology
Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay is called for short TFT-LCD) has the advantages such as volume is little, low in energy consumption, radiationless, in current field of flat panel displays, occupies leading position.
The conductivity principle of TFT applies high level on grid, makes source electrode and drain electrode by semiconductor channel conducting, thus charged to pixel electrode by data wire.Total capacitance=Cgs+C raceway groove+the Cgd of TFT, wherein Cgs is the electric capacity of the overlapping formation of grid and source electrode, and Cgd is the electric capacity of grid and the overlapping formation of drain electrode, and Cgs and Cgd preferably can reach 0, to reduce the total capacitance of TFT.But, current source electrode, between drain electrode and grid, all there is certain overlapping part, because if the space between source electrode and drain electrode is larger, the electric conductivity of TFT will be affected, and source electrode, not aim between drain electrode with grid, therefore in each TFT, the value of Cgs and Cgd is unfixed, cause the total capacitance of each TFT different, so under the condition that data-signal is equal, the voltage that pixel electrode is charged is also inconsistent, thus causes liquid crystal display to occur the bad phenomenon of colourity inequality.Further, due to the existence of Cgs and Cgd, the driving voltage of TFT is also increased, thus adds the time needed for charging process.
Summary of the invention
Embodiments provide a kind of thin-film transistor and manufacture method thereof, comprise array base palte and the manufacture method thereof of this thin-film transistor, and be provided with the display unit of this array base palte, make Cgs and the Cgd in TFT to reach 0.
For achieving the above object, embodiments of the invention adopt following technical scheme:
One aspect of the present invention provides a kind of thin-film transistor, comprise substrate, and the gate electrode, source electrode and the drain electrode that are arranged on substrate, the projection on the substrate of the space between described source electrode with described drain electrode overlaps with the projection of described gate electrode on substrate.
Preferably, described thin-film transistor is bottom gate thin film transistor.
Further, described thin-film transistor also comprises the gate insulation layer covering described gate electrode, the semiconductor active layer be arranged on described gate insulation layer.
Further, described thin-film transistor also comprises the ohmic contact layer be arranged between semiconductor active layer and source, drain electrode.
The present invention also provides a kind of array base palte, comprises above-mentioned thin-film transistor.
Further, array base palte also comprises and is arranged at transparency conducting layer on described substrate and transparency conductive electrode, and described transparency conducting layer is arranged at below the gate electrode of described thin-film transistor, and described transparency conductive electrode and described transparency conducting layer are arranged with layer.
Preferably, described transparency conductive electrode is electrically connected with the drain electrode of described thin-film transistor.
The present invention provides a kind of manufacture method of thin-film transistor on the other hand, comprises the following steps:
Substrate is formed gate electrode, gate insulation layer, semiconductor active layer and ohmic contact layer;
Using described gate electrode as mask plate, expose and develop from the back side of described substrate to the photoresist described substrate, after development, remaining photoresist is corresponding with the position of described gate electrode;
Sedimentary origin drain metal film on the substrate;
Peel off described remaining photoresist;
Described ohmic contact layer is etched, forms the space between the source electrode of thin-film transistor and drain electrode;
Form source electrode and drain electrode on the substrate.
The present invention also provides a kind of manufacture method of array base palte, comprises the following steps:
Substrate is formed gate electrode, grid line, gate insulation layer, semiconductor active layer, ohmic contact layer and transparency conductive electrode;
Using described gate electrode as mask plate, expose and develop from the back side of described substrate to the photoresist described substrate, after development, remaining photoresist is corresponding with the position of described gate electrode;
Sedimentary origin drain metal film on the substrate;
Peel off described remaining photoresist;
Described ohmic contact layer is etched, forms the space between the source electrode of thin-film transistor and drain electrode;
Form source electrode, drain electrode, data wire and passivation layer on the substrate.
Preferably, describedly on substrate, form grid, grid line, gate insulation layer, semiconductor active layer, ohmic contact layer and transparency conductive electrode, specifically comprise:
Deposit transparent conductive film and gate metal film successively on substrate;
Apply one deck photoresist on the substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the corresponding gate electrode region of complete reserve area and grid region, the corresponding transparency conductive electrode region of half reserve area, all the other are for remove region completely;
The gate metal film and transparent conductive film of removing region is completely etched away by wet-etching technology;
Cineration technics is carried out to remaining photoresist, removes the photoresist of half reserve area;
The gate metal film of half reserve area is etched away by wet-etching technology;
Peel off the photoresist of complete reserve area;
Deposit gate insulation layer film, semiconductor active layer film and ohmic contact layer film successively on the substrate;
Apply one deck photoresist on the substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the region, silicon island of the corresponding thin-film transistor of complete reserve area, the corresponding grid region of half reserve area, all the other are for remove region completely;
Ohmic contact layer film, semiconductor active layer film and the gate insulation layer film of removing region is completely etched away by dry etch process;
Cineration technics is carried out to remaining photoresist, removes the photoresist of half reserve area;
Ohmic contact layer film and the semiconductor active layer film of half reserve area is etched away by dry etch process.
Preferably, describedly form source electrode, drain electrode, data wire and passivation layer on the substrate, specifically comprise:
Deposit passivation layer film on the substrate;
Apply one deck photoresist on the substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the corresponding region, TFT silicon island of complete reserve area, half reserve area respective data lines region, all the other are for remove region completely;
The passivation layer film removing region is completely etched away by dry etch process;
The source-drain electrode metallic film removing region is completely etched away by wet-etching technology;
Cineration technics is carried out to remaining photoresist, removes the photoresist of half reserve area;
The passivation layer film of half reserve area is etched away by dry etch process;
Peel off the photoresist of complete reserve area.
The present invention also provides a kind of display unit, on the other hand comprising above-mentioned array base palte.
Compared with prior art, technique scheme tool provided by the present invention has the following advantages: in the manufacture method of array base palte provided by the invention, using lighttight gate electrode as mask plate, expose photoresist from the back side of substrate and develop, after development, remaining photoresist is corresponding with the position of gate electrode.While peeling off this remaining photoresist, deposition source-drain electrode metallic film on a photoresist also can be removed, therefore the space between formed source electrode and drain electrode corresponds to the position of gate electrode just, namely the projection of this space on substrate overlaps with gate electrode just, then source electrode, just there is not overlapping part between drain electrode and gate electrode, Cgs and Cgd is made to reach 0, thus avoid the bad phenomenon of colourity inequality, also reduce the driving voltage of TFT, shorten the time needed for charging process.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described.
The structural representation of the thin-film transistor that Fig. 1 provides for embodiments of the invention;
The structural representation of the array base palte that Fig. 2 provides for embodiments of the invention;
The manufacture process schematic diagram of the manufacture method of the array base palte that Fig. 3 a to Fig. 3 g provides for embodiments of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.
As shown in Figure 1, the thin-film transistor (TFT) that the embodiment of the present invention provides, comprise substrate 1, and be arranged at gate electrode 2, source electrode 41 and the drain electrode 42 on substrate 1, the projection on substrate 1 of the space between source electrode 41 with drain electrode 42 overlaps with the projection of gate electrode 2 on substrate.
Preferably, the thin-film transistor that the embodiment of the present invention provides is bottom gate thin film transistor, and namely gate electrode 2 is positioned at the below of source electrode 41 and drain electrode 42.Further, this TFT also comprises the gate insulation layer 3 of covering grid electrode 2, the semiconductor active layer 51 be arranged on gate insulation layer 3, and is arranged at the ohmic contact layer 52 between semiconductor active layer 51 and source motor 41, drain electrode 42.
Below this TFT is further described in conjunction with array base palte:
As shown in Figure 2, the array base palte that the embodiment of the present invention provides comprises the TFT in above-described embodiment, specifically comprises substrate 1, gate electrode 2, grid line (not shown), gate insulation layer 3, semiconductor active layer 51, ohmic contact layer 52, source electrode 41, drain electrode 42, data wire (not shown).In addition, this array base palte further comprises and is arranged at transparency conducting layer 60 on substrate 1 and transparency conductive electrode 61, and below the gate electrode 2 that transparency conducting layer 60 is arranged at, transparency conductive electrode 61 and transparency conducting layer 60 are arranged with layer.
The present embodiment is for twisted nematic (TwistedNematic, TN) liquid crystal panel, and as shown in Figure 2, transparency conductive electrode 61, as pixel electrode, is electrically connected with the drain electrode 42 of TFT.
Certainly, technical scheme of the present invention also can be applied in conversion hysteria (ADvancedsuperDimensionSwitch, the ADSDS) liquid crystal panel of senior super dimension field, and so transparency conductive electrode both as pixel electrode, can be electrically connected with drain electrode; Also as public electrode, can not be electrically connected with drain electrode.ADSDS(is called for short ADS) be BOE's autonomous innovation be representative with wide viewing angle technology core technology is referred to as.ADS is plane electric fields wide viewing angle core technology-senior super dimension field switch technology (ADvancedSuperDimensionSwitch), the electric field that its core technology characteristic description is produced for: the electric field produced by gap electrode edge in same plane and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell that between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thus improve liquid crystal operating efficiency and increase light transmission efficiency.Senior super dimension field switch technology can improve the picture quality of TFT-LCD product, have high-resolution, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples (pushMura).For different application, the improvement opportunity of ADS technology has high permeability I-ADS technology, high aperture H-ADS and high-resolution S-ADS technology etc.
Further, source electrode 41, drain electrode 42 and active layer are also coated with passivation layer 7, and passivation layer 7 can play a protective role to TFT, prevents TFT impaired, can also play insulating effect simultaneously, avoids the extraneous signal of telecommunication to produce interference to TFT.
The embodiment of the present invention additionally provides the manufacture method of above-mentioned TFT, comprises the following steps:
S11: form gate electrode, gate insulation layer, semiconductor active layer and ohmic contact layer on substrate.
S12: using gate electrode as mask plate, exposes the photoresist substrate from the back side of substrate and develops, and after development, remaining photoresist is corresponding with the position of gate electrode.
S13: sedimentary origin drain metal film on substrate.
S14: peel off remaining photoresist.
S15: etch ohmic contact layer, forms the space between the source electrode of thin-film transistor and drain electrode.
S16: form source electrode and drain electrode on substrate.
Below in conjunction with the manufacture method of the array base palte that the embodiment of the present invention provides, the manufacture method of this TFT is described in detail:
The manufacture method of the array base palte that the embodiment of the present invention provides, comprises the following steps:
S1: form gate electrode, grid line, gate insulation layer, semiconductor active layer, ohmic contact layer and pixel electrode (i.e. transparency conductive electrode) on substrate.
In the embodiment of the present invention, utilize gray tone mask plate to carry out the patterning processes of substrate, specifically comprise the following steps:
S101: deposit transparent conductive film and gate metal film successively on substrate.
Concrete, substrate utilize magnetron sputtering apparatus deposit layer of transparent conductive film and one deck grid metal film successively.Wherein, the composition of transparent conductive film can be tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide etc., and thickness can be metal film can be one or more laminated films formed in the metals such as molybdenum (Mo), aluminium (Al), copper (Cu), tungsten (W), and thickness is
S102: apply one deck photoresist on substrate, then gray tone (or halftoning) mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the corresponding gate electrode region of complete reserve area and grid region, half reserve area respective pixel electrode zone, all the other are for remove region completely.
S103: etched away the gate metal film and transparent conductive film of removing region completely by wet-etching technology.Namely the gate metal film beyond gate electrode region, grid region and pixel electrode area and transparent conductive film are all etched away, define gate electrode and grid line.
S104: carry out cineration technics to remaining photoresist, removes the photoresist of half reserve area.Meanwhile, the photoresist of complete reserve area has also been removed certain thickness, but does not affect the function of photoresist in subsequent step of complete reserve area.
S105: the gate metal film being etched away half reserve area by wet-etching technology.Namely the gate metal film of pixel electrode area is etched away, expose transparent conductive film, form pixel electrode.
S106: the photoresist peeling off complete reserve area.
So far, gray tone mask plate patterning processes terminates for the first time, as shown in Figure 3 a, in this patterning processes, defines gate electrode 2, grid line (not shown) and pixel electrode 61 on substrate 1.
S107: deposit gate insulation layer film, semiconductor active layer film and ohmic contact layer film on substrate successively.
Concrete, substrate utilizes the method deposition gate insulation layer film of plasma enhanced chemical vapor deposition (PECVD), and its composition can be SiN xand SiO xin one, or its compound of two kinds, thickness can be and then deposited semiconductor active layer film, its thickness can be last deposit ohmic contact layer film, its thickness can be
S108: apply one deck photoresist on substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the region, silicon island of the corresponding TFT of complete reserve area, the corresponding grid region of half reserve area, all the other are for remove region completely.
S109: etched away ohmic contact layer film, semiconductor active layer film and the gate insulation layer film of removing region completely by dry etch process.
Wherein, the reacting gas that semiconductor active layer film is corresponding can be SiH 4and H 2mist or SiH 2cl 2and H 2mist; The reacting gas that ohmic contact layer film is corresponding can be SiH 4, PH 3and H 2mist or SiH 2cl 2, PH 3and H 2mist; The reacting gas of gate insulation layer film can be SiH 4, NH 3and N 2mist or SiH 2cl 2, NH 3and N 2mist.Like this, just only can retain the ohmic contact layer 52 of region, TFT silicon island and grid region, semiconductor active layer 51 and gate insulation layer 3, form array base palte as shown in Figure 3 b.
S110: carry out cineration technics to remaining photoresist, removes the photoresist of half reserve area.Similar to above-mentioned steps S104, while removing the photoresist of half reserve area, the photoresist of complete reserve area has also been removed certain thickness, but does not affect the function of photoresist in subsequent step of complete reserve area.
S111: the ohmic contact layer film and the semiconductor active layer film that are etched away half reserve area by dry etch process.Namely the ohmic contact layer film of grid region and semiconductor active layer film are etched away, form the grid line being coated with gate insulation layer.
It should be noted that the step S1 in the embodiment of the present invention also can adopt common mask plate patterning processes to form gate electrode, grid line, gate insulation layer, semiconductor active layer, ohmic contact layer and pixel electrode.Such as, gate electrode and grid line is formed by first time mask plate patterning processes, then on substrate, gate insulation layer is deposited, on gate insulation layer, pixel electrode is formed again by second time mask plate patterning processes, semiconductor active layer film and the ohmic contact layer film in region, TFT silicon island is formed finally by third time mask plate patterning processes, and retain remaining photoresist on ohmic contact layer film, so that use in step S2 afterwards.
S2: as shown in Figure 3 c, using gate electrode 2 as mask plate, expose and develop from the back side of substrate 1 to the photoresist substrate 1, after development, remaining photoresist 8 is corresponding with the position of gate electrode 2.
Because gate electrode 2 is formed by metal material, gate electrode 2 is lighttight, and using lighttight gate electrode 2 as mask plate, expose and develop from the back side of substrate 1 to photoresist, then after development, remaining photoresist 8 is corresponding with the position of gate electrode 2.
S3: as shown in Figure 3 d, on substrate 1 sedimentary origin drain metal film 4.
Substrate utilizes the method sedimentary origin drain metal film 4 of magnetron sputtering or hot evaporation, and the material selected by source-drain electrode metallic film 4 can be identical with gate metal film, and thickness can be
S4: peel off remaining photoresist on doped semiconductor films.
In this step, adopt conventional photoresist lift off method.Should be noted that, Fig. 3 d is only schematic diagram, in actual manufacture process, the thickness of photoresist 8 is micron-sized, and the thickness of source-drain electrode metallic film 4 is nano level, namely the thickness of photoresist 8 will be far longer than the thickness of source-drain electrode metallic film 4, therefore while stripping photoresist 8, the source-drain electrode metallic film 4 be deposited on photoresist 8 also can be removed, and the space in the TFT formed between source electrode and drain electrode corresponds to the position of grid 2 just.
S5: etch ohmic contact layer, forms the space between the source electrode of TFT and drain electrode, as shown in Figure 3 e.
Concrete, etched away the ohmic contact layer 52 of above-mentioned gap by dry etch process, form the space between the source electrode of TFT and drain electrode.In the etching process of reality, in order to ensure that ohmic contact layer 52 can be carved by eating away completely, the time of etching can be increased as far as possible, and make semiconductor active layer 51 also have sub-fraction to be etched away, but not affecting the electrical property of TFT.
From step S107 so far, second time gray tone mask plate patterning processes terminates, as shown in Figure 3 e, in this patterning processes on the basis of first time patterning processes, define the space between the source electrode of TFT and drain electrode, and the gate insulation layer 3 of covering gate electric wire 2, and the projection on substrate 1 of this space overlaps with gate electrode 2 just.
S6: form source electrode, drain electrode, data wire and passivation layer on substrate.
In the embodiment of the present invention, continue to utilize gray tone mask plate to carry out the patterning processes of substrate, specifically comprise the following steps:
S601: as illustrated in figure 3f, on substrate 1 deposit passivation layer 7 film.
Concrete, utilize the method for PECVD to deposit one deck passivation layer 7 film on substrate 1, its composition can be SiN xand SiO xin one, or its compound of two kinds, thickness can be
S602: apply one deck photoresist on substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the corresponding region, TFT silicon island of complete reserve area, half reserve area respective data lines region, all the other are for remove region completely.
S603: etched away the passivation layer film removing region completely by dry etch process.
The reacting gas of passivation layer film can be SiH 4, NH 3and N 2mist or SiH 2cl 2, NH 3and N 2mist.The passivation layer film that this makes it possible to beyond by region, TFT silicon island and data wire region all etches away, and forms the TFT silicon island being coated with passivation layer.
S604: etched away the source-drain electrode metallic film removing region completely by wet-etching technology.
Pixel electrode is also positioned at this and removes within region completely, so after etching away the source-drain electrode metallic film removing region completely, has also just etched away the source-drain electrode metallic film of pixel electrode surface thus has exposed pixel electrode.
S605: carry out cineration technics to remaining photoresist, removes the photoresist of half reserve area.Similar to above-mentioned steps S104, S110, while removing the photoresist of half reserve area, the photoresist of complete reserve area has also been removed certain thickness, but does not affect the function of photoresist in subsequent step of complete reserve area.
S606: the passivation layer film being etched away half reserve area by dry etch process.
Utilize the method identical with above-mentioned steps S603, etch away the passivation layer film in data wire region, expose source-drain electrode metallic film, form data wire.
S607: peel off the remaining photoresist of complete reserve area, forms array base palte as shown in figure 3g.
From step S601 so far, gray tone mask plate patterning processes terminates for the third time, in this patterning processes on the basis of front twice patterning processes, define source electrode 41, drain electrode 42, data wire (not shown), and cover the passivation layer 7 on TFT silicon island.
Certainly, the step S6 in the embodiment of the present invention also can adopt common mask plate patterning processes to form source electrode, drain electrode, data wire and passivation layer.
In the array base palte that the embodiment of the present invention provides and manufacture method thereof, using lighttight gate electrode as mask plate, expose photoresist from the back side of substrate and develop, after development, remaining photoresist is corresponding with the position of gate electrode.While peeling off this remaining photoresist, deposition source-drain electrode metallic film on a photoresist also can be removed, therefore the space between formed source electrode and drain electrode corresponds to the position of gate electrode just, namely the projection of this space on substrate overlaps with gate electrode just, then source electrode, just there is not overlapping part between drain electrode and gate electrode, Cgs and Cgd is made to reach 0, thus avoid the bad phenomenon of colourity inequality, also reduce the driving voltage of TFT, shorten the time needed for charging process.
In addition, the embodiment of the present invention utilizes gray tone mask plate patterning processes, only needs to carry out the manufacture that 3 times patterning processes can complete array base palte, improves the production efficiency of array base palte, and reduce the production cost of array base palte.
The embodiment of the present invention also provides a kind of display unit, comprising the array base palte that the invention described above embodiment provides.This display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer.
The display unit provided due to the embodiment of the present invention has identical technical characteristic with the array base palte that the invention described above embodiment provides, so also can produce identical technique effect, solves identical technical problem.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims (2)

1. a manufacture method for array base palte, is characterized in that, comprising:
Substrate is formed gate electrode, grid line, gate insulation layer, semiconductor active layer, ohmic contact layer and transparency conductive electrode;
Using described gate electrode as mask plate, expose and develop from the back side of described substrate to the photoresist described substrate, after development, remaining photoresist is corresponding with the position of described gate electrode;
Sedimentary origin drain metal film on the substrate;
Peel off described remaining photoresist;
Described ohmic contact layer is etched, forms the space between the source electrode of thin-film transistor and drain electrode;
Form source electrode, drain electrode, data wire and passivation layer on the substrate;
Wherein, describedly on substrate, form gate electrode, grid line, gate insulation layer, semiconductor active layer, ohmic contact layer and transparency conductive electrode, specifically comprise:
Deposit transparent conductive film and gate metal film successively on substrate;
Apply one deck photoresist on the substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the corresponding gate electrode region of complete reserve area and grid region, the corresponding transparency conductive electrode region of half reserve area, all the other are for remove region completely;
The gate metal film and transparent conductive film of removing region is completely etched away by wet-etching technology;
Cineration technics is carried out to remaining photoresist, removes the photoresist of half reserve area;
The gate metal film of half reserve area is etched away by wet-etching technology;
Peel off the photoresist of complete reserve area;
Deposit gate insulation layer film, semiconductor active layer film and ohmic contact layer film successively on the substrate;
Apply one deck photoresist on the substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the region, silicon island of the corresponding thin-film transistor of complete reserve area, the corresponding grid region of half reserve area, all the other are for remove region completely;
Ohmic contact layer film, semiconductor active layer film and the gate insulation layer film of removing region is completely etched away by dry etch process;
Cineration technics is carried out to remaining photoresist, removes the photoresist of half reserve area;
Ohmic contact layer film and the semiconductor active layer film of half reserve area is etched away by dry etch process.
2. the manufacture method of array base palte according to claim 1, is characterized in that, describedly forms source electrode, drain electrode, data wire and passivation layer on the substrate, specifically comprises:
Deposit passivation layer film on the substrate;
Apply one deck photoresist on the substrate, then gray tone mask plate is utilized to carry out exposing and developing, photoresist after development forms complete reserve area, half reserve area and removes region completely, wherein, the corresponding region, thin-film transistor silicon island of complete reserve area, half reserve area respective data lines region, all the other are for remove region completely;
The passivation layer film removing region is completely etched away by dry etch process;
The source-drain electrode metallic film removing region is completely etched away by wet-etching technology;
Cineration technics is carried out to remaining photoresist, removes the photoresist of half reserve area;
The passivation layer film of half reserve area is etched away by dry etch process;
Peel off the photoresist of complete reserve area.
CN201310126140.9A 2013-04-12 2013-04-12 Thin-film transistor, array base palte and manufacture method thereof, display unit Expired - Fee Related CN103236440B (en)

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