CN104617039A - Array substrate, and manufacture method and display device thereof - Google Patents
Array substrate, and manufacture method and display device thereof Download PDFInfo
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- CN104617039A CN104617039A CN201510041228.XA CN201510041228A CN104617039A CN 104617039 A CN104617039 A CN 104617039A CN 201510041228 A CN201510041228 A CN 201510041228A CN 104617039 A CN104617039 A CN 104617039A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate, and a manufacture method and a display device thereof, and belongs to the display field. The manufacture method of the array substrate includes: forming a protection layer on a substrate of a TFT (thin film transistor), and forming a first electrode on the protection layer; forming a passive layer on a substrate of the first electrode, and forming a first via hole which runs through the passive layer and the protection layer and exposes a drain electrode of the TFT, and a second via hole which runs through the passive layer and exposes a portion of the first electrode; forming a conductive connection wire connected with the drain electrode of the TFT and the first electrode through the first via hole and the second via hole on the passive layer. The array substrate, and the manufacture method and the display device thereof can prevent pollution on a TFT channel when a pixel electrode is formed on the premise of not adding a picture composition technology, guarantees product quality, and further can perform plasma processing on the TFT channel, can reduce a leakage current of the TFT, and improves the product quality.
Description
Technical field
The present invention relates to display field, refer to a kind of array base palte and preparation method thereof, display unit especially.
Background technology
According to the direction of an electric field driving liquid crystal, thin-film transistor LCD device (TFT-LCD, Thin FilmTransistor Liquid Crystal Display) is divided into vertical electric field type and horizontal electric field type.Wherein, vertical electric field type TFT-LCD comprises: twisted-nematic (TN, Twist Nematic) type TFT-LCD; Horizontal electric field type TFT-LCD comprises: senior super Wei Chang conversion (ADvanced Super Dimension Switch, AD-SDS are called for short ADS) type TFT-LCD, plane switches (IPS, In Plane Switching) type TFT-LCD.
ADS technology is that the electric field that the electric field and gap electrode layer that are produced by gap electrode edge in same plane and plate electrode interlayer are produced forms multi-dimensional electric field, make in liquid crystal cell that between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thus improve liquid crystal operating efficiency and increase light transmission efficiency.Senior super dimension field switch technology can improve the picture quality of TFT-LCD product, have high-resolution, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples.
For different application, the improvement opportunity of ADS technology has high permeability I-ADS technology, high aperture H-ADS technology and high-resolution S-ADS technology etc.Wherein, the structure of the array base palte of existing H-ADS display mode as shown in Figure 1, is made up of substrate 1, gate electrode 2, public electrode wire 3, gate insulation layer 4, active layer 5, source electrode 6, drain electrode 7, pixel electrode 8, passivation layer 9 and public electrode 10.Wherein, pixel electrode adopts the first transparency conducting layer to be formed, and public electrode adopts the second transparency conducting layer to be formed.
The preparation flow of the array base palte of existing H-ADS display mode is: form grid line, public electrode wire and gate electrode by patterning processes; Active layer, source electrode, drain electrode and data wire is formed by patterning processes; Pixel electrode is formed by patterning processes; The passivation layer including via hole is formed by patterning processes; Public electrode is formed by patterning processes.
Wherein, after the making of thin-film transistor, TFT raceway groove can all nakedly be exposed on the external, impurity can be introduced to TFT raceway groove when utilizing transparency conducting layer to form pixel electrode by patterning processes, cause TFT raceway groove to pollute, simultaneously in residual, the raceway groove of etching liquid, transparency conducting layer is residual also can cause TFT raceway groove to pollute.And TFT raceway groove decides the characteristic of TFT, the pollution of TFT raceway groove can cause TFT characteristic abnormal, affects properties of product.
Before including the passivation layer of via hole by patterning processes formation, if carry out plasma treatment to TFT raceway groove, the leakage current of TFT can be reduced, improve product quality.But the pixel electrode that plasma treatment can cause transparency conducting layer to be formed is reduced, produce vaporific bad.Therefore the array base palte of existing H-ADS display mode can not carry out plasma treatment to TFT raceway groove, cause TFT leakage current to raise, affect product quality.
In order to solve the problem; existing conventional solution after forming source electrode, drain electrode and data wire by patterning processes, deposits layer protective layer protect TFT; and composition formation protective layer via hole is carried out to protective layer; afterwards when being utilized transparency conducting layer to form pixel electrode by patterning processes; pixel electrode is connected with drain electrode by protective layer via hole; but need the patterning processes of extra protective layer like this; add the patterning processes number of times making array base palte, improve the complexity of array base palte manufacture craft.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, display unit, under the prerequisite not increasing patterning processes, can avoiding the pollution caused TFT raceway groove when forming pixel electrode, ensureing product quality; And plasma treatment can be carried out to TFT raceway groove, the leakage current of TFT can be reduced, improve product quality.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
On the one hand, a kind of manufacture method of array base palte is provided, comprises:
The substrate being formed with thin-film transistor forms protective layer, and form the first electrode on described protective layer;
The substrate being formed with described first electrode forms passivation layer, and is formed and run through described passivation layer and described protective layer, expose the first via hole of the drain electrode of described thin-film transistor and run through described passivation layer, expose the second via hole of described first electrode of part;
Described passivation layer is formed and is connected the drain electrode of described thin-film transistor and the conductive connecting of described first electrode by described first via hole with described second via hole.
Further, described passivation layer is also formed with the second electrode, described second electrode and described conductive connecting are by being formed with a patterning processes.
Further, described on the substrate being formed with thin-film transistor, form protective layer before also comprise:
Plasma treatment is carried out to the raceway groove of described thin-film transistor.
Further, described first electrode is pixel electrode, and described second electrode is public electrode, and described manufacture method specifically comprises:
Described protective layer deposits the first transparency conducting layer, utilizes described first transparency conducting layer to form described pixel electrode by a patterning processes;
Deposit passivation layer on the substrate being formed with described pixel electrode, formed by patterning processes run through passivation layer and described protective layer, the first via hole of exposing the drain electrode of described thin-film transistor and run through described passivation layer, expose the second via hole of the described pixel electrode of part;
The substrate being formed with described passivation layer deposits the second transparency conducting layer, described second transparency conducting layer is utilized to form described public electrode and described conductive connecting by a patterning processes, described conductive connecting is connected with described drain electrode by described first via hole, and is connected with described pixel electrode by described second via hole.
Further, form described thin-film transistor to comprise:
Described substrate is provided;
The gate electrode of described thin-film transistor is formed on the substrate by patterning processes;
The substrate being formed with described gate electrode forms gate insulation layer;
Described gate insulation layer is formed the figure of active layer;
The substrate being formed with described active layer is formed by patterning processes source electrode and the drain electrode of described thin-film transistor.
The embodiment of the present invention additionally provides a kind of array base palte, and make for adopting above-mentioned manufacture method and obtain, described array base palte comprises:
Be positioned at the thin-film transistor on substrate;
Be positioned at the protective layer on the substrate being formed with described thin-film transistor;
Be positioned at the first electrode on described protective layer;
Be positioned at the passivation layer on the substrate being formed with described first electrode;
Be positioned on described passivation layer, by the first via hole and be connected the drain electrode of described thin-film transistor and the conductive connecting of described first electrode with the second via hole; wherein; described first via hole runs through described passivation layer and described protective layer, exposes the drain electrode of described thin-film transistor, and described second via hole runs through described passivation layer, exposes described first electrode of part.
Further, described array base palte also comprises:
Be positioned at the second electrode on described passivation layer.
Further; described first electrode is pixel electrode; described second electrode is public electrode; described first via hole runs through described passivation layer and described protective layer, exposes the drain electrode of described thin-film transistor; described second via hole runs through described passivation layer, exposes the described pixel electrode of part; described conductive connecting is connected with described drain electrode by described first via hole, and is connected with described pixel electrode by described second via hole.
Further, the thickness of described protective layer is
The embodiment of the present invention additionally provides a kind of display unit, comprises above-mentioned array base palte.
Embodiments of the invention have following beneficial effect:
In such scheme; after substrate forms thin-film transistor; thin-film transistor is formed layer protective layer protect thin-film transistor; and form the first electrode on the protection layer; afterwards composition is carried out to passivation layer and form via hole; and form conductive connecting over the passivation layer, make conductive connecting can be connected the drain electrode of the first electrode and thin-film transistor by via hole.Technical scheme of the present invention need not adopt special patterning processes to carry out composition to protective layer; but pass through figure and the via hole of a patterning processes formation passivation layer; can under the prerequisite not increasing patterning processes; avoid pollution TFT raceway groove caused when formation the first electrode, ensure product quality.
Accompanying drawing explanation
Fig. 1 is the structural representation of the array base palte of existing H-ADS display mode;
Fig. 2 is the schematic diagram after the embodiment of the present invention forms gate electrode and public electrode wire on substrate;
Fig. 3 is the schematic diagram after the embodiment of the present invention is formed with active layer, source electrode and drain electrode;
Fig. 4 is the schematic diagram after the embodiment of the present invention forms protective layer;
Fig. 5 is the schematic diagram after the embodiment of the present invention forms pixel electrode;
Fig. 6 is the schematic diagram after the embodiment of the present invention one forms passivation layer;
Fig. 7 is the schematic diagram after the embodiment of the present invention one forms public electrode;
Fig. 8 is the schematic diagram after the embodiment of the present invention two forms passivation layer;
Fig. 9 is the schematic diagram after the embodiment of the present invention two forms public electrode.
Reference numeral
1 underlay substrate 2 gate electrode 3 public electrode wire 4 gate insulation layer
5 active layer 6 source electrode 7 drain electrode 8 pixel electrodes
9 passivation layer 10 public electrode 11 protective layer 12 conductive connectings
Embodiment
For embodiments of the invention will be solved technical problem, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display unit, under the prerequisite not increasing patterning processes, can avoiding the pollution caused TFT raceway groove when forming pixel electrode, ensureing product quality; And plasma treatment can be carried out to TFT raceway groove, the leakage current of TFT can be reduced, improve product quality.
Embodiment one
Present embodiments provide a kind of manufacture method of array base palte, comprising:
The substrate being formed with thin-film transistor forms protective layer, and form the first electrode on described protective layer;
The substrate being formed with described first electrode forms passivation layer, and is formed and run through described passivation layer and described protective layer, expose the first via hole of the drain electrode of described thin-film transistor and run through described passivation layer, expose the second via hole of described first electrode of part;
Described passivation layer is formed and is connected the drain electrode of described thin-film transistor and the conductive connecting of described first electrode by described first via hole with described second via hole.
After the present embodiment forms thin-film transistor on substrate; thin-film transistor is formed layer protective layer protect thin-film transistor; and form the first electrode on the protection layer; afterwards composition is carried out to passivation layer and form via hole; and form conductive connecting over the passivation layer, make conductive connecting can be connected the drain electrode of the first electrode and thin-film transistor by via hole.Technical scheme of the present invention need not adopt special patterning processes to carry out composition to protective layer; but pass through figure and the via hole of a patterning processes formation passivation layer; can under the prerequisite not increasing patterning processes; avoid pollution TFT raceway groove caused when formation the first electrode, ensure product quality.
Further, described passivation layer is also formed with the second electrode, described second electrode and described conductive connecting are by being formed with a patterning processes.
Further, described on the substrate being formed with thin-film transistor, form protective layer before also comprise:
Plasma treatment is carried out to the raceway groove of described thin-film transistor.Because plasma treatment is before formation first electrode, therefore can not impact the first electrode, the plasma treatment of carrying out TFT raceway groove can reduce the leakage current of TFT, improves product quality.
In one specific embodiment, described first electrode is pixel electrode, and described second electrode is public electrode, and described manufacture method specifically comprises:
Described protective layer deposits the first transparency conducting layer, utilizes described first transparency conducting layer to form described pixel electrode by a patterning processes;
Deposit passivation layer on the substrate being formed with described pixel electrode, formed by patterning processes run through passivation layer and described protective layer, the first via hole of exposing the drain electrode of described thin-film transistor and run through described passivation layer, expose the second via hole of the described pixel electrode of part;
The substrate being formed with described passivation layer deposits the second transparency conducting layer, described second transparency conducting layer is utilized to form described public electrode and described conductive connecting by a patterning processes, described conductive connecting is connected with described drain electrode by described first via hole, and is connected with described pixel electrode by described second via hole.
Further, form described thin-film transistor to comprise:
Described substrate is provided;
The gate electrode of described thin-film transistor is formed on the substrate by patterning processes;
The substrate being formed with described gate electrode forms gate insulation layer;
Described gate insulation layer is formed the figure of active layer;
The substrate being formed with described active layer is formed by patterning processes source electrode and the drain electrode of described thin-film transistor.
Embodiment two
Present embodiments provide a kind of array base palte, make for adopting above-mentioned manufacture method and obtain, described array base palte comprises:
Be positioned at the thin-film transistor on substrate;
Be positioned at the protective layer on the substrate being formed with described thin-film transistor;
Be positioned at the first electrode on described protective layer;
Be positioned at the passivation layer on the substrate being formed with described first electrode;
Be positioned on described passivation layer, by the first via hole and be connected the drain electrode of described thin-film transistor and the conductive connecting of described first electrode with the second via hole; wherein; described first via hole runs through described passivation layer and described protective layer, exposes the drain electrode of described thin-film transistor, and described second via hole runs through described passivation layer, exposes described first electrode of part.
The present embodiment forms layer protective layer and protects thin-film transistor on thin-film transistor; and form the first electrode on the protection layer; afterwards composition is carried out to passivation layer and form via hole; and form conductive connecting over the passivation layer, make conductive connecting can be connected the drain electrode of the first electrode and thin-film transistor by via hole.Technical scheme of the present invention need not adopt special patterning processes to carry out composition to protective layer; but pass through figure and the via hole of a patterning processes formation passivation layer; can under the prerequisite not increasing patterning processes; avoid pollution TFT raceway groove caused when formation the first electrode, ensure product quality.
Further, described array base palte also comprises:
Be positioned at the second electrode on described passivation layer.
In one specific embodiment; described first electrode is pixel electrode; described second electrode is public electrode; described first via hole runs through described passivation layer and described protective layer, exposes the drain electrode of described thin-film transistor; described second via hole runs through described passivation layer, exposes the described pixel electrode of part; described conductive connecting is connected with described drain electrode by described first via hole, and is connected with described pixel electrode by described second via hole.
Preferably, the thickness of described protective layer is
Embodiment three
Present embodiments provide a kind of display unit, comprise above-mentioned array base palte.Described display unit can be: any product or parts with Presentation Function such as liquid crystal panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer, navigator, Electronic Paper.
Embodiment four
Below in conjunction with accompanying drawing, array base palte of the present embodiment and preparation method thereof is described in detail:
The manufacture method of the array base palte of the present embodiment specifically comprises the following steps:
Step a1: provide a underlay substrate 1, underlay substrate 1 is formed the figure of gate electrode 2, public electrode wire 3 and grid line;
As shown in Figure 2, provide a underlay substrate 1, underlay substrate 1 is formed the figure comprising gate electrode 2, the grid line be connected with gate electrode 2 and public electrode wire 3 be made up of grid metal level.Wherein, underlay substrate 1 can be glass substrate or quartz base plate.
Particularly, can adopt the method for sputtering or thermal evaporation on underlay substrate 1, deposit a layer thickness is 2500-
grid metal level, grid metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, grid metal level can be single layer structure or sandwich construction, and sandwich construction is Cu Mo such as, Ti Cu Ti, Mo Al Mo etc.Grid metal level applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of grid line, public electrode wire and gate electrode, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etched away the grid metallic film of the non-reserve area of photoresist by etching technics completely, peel off remaining photoresist, form the figure of grid line, public electrode wire 3 and gate electrode 2.
Step a2: form gate insulation layer 4 on the underlay substrate 1 through step a1, and on gate insulation layer 4, be formed with the figure of active layer 5, source electrode 6, drain electrode 7 and data wire;
As shown in Figure 3, particularly, can strengthen chemical vapour deposition (CVD) (PECVD) method by using plasma, on the underlay substrate 1 through step a1, deposit thickness is about 2000-
gate insulation layer 4, wherein, gate insulator layer material can select oxide, nitride or nitrogen oxide, and gate insulation layer can be individual layer, bilayer or sandwich construction.Particularly, gate insulation layer can adopt SiNx, SiOx or Si (ON) x.
Particularly, magnetron sputtering, thermal evaporation or other film build method can be adopted on gate insulation layer 4 to deposit a layer thickness and be about 20-
semiconductor layer, semiconductor layer can adopt a-Si and n+a-Si.Apply photoresist on the semiconductor layer, carry out exposing, developing, etching semiconductor layer, and stripping photoresist, be formed with the figure of active layer 5.
Particularly, can on the underlay substrate 1 being formed with active layer 5, adopt magnetron sputtering, thermal evaporation or other film build method to deposit a layer thickness and be about 2000-
source and drain metal level, source and drain metal level can be the alloy of the metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals.Source and drain metal level can be single layer structure or sandwich construction, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Source and drain metal level applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of source electrode, drain electrode and data wire, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; The source and drain metallic film of the non-reserve area of photoresist is etched away completely by etching technics, peel off remaining photoresist, form the figure of data wire, source electrode 6, drain electrode 7, source electrode 6 is connected by active layer 5 with drain electrode 7, TFT completes, and is TFT raceway groove between source electrode 6 and drain electrode 7.
Further, active layer 5 and source electrode 6, drain electrode 7, data wire also can be formed by a same patterning processes.
Step a3: plasma treatment is carried out to TFT raceway groove, and form protective layer 11;
As shown in Figure 4, H is carried out to the underlay substrate 1 through step a2
2plasma treatment TFT raceway groove, then adopts magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness to be 50-
protective layer 11, wherein, protective layer material can select oxide, nitride or nitrogen oxide, and particularly, protective layer can adopt SiNx, SiOx or Si (ON) x.Protective layer can be single layer structure, also can be the double-layer structure adopting silicon nitride and silica to form.
The plasma treatment of carrying out TFT raceway groove can reduce the leakage current of TFT, improves product quality.The present embodiment carried out plasma treatment to TFT raceway groove before formation pixel electrode, can not impact pixel electrode.
Step a4: the figure forming pixel electrode 8 on the underlay substrate 1 through step a3;
As shown in Figure 5, particularly, can on the underlay substrate 1 through step a3, adopt magnetron sputtering, thermal evaporation or other film build method to deposit a layer thickness and be about 20-
the first transparency conducting layer, the first transparency conducting layer can select ITO or IZO.First transparency conducting layer applies photoresist, carries out exposing, developing, etch the first transparency conducting layer, and stripping photoresist, form the figure of the pixel electrode 8 be made up of the first transparency conducting layer.
Step a5: form the figure including the gate insulation layer 4 of grid insulating layer through hole on the underlay substrate 1 through step a4, include the figure of the protective layer 11 of protective layer via hole, and form the figure including the passivation layer 9 of drain electrode via hole, pixel electrode via hole and public electrode via hole;
As shown in Figure 6, particularly, can on the underlay substrate 1 through step a4, magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness be adopted to be 400-
passivation material, wherein, passivation material can select oxide, nitride or nitrogen oxide, and particularly, passivation layer can adopt SiNx, SiOx or Si (ON) x.Passivation layer can be single layer structure, also can be the double-layer structure adopting silicon nitride and silica to form.
Passivation material applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of passivation layer, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure, carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged, the passivation material of the non-reserve area of photoresist is etched away completely by etching technics, peel off remaining photoresist, formation includes drain electrode via hole, the figure of the passivation layer 9 of pixel electrode via hole and public electrode via hole, wherein source electrode via hole corresponds to drain electrode 7, pixel electrode via hole corresponds to pixel electrode 8, expose pixel electrode 8, public electrode via hole corresponds to public electrode wire 3, the protective layer 11 at drain electrode via hole place is etched, expose drain electrode 7, the protective layer 11 at public electrode via hole place and gate insulation layer 4 are all etched, expose public electrode wire 3, the figure of the figure obtaining the protective layer 11 including protective layer via hole and the gate insulation layer 4 including grid insulating layer through hole.
Step a6: the figure forming public electrode 10 and conductive connecting 12 on the underlay substrate through step a5;
As shown in Figure 7, particularly, magnetron sputtering, thermal evaporation or other film build method can be adopted on the underlay substrate through step a5 to deposit a layer thickness and be about 20-
the second transparency conducting layer, the second transparency conducting layer can select ITO or IZO.Second transparency conducting layer applies photoresist, expose, development, etch the second transparency conducting layer, and stripping photoresist, form the figure of the public electrode 10 and conductive connecting 12 be made up of the second transparency conducting layer, public electrode 10 is by public electrode via hole, protective layer via hole, be connected with public electrode wire 3 with grid insulating layer through hole, conductive connecting 12 is by drain electrode via hole, protective layer via hole is connected with drain electrode 7, conductive connecting 12 is connected with pixel electrode 8 by pixel electrode via hole, thus realize drain electrode 7 by conductive connecting 12 and be connected with the conduction of pixel electrode 8.
Array base palte as shown in Figure 7 can be produced by above-mentioned steps a1-a6; after the present embodiment forms thin-film transistor on substrate; thin-film transistor is formed layer protective layer protect thin-film transistor; and form pixel electrode on the protection layer; while composition is carried out to passivation layer, form protective layer via hole afterwards, and connect the drain electrode of pixel electrode and thin-film transistor by conductive connecting.Technical scheme of the present invention need not adopt special patterning processes to carry out composition to protective layer, but pass through figure and the protective layer via hole of a patterning processes formation passivation layer, can under the prerequisite not increasing patterning processes, avoiding pollution TFT raceway groove caused when forming pixel electrode, ensureing product quality; And before formation protective layer; plasma treatment can also be carried out to TFT raceway groove; because plasma treatment was carried out before formation pixel electrode; therefore can not impact pixel electrode; the plasma treatment of carrying out TFT raceway groove can reduce the leakage current of TFT, improves product quality.
Embodiment five
Below in conjunction with accompanying drawing, array base palte of the present embodiment and preparation method thereof is described in detail:
The manufacture method of the array base palte of the present embodiment specifically comprises the following steps:
Step b1: provide a underlay substrate 1, underlay substrate 1 is formed the figure of gate electrode 2, public electrode wire 3 and grid line;
As shown in Figure 2, provide a underlay substrate 1, underlay substrate 1 is formed the figure comprising gate electrode 2, the grid line be connected with gate electrode 2 and public electrode wire 3 be made up of grid metal level.Wherein, underlay substrate 1 can be glass substrate or quartz base plate.
Particularly, can adopt the method for sputtering or thermal evaporation on underlay substrate 1, deposit a layer thickness is 2500-
grid metal level, grid metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, grid metal level can be single layer structure or sandwich construction, and sandwich construction is Cu Mo such as, Ti Cu Ti, Mo Al Mo etc.Grid metal level applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of grid line, public electrode wire and gate electrode, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etched away the grid metallic film of the non-reserve area of photoresist by etching technics completely, peel off remaining photoresist, form the figure of grid line, public electrode wire 3 and gate electrode 2.
Step b2: form gate insulation layer 4 on the underlay substrate 1 through step b1, and on gate insulation layer 4, be formed with the figure of active layer 5, source electrode 6, drain electrode 7 and data wire;
As shown in Figure 3, particularly, can strengthen chemical vapour deposition (CVD) (PECVD) method by using plasma, on the underlay substrate 1 through step b1, deposit thickness is about 2000-
gate insulation layer 4, wherein, gate insulator layer material can select oxide, nitride or nitrogen oxide, and gate insulation layer can be individual layer, bilayer or sandwich construction.Particularly, gate insulation layer can adopt SiNx, SiOx or Si (ON) x.
Particularly, magnetron sputtering, thermal evaporation or other film build method can be adopted on gate insulation layer 4 to deposit a layer thickness and be about 20-
semiconductor layer, semiconductor layer can adopt a-Si and n+a-Si.Apply photoresist on the semiconductor layer, carry out exposing, developing, etching semiconductor layer, and stripping photoresist, be formed with the figure of active layer 5.
Particularly, can on the underlay substrate 1 being formed with active layer 5, adopt magnetron sputtering, thermal evaporation or other film build method to deposit a layer thickness and be about 2000-
source and drain metal level, source and drain metal level can be the alloy of the metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals.Source and drain metal level can be single layer structure or sandwich construction, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Source and drain metal level applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of source electrode, drain electrode and data wire, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure; Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; The source and drain metallic film of the non-reserve area of photoresist is etched away completely by etching technics, peel off remaining photoresist, form the figure of data wire, source electrode 6, drain electrode 7, source electrode 6 is connected by active layer 5 with drain electrode 7, TFT completes, and is TFT raceway groove between source electrode 6 and drain electrode 7.
Further, active layer 5 and source electrode 6, drain electrode 7, data wire also can be formed by a same patterning processes.
Step b3: plasma treatment is carried out to TFT raceway groove, and form protective layer 11;
As shown in Figure 4, H is carried out to the underlay substrate 1 through step b2
2plasma treatment TFT raceway groove, then adopts magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness to be 50-
protective layer 11, wherein, protective layer material can select oxide, nitride or nitrogen oxide, and particularly, protective layer can adopt SiNx, SiOx or Si (ON) x.Protective layer can be single layer structure, also can be the double-layer structure adopting silicon nitride and silica to form.
The plasma treatment of carrying out TFT raceway groove can reduce the leakage current of TFT, improves product quality.The present embodiment carried out plasma treatment to TFT raceway groove before formation pixel electrode, can not impact pixel electrode.
Step b4: the figure forming pixel electrode 8 on the underlay substrate 1 through step b3;
As shown in Figure 5, particularly, can on the underlay substrate 1 through step b3, adopt magnetron sputtering, thermal evaporation or other film build method to deposit a layer thickness and be about 20-
the first transparency conducting layer, the first transparency conducting layer can select ITO or IZO.First transparency conducting layer applies photoresist, carries out exposing, developing, etch the first transparency conducting layer, and stripping photoresist, form the figure of the pixel electrode 8 be made up of the first transparency conducting layer.
Step b5: form the figure including the gate insulation layer 4 of grid insulating layer through hole on the underlay substrate 1 through step b4, include the figure of the protective layer 11 of protective layer via hole, and form the figure including the passivation layer 9 of drain electrode via hole, pixel electrode via hole and public electrode via hole;
As shown in Figure 8, particularly, can on the underlay substrate 1 through step b4, magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness be adopted to be 400-
passivation material, wherein, passivation material can select oxide, nitride or nitrogen oxide, and particularly, passivation layer can adopt SiNx, SiOx or Si (ON) x.Passivation layer can be single layer structure, also can be the double-layer structure adopting silicon nitride and silica to form.
Passivation material applies one deck photoresist, mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist and photoresist reserve area, wherein, photoresist reserve area corresponds to the figure region of passivation layer, and the non-reserve area of photoresist corresponds to the region beyond above-mentioned figure, carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged, the passivation material of the non-reserve area of photoresist is etched away completely by etching technics, peel off remaining photoresist, formation includes drain electrode via hole, the figure of the passivation layer 9 of pixel electrode via hole and public electrode via hole, wherein drain electrode via hole corresponds to drain electrode 7, pixel electrode via hole corresponds to pixel electrode 8, different from embodiment four, drain electrode via hole in the present embodiment and pixel electrode via hole connect the large via hole of composition one, public electrode via hole corresponds to public electrode wire 3, the protective layer 11 at drain electrode via hole place is etched, the protective layer 11 at public electrode via hole place and gate insulation layer 4 are all etched, the figure of the figure obtaining the protective layer 11 including protective layer via hole and the gate insulation layer 4 including grid insulating layer through hole.
Step b6: the figure forming public electrode 10 and conductive connecting 12 on the underlay substrate through step b5;
As shown in Figure 9, particularly, magnetron sputtering, thermal evaporation or other film build method can be adopted on the underlay substrate through step b5 to deposit a layer thickness and be about 20-
the second transparency conducting layer, the second transparency conducting layer can select ITO or IZO.Second transparency conducting layer applies photoresist, expose, development, etch the second transparency conducting layer, and stripping photoresist, form the figure of the public electrode 10 and conductive connecting 12 be made up of the second transparency conducting layer, public electrode 10 is by public electrode via hole, protective layer via hole is connected with public electrode wire 3 with grid insulating layer through hole, conductive connecting 12 is positioned at the large via hole of drain electrode via hole and pixel electrode via hole composition, conductive connecting 12 is connected with pixel electrode 8 and drain electrode 7 respectively, thus realize drain electrode 7 by conductive connecting 12 and be connected with the conduction of pixel electrode 8.
Array base palte as shown in Figure 9 can be produced by above-mentioned steps b1-b6; after the present embodiment forms thin-film transistor on substrate; thin-film transistor is formed layer protective layer protect thin-film transistor; and form pixel electrode on the protection layer; while composition is carried out to passivation layer, form protective layer via hole afterwards, and connect the drain electrode of pixel electrode and thin-film transistor by conductive connecting.Technical scheme of the present invention need not adopt special patterning processes to carry out composition to protective layer, but pass through figure and the protective layer via hole of a patterning processes formation passivation layer, can under the prerequisite not increasing patterning processes, avoiding pollution TFT raceway groove caused when forming pixel electrode, ensureing product quality; And before formation protective layer; plasma treatment can also be carried out to TFT raceway groove; because plasma treatment was carried out before formation pixel electrode; therefore can not impact pixel electrode; the plasma treatment of carrying out TFT raceway groove can reduce the leakage current of TFT, improves product quality.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a manufacture method for array base palte, is characterized in that, comprising:
The substrate being formed with thin-film transistor forms protective layer, and form the first electrode on described protective layer;
The substrate being formed with described first electrode forms passivation layer, and is formed and run through described passivation layer and described protective layer, expose the first via hole of the drain electrode of described thin-film transistor and run through described passivation layer, expose the second via hole of described first electrode of part;
Described passivation layer is formed and is connected the drain electrode of described thin-film transistor and the conductive connecting of described first electrode by described first via hole with described second via hole.
2. the manufacture method of array base palte according to claim 1, is characterized in that, described passivation layer is also formed with the second electrode, and described second electrode and described conductive connecting are by being formed with a patterning processes.
3. the manufacture method of array base palte according to claim 1 and 2, is characterized in that, described on the substrate being formed with thin-film transistor, form protective layer before also comprise:
Plasma treatment is carried out to the raceway groove of described thin-film transistor.
4. the manufacture method of the array base palte according to Claims 2 or 3, is characterized in that, described first electrode is pixel electrode, and described second electrode is public electrode, and described manufacture method specifically comprises:
Described protective layer deposits the first transparency conducting layer, utilizes described first transparency conducting layer to form described pixel electrode by a patterning processes;
Deposit passivation layer on the substrate being formed with described pixel electrode, formed by patterning processes run through passivation layer and described protective layer, the first via hole of exposing the drain electrode of described thin-film transistor and run through described passivation layer, expose the second via hole of the described pixel electrode of part;
The substrate being formed with described passivation layer deposits the second transparency conducting layer, described second transparency conducting layer is utilized to form described public electrode and described conductive connecting by a patterning processes, described conductive connecting is connected with described drain electrode by described first via hole, and is connected with described pixel electrode by described second via hole.
5. the manufacture method of array base palte according to claim 4, is characterized in that, forms described thin-film transistor and comprises:
Described substrate is provided;
The gate electrode of described thin-film transistor is formed on the substrate by patterning processes;
The substrate being formed with described gate electrode forms gate insulation layer;
Described gate insulation layer is formed the figure of active layer;
The substrate being formed with described active layer is formed by patterning processes source electrode and the drain electrode of described thin-film transistor.
6. an array base palte, is characterized in that, make for adopting the manufacture method according to any one of claim 1-5 and obtain, described array base palte comprises:
Be positioned at the thin-film transistor on substrate;
Be positioned at the protective layer on the substrate being formed with described thin-film transistor;
Be positioned at the first electrode on described protective layer;
Be positioned at the passivation layer on the substrate being formed with described first electrode;
Be positioned on described passivation layer, by the first via hole and be connected the drain electrode of described thin-film transistor and the conductive connecting of described first electrode with the second via hole; wherein; described first via hole runs through described passivation layer and described protective layer, exposes the drain electrode of described thin-film transistor, and described second via hole runs through described passivation layer, exposes described first electrode of part.
7. array base palte according to claim 6, is characterized in that, described array base palte also comprises:
Be positioned at the second electrode on described passivation layer.
8. array base palte according to claim 7; it is characterized in that; described first electrode is pixel electrode; described second electrode is public electrode; described first via hole runs through described passivation layer and described protective layer, exposes the drain electrode of described thin-film transistor; described second via hole runs through described passivation layer, exposes the described pixel electrode of part, and described conductive connecting is connected with described drain electrode by described first via hole, and is connected with described pixel electrode by described second via hole.
9. the array base palte according to any one of claim 6-8, is characterized in that, the thickness of described protective layer is
10. a display unit, is characterized in that, comprises the array base palte according to any one of claim 6-9.
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