CN102945827A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN102945827A CN102945827A CN2012104589849A CN201210458984A CN102945827A CN 102945827 A CN102945827 A CN 102945827A CN 2012104589849 A CN2012104589849 A CN 2012104589849A CN 201210458984 A CN201210458984 A CN 201210458984A CN 102945827 A CN102945827 A CN 102945827A
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Abstract
The invention provides a manufacturing method of an array substrate and the array substrate. The manufacturing method of the array substrate comprises the following steps: a grid metal film, an insulating film and a semiconductor film are formed on the substrate, and graphs including grid lines, a gate insulation layer and a semiconductor layer are formed through a first composition process; a transparent conducting film and a metal film are sequentially formed, and graphs including data lines, a source electrode, a drain electrode, a public electrode and a public electrode leading wire are formed through a second composition process; an insulation layer is formed, and the graph of an insulation layer through hole in the position of the drain electrode is formed through a third composition process; and a pixel electrode layer is formed, and the graph of a pixel electrode in a slit structure is formed through a fourth composition process. According to the manufacturing method of the array substrate, the manufacturing steps of the array substrate are reduced, so that the manufacturing cost of the array substrate is reduced.
Description
Technical field
The invention belongs to the Display Technique field, be specifically related to a kind of array base palte and preparation method thereof.
Background technology
In panel display apparatus, Thin Film Transistor-LCD (Thin FilmTransistor Liquid Crystal Display, be called for short TFT-LCD) have that volume is little, low in energy consumption, manufacturing cost is relatively low and the characteristics such as radiationless, occupied leading position in current flat panel display market.
At present, the display mode of TFT-LCD mainly contains TN (Twisted Nematic, twisted-nematic) pattern, VA (Vertical Alignment, vertical orientated) pattern, IPS (In-Plane-Switching, the in-plane conversion) pattern and AD-SDS (ADvancedSuper Dimension Switch, a senior super dimension switch technology is called for short ADS) pattern etc.
Wherein, the liquid crystal display of ADS pattern mainly is that the electric field that the electric field that produces by gap electrode edge in the same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
But ADS type display unit adopts 6 composition techniques to make mostly, and processing step is more, and the cost of manufacture of display unit is higher.
Summary of the invention
The technical problem to be solved in the present invention is exactly for the defects that exists in the prior art, and a kind of array base palte and preparation method thereof is provided.
The invention provides a kind of array substrate manufacturing method, comprising:
Step S1 forms grid metallic film, insulation film and semiconductive thin film at described substrate, comprises the figure of grid line, grid, gate insulator and semiconductor layer by the composition technique formation first time;
Step S2 forms transparent conductive film and metallic film successively on the substrate of completing steps S1, comprise the figure of data wire, source electrode, drain electrode and public electrode by the composition technique formation second time;
Step S3 forms insulating barrier at the substrate of completing steps S2, forms by composition for the third time to comprise that technique is in the insulating barrier via pattern of described drain locations;
Step S4 forms pixel electrode layer at the substrate of completing steps S3, forms the pixel electrode figure that comprises narrow slit structure by the 4th composition technique.
Preferably, described step 2 by the second time composition technique also form the figure that comprises public electrode lead-in wire; Described public electrode lead-in wire is used for being electrically connected the public electrode of two the adjacent pixel regions that limited by grid line and data wire.
Preferably, in described first time composition technique, adopt halftoning or gray tone mask plate to form the figure that comprises grid line, grid, gate insulator and semiconductor layer by half exposure technology.
Preferably, the figure of described semiconductor layer is positioned at the top of described grid line.
Preferably, in described second time composition technique, keep the metal thin-film pattern of the figure top of described public electrode lead-in wire, figure and the metal thin-film pattern of described public electrode lead-in wire have identical shaped.
Preferably, described grid metallic film adopts molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium, copper or its combination to make, and the thickness of described grid metallic film is
And/or described grid insulating film adopts silicon nitride, silica or silicon oxy-nitride material to make, and the thickness of described grid insulating film is
And/or the thickness of described semiconductive thin film is
And/or described transparent conductive film is ito thin film or IZO film; The thickness of described transparent conductive film is
And/or the material of described metallic film is molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper, and the thickness of described metallic film is
And/or described insulating barrier adopts silicon nitride or made of silicon dioxide;
And/or described pixel electrode layer adopts ito thin film or IZO film, and the thickness of described pixel electrode layer is
The present invention also provides a kind of array base palte, comprise substrate, grid line, data wire and thin-film transistor, in the pixel region of described grid line and the restriction of described data wire, be provided with and comprise public electrode, pixel electrode and thin-film transistor, described pixel electrode is relative with described public electrode, and between described pixel electrode and described public electrode, be provided with insulating barrier, described thin-film transistor comprises grid, gate insulator, semiconductor layer, source electrode and drain electrode, and described source electrode and drain electrode below comprise having the transparent conductive film figure identical shaped with described source electrode, drain electrode.
Preferably, further comprise the public electrode lead-in wire, described public electrode lead-in wire is used for being electrically connected the public electrode of two the adjacent pixel regions in grid line and the data wire limited area.
Preferably, described semiconductor layer is positioned at described grid line top.
Preferably, have the metal thin-film pattern identical shaped with described public electrode lead-in wire above the described public electrode lead-in wire.
The present invention has following beneficial effect:
Array substrate manufacturing method provided by the invention only can form array base palte by four composition techniques, has reduced the making step of array base palte, thereby has reduced the cost of manufacture of array base palte.
Array base palte provided by the invention has reduced the cost of array base palte owing to only form by four composition techniques.
Description of drawings
Fig. 1 a is the plane graph of embodiment of the invention array base palte;
Fig. 1 b is the partial enlarged drawing at circled positions place among Fig. 1 a;
Fig. 1 c along A1-A1 among Fig. 1 b to cutaway view;
Fig. 2 is the flow chart of present embodiment array substrate manufacturing method;
Fig. 3 a is the plane graph after the embodiment of the invention composition technique first time;
Fig. 3 b be along A2-A2 among Fig. 3 a to cutaway view;
Fig. 4 a is the plane graph after the embodiment of the invention composition technique second time;
Fig. 4 b be along A3-A3 among Fig. 4 a to cutaway view;
Fig. 5 a is for the third time plane graph after the composition technique of the embodiment of the invention;
Fig. 5 b be along A4-A4 among Fig. 5 a to cutaway view.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with accompanying drawing array base palte provided by the invention and preparation method thereof is described in detail.
The array base palte that is obtained by the present embodiment array substrate manufacturing method is mainly used in ADS type display unit.
Referring to Fig. 1 a and Fig. 1 b, Fig. 1 a is the plane graph of embodiment of the invention array base palte.Fig. 1 b be along A1-A1 among Fig. 1 a to cutaway view.
Array base palte specifically can comprise TFT (thin-film transistor), grid line 3 and data wire 7c, forms in the pixel region that grid line 3 and data wire 7c limit and includes pixel electrode 9, public electrode 2a.
Can also be provided with public electrode lead-in wire 2b between per two public electrode 2a, public electrode lead-in wire 2b is used for providing electric energy to public electrode 2a, and the public electrode 2a of two adjacent pixel regions that will be limited by grid line 3 and data wire 7c is electrically connected.Public electrode lead-in wire 2b will be electrically connected with public electrode 2a by connecting portion 2c.
Thin-film transistor specifically can comprise grid, gate insulator 4, semiconductor layer 6, source electrode 7a and drain electrode 7b.Grid is formed on the glass substrate 1, and is electrically connected with grid line 3.In the present embodiment, because grid and grid line 3 are to form with a composition technique, and both are electrically connected.
Present embodiment can directly use as grid with grid line 3, and namely follow-up semiconductor layer is positioned at described grid line 3 tops.
In the present embodiment, source electrode 7a, drain electrode 7b, public electrode 2a, public electrode lead-in wire 2b and data wire 7c form with a composition technique.And in the composition technical process, can will keep with the public electrode relative metallic film in 2b position that goes between.Thereby can obtain following architectural feature, namely, in source electrode 7a and drain electrode 7b place layer, the zone relative with public electrode lead-in wire 2b position is provided with metallic film, in other words, have the metal thin-film pattern identical shaped with public electrode lead-in wire 2b above public electrode lead-in wire 2b, this can improve the electric conductivity of public electrode lead-in wire 2b.This metallic film is identical with the metallic film that forms source electrode 7a and drain electrode 7b.
In addition, the present embodiment array base palte not only can be used for ADS type display unit, and can be used for the display unit of other type.
Further specify the technical scheme of present embodiment manufacture method below by embodiment.Present embodiment obtains array base palte by four composition techniques, and Fig. 2 is the flow chart of embodiment of the invention array substrate manufacturing method.The composition technique of mentioning hereinafter comprises photoresist coating, mask, exposure, etching and photoresist removal technique.
As shown in Figure 2, the present embodiment array substrate manufacturing method may further comprise the steps:
Step S1 forms grid metallic film, insulation film and semiconductive thin film at glass substrate 1, comprises the figure of grid line, grid, gate insulator and semiconductor layer by the composition technique formation first time.
In step S1, at first at glass substrate 1 formation thickness be
The grid metallic film.Glass substrate 1 can also replace with quartz base plate.The grid metallic film adopts the metal materials such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper, perhaps adopts the combining structure of the film of above-mentioned several metal material formation.The grid metallic film can adopt magnetron sputtering, thermal evaporation or other film build method to form.
Then, the surperficial successive sedimentation thickness at the grid metallic film is
The gate insulator layer film.The gate insulator layer film can adopt silicon nitride, silica or silicon oxynitride, and it forms by chemical vapour deposition technique.
Surperficial successive sedimentation thickness at the gate insulator layer film is
Semiconductive thin film.Semiconductive thin film can adopt the semi-conducting material of semiconductor or doping, and it forms by chemical vapour deposition technique.
At last, form the figure that comprises grid line 3, grid, gate insulator 4 and semiconductor layer 6 by the first composition technique.
Composition process using half exposure technique carries out composition for the first time, as adopting halftoning or gray tone mask plate grid metallic film, insulation film and semiconductive thin film is carried out composition.
Shown in Fig. 3 a and Fig. 3 b, Fig. 3 a is for the first time plane graph after the composition technique of the embodiment of the invention, Fig. 3 b be along A2-A2 among Fig. 3 a to cutaway view.The first composition technique forms double grid line 3, and double grid line 3 can reduce the cost of manufacture of array base palte on the one hand, can improve visible angle on the other hand, improves graphical quality.
Present embodiment can directly use as grid with grid line 3, and namely follow-up semiconductor layer is positioned at described grid line top.
Step S2 forms transparent conductive film and metallic film successively on the glass substrate of completing steps S1, comprise data wire, source electrode, drain electrode and public electrode, connecting portion figure by the composition technique formation second time.
In step S2, at first, form continuous thickness at the glass substrate of completing steps S1 and be
Transparent conductive film, the material of transparent conductive film can be ITO (indium tin oxide) or IZO (indium-zinc oxide) or other macromolecule transparent material, it can form by magnetron sputtering or other thin film-forming method.
Then, forming thickness at transparent conductive film is
Metallic film.The material of metallic film can be molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper, the combining structure of the film that perhaps forms for above-mentioned material.
At last, comprise data wire 7c, source electrode 7a, drain electrode 7b, public electrode 2a and connecting portion 2c figure by the composition technique formation second time.Because data wire 7c, source electrode 7a, drain electrode 7b, public electrode 2a obtain by a composition technique, therefore, the transparent conductive film figure that will be positioned at source electrode 7a and drain electrode 7b below keeps, thereby comprises having the transparent conductive film figure identical shaped with source electrode 7a, drain electrode 7b below source electrode 7a and drain electrode 7b.
In step S2, preferably, composition technique also forms the figure that comprises public electrode lead-in wire 2b for the second time, public electrode lead-in wire 2b is used for being electrically connected the public electrode 2a of two the adjacent pixel regions that limited by grid line 3 and data wire 7c, simultaneously, public electrode lead-in wire 2b provides electric energy to public electrode 2a.Public electrode lead-in wire 2b is electrically connected by connecting portion 2c and public electrode 2a.
In step S2, when the enforcement composition technique second time, the metal thin-film pattern (namely forming the metallic film of source electrode, drain electrode) that can keep public electrode lead-in wire 2b figure top, and the figure of the figure that makes public electrode lead-in wire 2b and metallic film have identical shaped, thereby can improve the go between electric conductivity of 2b of public electrode.
Shown in Fig. 4 a and Fig. 4 b, Fig. 4 a is the plane graph after the embodiment of the invention composition technique second time; Fig. 4 b be along A3-A3 among Fig. 4 a to cutaway view.
Step S3 forms insulating barrier at the glass substrate of completing steps S2, forms the figure of the insulating barrier via hole that is included in described drain locations by composition technique for the third time.
In step S3, at first, form thickness at the glass substrate of completing steps S2 and be
Insulating barrier 8, the material of insulating barrier 8 can be silicon nitride (SiNx) or silicon dioxide, it adopts chemical gaseous phase depositing process or other thin film-forming method to form.
Then, form in drain electrode 7b position by composition technique for the third time and to comprise the insulating barrier via hole image, the insulating barrier via hole with so that drain electrode 7b and pixel electrode 9 be electrically connected.
Fig. 5 a is for the third time plane graph after the composition technique of the embodiment of the invention, Fig. 5 b be along A4-A4 among Fig. 5 a to cutaway view.Shown in Fig. 5 a and Fig. 5 b, insulating barrier via hole 5 is arranged on drain electrode 7b position, and 7b and pixel electrode 9 are electrically connected in order to draining.
Step S4 forms pixel electrode layer at the substrate of completing steps S3, forms the pixel electrode that comprises narrow slit structure by the 4th composition technique.
In step S4, at first, by chemical gaseous phase depositing process at the glass substrate 1 formation thickness of completing steps S3 be
Pixel electrode layer, the material of pixel electrode layer can be ITO or IZO.
Then, utilize the mask plate of transparency electrode, form the pixel electrode 8 that comprises narrow slit structure by the 4th composition technique.In addition, in step S4, can also form simultaneously the storage capacitance (not shown) by the 4th composition technique.
Fig. 1 a is the plane graph after the 4th composition technique of the embodiment of the invention.As shown in Figure 1a, be provided with narrow slit structure 10 at pixel electrode 9.
Need to prove to have on closo shield bars (black matrix) and shield bars and the array base palte that public electrode links to each other, transistorized structure obviously can have various modifications and variations.
The array substrate manufacturing method that present embodiment provides has formed array base palte by four composition techniques, for existing six times or more times composition technique, simplified the making step of array base palte, thereby reduced the techniques such as exposure, development, and then reduced the cost of manufacture of array base palte.
Be understandable that above execution mode only is the illustrative embodiments that adopts for principle of the present invention is described, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement also are considered as protection scope of the present invention.
Claims (10)
1. an array substrate manufacturing method is characterized in that, comprising:
Step S1 forms grid metallic film, insulation film and semiconductive thin film at described substrate, comprises the figure of grid line, grid, gate insulator and semiconductor layer by the composition technique formation first time;
Step S2 forms transparent conductive film and metallic film successively on the substrate of completing steps S1, comprise the figure of data wire, source electrode, drain electrode and public electrode by the composition technique formation second time;
Step S3 forms insulating barrier at the substrate of completing steps S2, forms the insulating barrier via pattern that is included in described drain locations by composition technique for the third time;
Step S4 forms pixel electrode layer at the substrate of completing steps S3, forms the pixel electrode figure that comprises narrow slit structure by the 4th composition technique.
2. array substrate manufacturing method according to claim 1 is characterized in that, described step 2 by the second time composition technique also form the figure that comprises public electrode lead-in wire; Described public electrode lead-in wire is used for being electrically connected the public electrode of two the adjacent pixel regions that limited by grid line and data wire.
3. array substrate manufacturing method according to claim 1 and 2, it is characterized in that, in described first time composition technique, adopt halftoning or gray tone mask plate to form the figure that comprises grid line, grid, gate insulator and semiconductor layer by half exposure technology.
4. array substrate manufacturing method according to claim 1 and 2 is characterized in that, the figure of described semiconductor layer is positioned at the top of described grid line.
5. array substrate manufacturing method according to claim 2, it is characterized in that, in described second time composition technique, keep the metal thin-film pattern of the figure top of described public electrode lead-in wire, figure and the metal thin-film pattern of described public electrode lead-in wire have identical shaped.
6. array substrate manufacturing method according to claim 1 is characterized in that, described grid metallic film adopts molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium, copper or its combination to make, and the thickness of described grid metallic film is
And/or described grid insulating film adopts silicon nitride, silica or silicon oxy-nitride material to make, and the thickness of described grid insulating film is
And/or the thickness of described semiconductive thin film is
And/or described transparent conductive film is ito thin film or IZO film; The thickness of described transparent conductive film is
And/or the material of described metallic film is molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper, and the thickness of described metallic film is
And/or described insulating barrier adopts silicon nitride or made of silicon dioxide;
And/or described pixel electrode layer adopts ito thin film or IZO film, and the thickness of described pixel electrode layer is
7. array base palte, comprise substrate, grid line, data wire and thin-film transistor, in the pixel region of described grid line and the restriction of described data wire, be provided with and comprise public electrode, pixel electrode and thin-film transistor, described pixel electrode is relative with described public electrode, and between described pixel electrode and described public electrode, be provided with insulating barrier, it is characterized in that, described thin-film transistor comprises grid, gate insulator, semiconductor layer, source electrode and drain electrode, and described source electrode and drain electrode below comprise having the transparent conductive film figure identical shaped with described source electrode, drain electrode.
8. array base palte according to claim 7 is characterized in that, further comprises the public electrode lead-in wire, and described public electrode lead-in wire is used for being electrically connected the public electrode of two the adjacent pixel regions in grid line and the data wire limited area.
9. according to claim 7 or 8 described array substrate manufacturing methods, it is characterized in that described semiconductor layer is positioned at described grid line top.
10. array base palte according to claim 8 is characterized in that, described public electrode lead-in wire top has the metal thin-film pattern identical shaped with described public electrode lead-in wire.
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| CN104730780A (en) * | 2013-12-20 | 2015-06-24 | 乐金显示有限公司 | Liquid crystal display device |
| WO2016141705A1 (en) * | 2015-03-11 | 2016-09-15 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display device |
| CN114217483A (en) * | 2021-12-17 | 2022-03-22 | 惠科股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| WO2023272480A1 (en) * | 2021-06-29 | 2023-01-05 | 京东方科技集团股份有限公司 | Display substrate, display device, and manufacturing method for display substrate |
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Application publication date: 20130227 |