CN103676390A - Array base plate, manufacturing method thereof, and display device - Google Patents
Array base plate, manufacturing method thereof, and display device Download PDFInfo
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- CN103676390A CN103676390A CN201310752921.9A CN201310752921A CN103676390A CN 103676390 A CN103676390 A CN 103676390A CN 201310752921 A CN201310752921 A CN 201310752921A CN 103676390 A CN103676390 A CN 103676390A
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Abstract
The invention relates to the field of display technology, in particular to an array base plate, a manufacturing method thereof, and a display device. The array base plate comprises a thin film transistor, a pixel electrode, and a color filter layer and a flat layer located above the thin film transistor, wherein the thin film transistor comprises a source electrode and a drain electrode; and the pixel electrode is electrically connected with the drain electrode of the thin film transistor through a first via hole in the flat layer. The invention provides the array base plate, the manufacturing method thereof, and the display device. The array base plate comprises the color filter layer, and the pixel electrode is electrically connected with the drain electrode through the first via hole in the flat layer, so that the length (or the area) of the source electrode and the drain electrode required for shielding light leakage can be effectively reduced, the aperture opening ratio can be effectively increased, the transmittance of a panel is improved, and the power consumption is reduced.
Description
Technical field
The present invention relates to display technique field, particularly array base palte and preparation method thereof, display device.
Background technology
At TFT-LCD(Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) owing to thering is the features such as volume is little, low in energy consumption, radiationless, receive much concern, in flat pannel display field, occupied leading position, be widely used in all trades and professions.This liquid crystal display is formed box by color membrane substrates and array base palte conventionally, but in actual production, often there will be due on the inaccurate problem that causes light leak and then affect display quality of box.For fear of this problem, in prior art, disclose and a kind of color membrane substrates has been positioned to array base-plate structure (COA, CF on Array), this structure does not need box technique, can effectively eliminate due to the light leak problem that box technique is caused, and can effectively reduce black matrix width, can improve light rate.
As shown in Figure 1, be prior art COA structural representation.Grid 2 ', gate insulation layer 3 ', semiconductor layer 4 ', source electrode 5 ' and drain electrode 6 ' that this structure comprises substrate, on substrate, forms successively; in source electrode 5 ' and drain electrode 6 ', be provided with black matrix 7 ' and chromatic filter layer 8 ' and be positioned at the protective seam 9 ' on both; this protective seam 9 ' is provided with pixel electrode 10 '; this pixel electrode 10 ' is connected with drain electrode 6 ' by running through the via hole of protective seam 9 ' and chromatic filter layer 8 ', and this pixel electrode is provided with passivation layer 11 ' and public electrode 12 '.
As can be seen from Figure 1; for being set, pixel electrode 10 ' and drain electrode 6 ' realize via hole electrical connection; via hole must be run through to protective seam 9 ' and chromatic filter layer 8 '; cause like this gradient distance of chromatic filter layer 8 ' larger, the toe distance toe distance large and passivation layer 11 ' of protective seam 9 ' is larger.Due to via hole position, liquid crystal arrangement there will be irregular phenomenon and causes light leakage phenomena problem, therefore, the length that need to lengthen source electrode 5 ' and drain electrode 6 ' is carried out shading, (because source electrode 5 ', drain electrode 6 ' are metal level, himself is light tight, can prevent near the uneven light leak problem causing of the liquid crystal aligning of via hole) but the increase of source electrode 5 ' and drain electrode 6 ' length will cause aperture opening ratio reduction, increase product power consumption.
Meanwhile, because the gradient distance of each layer is excessive, may cause broken string phenomenon, and cause pixel electrode to charge, and then affect display quality.
(1) technical matters that will solve
The object of this invention is to provide a kind of array base palte and preparation method thereof, display device, the length that lengthens source-drain electrode to overcome available technology adopting causes the low defect of aperture opening ratio.
(2) technical scheme
To achieve these goals, one aspect of the present invention provides a kind of array base palte, comprise: thin film transistor (TFT) and pixel electrode, described thin film transistor (TFT) comprises source electrode and drain electrode, also comprise: be positioned at chromatic filter layer and the flatness layer of thin film transistor (TFT) top, described pixel electrode is electrically connected to the drain electrode of described thin film transistor (TFT) by the first via hole on flatness layer.
Preferably, in described thin film transistor (TFT) source electrode and drain electrode, be also provided with black matrix, described black matrix and described chromatic filter layer interval arrange.
Preferably, described the first via hole is between black matrix and chromatic filter layer.
Preferably, described black matrix is provided with connecting electrode.
Preferably, described connecting electrode is made by metal material.
Preferably, also comprise public electrode and passivation layer, passivation layer is between public electrode and pixel electrode;
Described passivation layer is provided with the second via hole, and described public electrode is electrically connected to connecting electrode by the second via hole.
Preferably, described thin film transistor (TFT) is bottom gate thin film transistor.
On the other hand, the present invention also comprises a kind of display device, comprises above-mentioned array base palte and transparency carrier, between described array base palte and transparency carrier, is provided with chock insulator matter.
On the one hand, the present invention also provides a kind of method for making of array base palte, comprises the steps: again
On substrate, form the pattern that comprises thin film transistor (TFT) source electrode and drain electrode;
On thin film transistor (TFT), form the figure of chromatic filter layer;
On the figure of chromatic filter layer, form the figure of flatness layer, on described flatness layer, form the first via hole;
Form the figure of pixel electrode, described pixel electrode is connected with thin film transistor (TFT) drain electrode by the first via hole.
Preferably, before forming the figure of flatness layer, be also included in the figure that is formed with black matrix in described thin film transistor (TFT) source electrode and drain electrode, the pattern spacing setting of the figure of described black matrix and chromatic filter layer.
Preferably, on black matrix, form the figure connecting.
Preferably, also comprise formation passivation layer, and form the second via hole;
On passivation layer, form the figure of public electrode;
Described passivation layer is between public electrode and pixel electrode; Described public electrode is electrically connected to connecting electrode by the second via hole.
(3) beneficial effect
The invention provides a kind of array base palte and preparation method thereof, display device, this array base palte comprises chromatic filter layer, pixel electrode is set to be electrically connected by the first via hole and drain electrode on flatness layer, can effectively reduce the length (or area) of the source-drain electrode required in order to block light leak, and then can effectively increase aperture opening ratio, the transmitance that improves panel, reduces power consumption.
Accompanying drawing explanation
Fig. 1 is prior art COA structural representation;
Fig. 2 is embodiment of the present invention array base-plate structure schematic diagram;
Fig. 3 is embodiment of the present invention array substrate manufacturing method process flow diagram.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, to the invention provides scheme, be described in detail.The direction term that the present invention mentions, as represent direction " on ", D score, be only that direction with reference to accompanying drawing is with explanation and understand the present invention, but not in order to limit the present invention.
The embodiment of the present invention provides a kind of array base palte, comprise thin film transistor (TFT) and pixel electrode, described thin film transistor (TFT) comprises source electrode and drain electrode, also comprise: be positioned at chromatic filter layer and the flatness layer of thin film transistor (TFT) top, described pixel electrode is electrically connected to the drain electrode of described thin film transistor (TFT) by the first via hole on flatness layer.
Array base palte provided by the invention, pixel electrode is electrically connected by the first via hole and drain electrode, has farthest reduced the length (or area) of the source-drain electrode required in order to block light leak, and then can effectively increase aperture opening ratio, the transmitance that improves panel, reduces power consumption.
As shown in Figure 2, grid 2, gate insulation layer 3, semiconductor layer 4, source electrode 5, drain electrode 6 that this array base-plate structure for example can comprise substrate, on substrate, form successively, source electrode 5 and drain electrode 6 are provided with black matrix 7 and chromatic filter layer 8, and this black matrix 7 and chromatic filter layer 8 intervals arrange.This black matrix 7 and chromatic filter layer 8 are provided with flatness layer 9 and pixel electrode 10, and this flatness layer 9 is provided with the first via hole, and this first via hole is between black matrix 7 and chromatic filter layer 8, and this pixel electrode 10 is connected with drain electrode 6 by the first via hole.
Concrete, this chromatic filter layer 8 comprises red filter layer, green filter layer and blue color filter layer, for rich colors and brightness, this chromatic filter layer 8 for example can also comprise Yellow filter layer and white filter layer.
In the present embodiment, pixel electrode 10 is electrically connected by the first via hole and drain electrode 6, has farthest reduced the length (or area) of the source-drain electrode required in order to block light leak, and then can effectively increase aperture opening ratio, improves the transmitance of panel, reduces power consumption.
In addition, on this black matrix 7, be also provided with connecting electrode 11, passivation layer 12 and public electrode 13, this passivation layer 12 is provided with the second via hole, and the position of this second via hole is corresponding with the position of connecting electrode.Public electrode 13 is connected with connecting electrode 11 by the second via hole, realizes and being electrically connected to, and can effectively reduce common electric voltage inequality, the solution electrical phenomena such as crosstalk.
Wherein, the second via hole, not only through passivation layer 12, also through flatness layer 9, thereby makes public electrode 13 be connected with connecting electrode 11.
The present embodiment, by set up connecting electrode 11 on black matrix 7, arranges connecting electrode 11 and is electrically connected to public electrode 13, thereby can reduce common electric voltage inequality, solves the electrical phenomena such as crosstalk.
It should be noted that, the thin film transistor (TFT) of the array base palte in the present embodiment in being is bottom gate thin film transistor.Certainly, this thin film transistor (TFT) can also be the thin film transistor (TFT) of top gate type thin film transistor or other types.When the structure of top gate type thin film transistor, grid can be positioned at the top of chromatic filter layer.
Array base palte provided by the invention, is electrically connected pixel electrode and drain electrode by connecting electrode, has reduced the length (or area) of the source-drain electrode required in order to block light leak, and then can effectively increase aperture opening ratio, improves the transmitance of panel, reduces power consumption.
For technical solution of the present invention is described better, the bottom gate thin film transistor structure of take in the present embodiment is introduced as example.As shown in Figure 3, the invention provides a kind of method for making of array base palte, it comprises the steps:
S1, on substrate, form the pattern comprise thin film transistor (TFT) source electrode and drain electrode.
On substrate, form gate metal film, by a composition technique, form the pattern that comprises grid.
On the substrate of grid, form successively gate insulator layer film and semiconductor layer film being formed with, by a composition technique, form gate insulator and semiconductor layer pattern.
Being formed with leakage metallic film in formation source on the substrate of semiconductor layer, by a composition technique, form source electrode and drain pattern.
Certainly, step S1 can also adopt other modes to realize, and is not limited to aforesaid way.For example: gate insulator, semiconductor pattern and source-drain electrode pattern can form with in a composition technique.
Wherein, composition technique can comprise the partly or entirely step such as film forming, exposure, development and etching.The method of film forming can comprise the common process methods such as coating, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), magnetron sputtering.
Gate metal membraneous material, source are leaked metallic film material and conventionally can be adopted the metals such as molybdenum, aluminium, molybdenum and tungsten alloy, chromium or copper, also can use the unitized construction of above-mentioned different materials film; Semiconductor layer is selected the materials such as amorphous silicon, low temperature polycrystalline silicon or oxide semiconductor; The material that gate insulation layer film adopts is silicon nitride normally, can be also monox and silicon oxynitride etc.
Step S2, in thin film transistor (TFT) source electrode and drain electrode, be formed with the figure of black matrix and the figure of chromatic filter layer, the setting of the figure of described black matrix and chromatic filter layer interval.
Concrete, deposit black resin material, form the figure of black matrix, the figure of this black matrix is that interval arranges.Chromatic filter layer can comprise redness (R), green (G), blue (B) etc.
Step S3, on black matrix, form connecting electrode.
Concrete, depositing metal layers on the basis of completing steps S2, by the figure of composition technique formation connecting electrode.
Step S4, form flatness layer completing on the substrate of above-mentioned steps, and on flatness layer, form the first via hole.
Concrete, depositing insulating layer on the substrate of completing steps S3, forms flatness layer, and on flatness layer, forms the first via hole.
Step S5, complete the figure that forms pixel electrode on the substrate of above-mentioned steps, described pixel electrode is connected with draining by the first via hole.
Concrete, deposit transparent conductive material on the substrate of completing steps S3, by the figure of composition technique formation pixel electrode, is connected with drain electrode by the first via hole.
Step S6, form passivation layer completing on the substrate of above-mentioned steps, and on passivation layer, form the second via hole.
The figure of step S7, formation public electrode, described public electrode is connected with connecting electrode by the second via hole.
Concrete, on the basis of completing steps S6 substrate, deposit transparent conductive material, for example ITO, IZO, form public electrode, and this public electrode is electrically connected to connecting electrode by the second via hole on passivation layer.
And have more than in the present invention, be limited to bottom gate thin film transistor, the thin film transistor (TFT) of other types is all applicable to this programme.Although this instructions is illustrated bottom gate thin film transistor as embodiment, but be not limited to this, bottom gate thin film transistor should be interpreted as the general designation of bottom gate thin film transistor, so-called bottom gate thin film transistor: the grid of thin film transistor (TFT) is positioned at this class thin film transistor (TFT) of thin film transistor (TFT) semiconductor layer below.According to same reason, top gate type thin film transistor should be interpreted as the general designation of top-gate thin-film transistors, so-called top-gate thin-film transistors: the grid of thin film transistor (TFT) is positioned at this class thin film transistor (TFT) of thin film transistor (TFT) semiconductor layer top.
That in the present embodiment, adopt is ADS(ADvanced Super Dimension Switch, and a senior super dimension switch technology, is called for short ADS) structure, be positioned at the public electrode of different layers and pixel electrode all on array base palte.
A so-called senior super dimension switch technology (ADvanced Super Dimension Switch), be called for short ADS, its core technology characteristic description is: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal work efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).For different application, the improvement technology of ADS technology has high permeability I-ADS technology, high aperture H-ADS and high resolving power S-ADS technology etc.
The public electrode that it will be understood by those skilled in the art that above-described embodiment can be tabular or slit-shaped, and pixel electrode is also so, and the order up and down of pixel electrode and public electrode can be put upside down, and upper/lower electrode can be all slit-shaped; And the setting of public electrode also can multiplely change, for example, as long as guarantee to form multi-dimensional electric field between public electrode and pixel electrode: public electrode and grid are positioned at together layer.
Certainly, at traditional TN(Twisted Nemati, twisted-nematic) in the structure of pattern and IPS, the also scheme in applicable the present invention.
In addition, the present invention also provides a kind of display device, comprises array base palte and transparency carrier in above-described embodiment, between described array base palte and transparency carrier, is provided with chock insulator matter.Described display device can be specifically liquid crystal display, OLED display, Electronic Paper and other display device of using array base palte to drive.
Foregoing description provides for example with for the purpose of describing, and is not exhaustively or limit the invention to disclosed form.Many modifications and variations are obvious for the ordinary skill in the art.Selecting and describing embodiment is for better explanation principle of the present invention and practical application, thereby and makes those of ordinary skill in the art can understand the various embodiment with various modifications that the present invention's design is suitable for special-purpose.
Claims (12)
1. an array base palte, comprise thin film transistor (TFT) and pixel electrode, described thin film transistor (TFT) comprises source electrode and drain electrode, it is characterized in that, also comprise: be positioned at chromatic filter layer and the flatness layer of thin film transistor (TFT) top, described pixel electrode is electrically connected to the drain electrode of described thin film transistor (TFT) by the first via hole on flatness layer.
2. array base palte as claimed in claim 1, is characterized in that, in described thin film transistor (TFT) source electrode and drain electrode, is also provided with black matrix, and described black matrix and described chromatic filter layer interval arrange.
3. array base palte as claimed in claim 2, is characterized in that, described the first via hole is between black matrix and chromatic filter layer.
4. array base palte as claimed in claim 2, is characterized in that, described black matrix is provided with connecting electrode.
5. array base palte as claimed in claim 4, is characterized in that, described connecting electrode is made by metal material.
6. array base palte as claimed in claim 1, is characterized in that, also comprises public electrode and passivation layer, and passivation layer is between public electrode and pixel electrode;
Described passivation layer is provided with the second via hole, and described public electrode is electrically connected to connecting electrode by the second via hole.
7. array base palte as claimed in claim 1, is characterized in that, described thin film transistor (TFT) is bottom gate thin film transistor.
8. a display device, is characterized in that, comprises array base palte and transparency carrier described in claim 1-7 any one, between described array base palte and transparency carrier, is provided with chock insulator matter.
9. a method for making for array base palte, is characterized in that, comprises the steps:
On substrate, form the pattern that comprises thin film transistor (TFT) source electrode and drain electrode;
On thin film transistor (TFT), form the figure of chromatic filter layer;
On the figure of chromatic filter layer, form the figure of flatness layer, on described flatness layer, form the first via hole;
Form the figure of pixel electrode, described pixel electrode is connected with thin film transistor (TFT) drain electrode by the first via hole.
10. method for making as claimed in claim 9, it is characterized in that, before forming the figure of flatness layer, be also included in the figure that is formed with black matrix in described thin film transistor (TFT) source electrode and drain electrode, the pattern spacing setting of the figure of described black matrix and chromatic filter layer.
11. method for makings as claimed in claim 10, is characterized in that, also comprise:
On black matrix, form the figure of connecting electrode.
12. method for makings as claimed in claim 11, is characterized in that, also comprise formation passivation layer, and form the second via hole;
On passivation layer, form the figure of public electrode;
Described passivation layer is between public electrode and pixel electrode; Described public electrode is electrically connected to connecting electrode by the second via hole.
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| CN105467626A (en) * | 2014-09-11 | 2016-04-06 | 群创光电股份有限公司 | Liquid crystal display apparatus and element substrate of same |
| WO2018120691A1 (en) * | 2016-12-28 | 2018-07-05 | 京东方科技集团股份有限公司 | Array substrate and method for manufacturing same, and display device |
| CN111367128A (en) * | 2020-04-03 | 2020-07-03 | 厦门天马微电子有限公司 | Low-temperature polycrystalline silicon display panel, manufacturing method thereof and liquid crystal display device |
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| CN105259678B (en) * | 2014-07-17 | 2019-08-06 | 群创光电股份有限公司 | Liquid crystal display device and its device substrate |
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