CN114236926A

CN114236926A - Array substrate and display panel

Info

Publication number: CN114236926A
Application number: CN202111566378.4A
Authority: CN
Inventors: 李辉; 郑浩旋
Original assignee: HKC Co Ltd; Mianyang HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Mianyang HKC Optoelectronics Technology Co Ltd
Priority date: 2021-12-20
Filing date: 2021-12-20
Publication date: 2022-03-25
Anticipated expiration: 2041-12-20
Also published as: CN114236926B

Abstract

The utility model belongs to the display field, concretely relates to array substrate and display panel, wherein array substrate includes the substrate base plate and forms in proper order drive layer, flat layer, fill up high portion, electrode layer and the layer of joining in marriage on the substrate base plate, the electrode layer is through running through the via hole on flat layer with the drive layer electricity is connected, it is close to fill up high portion the via hole setting, in the flat layer with it is relative and keep away from to fill up high portion the position of filling up high portion is the bulge form, in order to center on the via hole forms the barricade. According to the alignment layer forming method and device, the portion, away from one side of the high part, of the flat layer forms the bulge through the high part, so that the blocking wall is formed around the through hole, alignment liquid can be blocked by the blocking wall and is difficult to diffuse into the through hole in the process of forming the alignment layer by subsequently coating the alignment liquid, the uneven thickness of the alignment layer at the periphery of the through hole can be improved through the design, and therefore the display image quality of the display panel is improved.

Description

Array substrate and display panel

Technical Field

The application belongs to the display field, and particularly relates to an array substrate and a display panel.

Background

The liquid crystal display is characterized in that one side of the array substrate, which is close to the liquid crystal layer, is provided with an alignment layer (PI), the alignment layer mainly plays a role of liquid crystal alignment in the liquid crystal display, and can provide a pretilt angle for liquid crystals, so that the liquid crystals can rapidly rotate under the action of an electric field, and the purpose of picture switching is achieved. The alignment layer is formed by solidifying alignment liquid, and the alignment liquid has fluidity.

At present, through holes are arranged at a plurality of positions of an array substrate, alignment liquid around the through holes can diffuse into the through holes before and during curing of the alignment liquid, so that the film thickness of an alignment layer around the through holes is thinner than that of other areas, namely, the film thickness of the alignment layer is uneven, and thus the phenomenon of uneven display brightness (namely mura) is easy to occur, and the display image quality of a display panel is influenced.

Disclosure of Invention

The present disclosure is directed to an array substrate and a display panel, which can improve display defects caused by non-uniform thickness of an alignment layer.

In order to achieve the above object, the present application provides an array substrate, including a substrate, and a driving layer, a flat layer, an electrode layer and an alignment layer sequentially formed on the substrate, wherein the electrode layer is electrically connected to the driving layer through a via hole penetrating through the flat layer, the array substrate includes:

the heightening part is positioned on one side, far away from the electrode layer, of the flat layer and is arranged close to the through hole;

the position, opposite to the pad high part and far away from the pad high part, in the flat layer is in a convex shape so as to surround the via hole to form a retaining wall.

Optionally, the array substrate further includes a color resistor, the color resistor is disposed between the flat layer and the driving layer, and the color resistor includes a plurality of color resistors of different colors;

the mat-up part and at least one color resistance layer in the plurality of color resistances with different colors are arranged in the same layer.

Optionally, the driving layer comprises a transistor;

the raised portion comprises a first raised portion;

the via hole comprises a first via hole, and the first via hole penetrates through the flat layer and the first raised part;

the position, opposite to the first raised part and far away from the first raised part, in the flat layer is convex so as to form a first retaining wall around the first via hole;

the electrode layer comprises a pixel electrode which is electrically connected with the source electrode or the drain electrode of the transistor through the first via hole.

Optionally, the driving layer further includes a common line disposed at the same layer as the gate electrode of the transistor;

the heightening part also comprises a second heightening part which is arranged at the same layer as the first heightening part;

the via hole further comprises a second via hole, and the second via hole penetrates through the flat layer and the second raised part;

the position, opposite to the second raised part and far away from the second raised part, in the flat layer is convex so as to form a second retaining wall around the second via hole;

the electrode layer further comprises a common electrode, the common electrode and the pixel electrode are arranged on the same layer, and the common electrode is connected with the common line through the second through hole.

Optionally, a light shielding portion is further disposed between the driving layer and the planarization layer, and an orthographic projection of the light shielding portion on the substrate covers a non-light-transmitting structure of the driving layer, where the non-light-transmitting structure includes at least one of a transistor, a scan line, a data line, and a common line; wherein,

the shading part comprises the raised part; or

The raised part is positioned on one side of the light shielding part far away from the driving layer, and the orthographic projection of the raised part on the substrate base plate is positioned in the orthographic projection of the light shielding part on the substrate base plate.

Optionally, the color resistances of the plurality of different colors include a red color resistance and a blue color resistance;

the shading part comprises a first film layer and a second film layer which are sequentially stacked, the first film layer and the red color resistor are arranged on the same layer, and the second film layer and the blue color resistor are arranged on the same layer.

Optionally, the color resistances of the plurality of different colors further include a green color resistance;

when the raised part is positioned on one side of the light shielding part far away from the driving layer and the orthographic projection of the raised part on the substrate is positioned in the orthographic projection of the light shielding part on the substrate, the raised part and the green color resistance layer are arranged at the same layer.

Optionally, when the raised portion is disposed around the via:

the inner wall of the raised part belongs to a part of the hole wall of the through hole; or

A gap is formed between the inner wall of the raised part and the hole wall of the through hole.

Optionally, the outer diameter of the pad height part is 16 to 60 micrometers, the inner diameter of the pad height part is 8 to 50 micrometers, and the thickness of the pad height part is 0.5 to 3 micrometers;

when a gap is formed between the inner wall of the raised part and the hole wall of the through hole, the gap between the inner wall of the retaining wall and the hole wall of the through hole is 5-15 micrometers.

The present application also provides a display panel, including:

the array substrate of any of the above;

an opposite substrate arranged opposite to the array substrate and provided to the box;

and a liquid crystal layer disposed between the array substrate and the opposite substrate.

The application discloses display panel and display device has following beneficial effect:

in the application, the heightening part is arranged at the position of the via hole on one side of the flat layer, and when the flat layer is formed, the heightening part enables the flat layer to be partially protruded on one side far away from the heightening part so as to surround the via hole to form a retaining wall, so that the alignment liquid is blocked by the retaining wall and is difficult to diffuse into the via hole in the subsequent process of coating the alignment liquid to form the alignment layer, and the design can improve the phenomenon of uneven thickness of the alignment layer on the periphery of the via hole, thereby improving the display image quality of the display panel.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an array substrate according to a second embodiment of the present application;

fig. 3 is a schematic structural diagram of an array substrate according to a third embodiment of the present application;

fig. 4 is an enlarged structural schematic view of a via hole position of an array substrate in the third embodiment of the present application;

fig. 5 is a schematic structural diagram of a display panel in the fourth embodiment of the present application.

Description of reference numerals:

100. an array substrate;

110. a substrate base plate;

120. a drive layer; 121. a first metal layer; 1211. a gate electrode; 1212. a common line; 122. an insulating layer; 123. an active layer; 124. a second metal layer; 1241. a source electrode; 1242. a drain electrode; 125. a passivation layer;

130. a planarization layer; 131. a first retaining wall; 132. a second retaining wall; 133. a first via hole; 134. a second via hole;

140. an electrode layer; 141. a pixel electrode; 142. a common electrode;

150. an alignment layer;

160. a raised portion; 161. a first raised portion 162, a second raised portion;

170. color resistance;

180. a light shielding portion; 181. a first film layer; 182. a second film layer;

200. an opposing substrate; 300. and a liquid crystal layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

The present application will be described in further detail with reference to the following drawings and specific examples. It should be noted that the technical features mentioned in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

Example one

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure, and referring to fig. 1, the array substrate includes a substrate 110, and a driving layer 120, a planarization layer 130, an electrode layer 140, and an alignment layer 150 sequentially formed on the substrate 110. The flat layer 130 is partially opened with a via hole, and the electrode layer 140 is electrically connected to the driving layer 120 through the via hole penetrating the flat layer 130.

The side of the flat layer 130 away from the electrode layer 140 is provided with a raised portion 160, specifically, the raised portion 160 may be disposed between the driving layer 120 and the flat layer 130, and the raised portion 160 is disposed near the via hole. The flat layer 130 is protruded at a position opposite to the raised portion 160 and far from the raised portion 160 to form a retaining wall around the via hole. That is, the raised portion 160 is formed on the substrate 110 before the planarization layer 130, so that when the planarization layer 130 is formed, the raised portion 160 is disposed to partially protrude the planarization layer 130 away from the raised portion 160, i.e. the raised structure surrounds the via retaining wall.

It should be noted that, the shape of the raised portion 160 is not limited, and it may be disposed around the via hole to form a ring structure, or may be discontinuous, that is, the formed ring structure may have a partial gap. Accordingly, the retaining wall may be a ring-shaped structure surrounding the via hole, or may be discontinuous. In this embodiment, the raised portion 160 and the retaining wall are both annular structures, and the retaining wall can enclose the via hole, so as to obtain a better blocking effect.

The substrate base plate 110 may be a glass base plate, but is not limited thereto, and may also be a polyimide base plate, as the case may be. The array substrate is formed by a multi-layer film structure, which may include a whole-surface film layer, such as the alignment layer 150, the planarization layer 130, etc., or a non-whole-surface film layer, which includes a plurality of independent pattern blocks, such as: electrode layer 140, and the film layer on which raised portion 160 is located.

Wherein the driving layer 120 may be formed of a multi-layer film layer structure; the raised portion 160 is not limited to be disposed between the driving layer 120 and the flat layer 130, and may be disposed in the same layer as at least one of the film structures in the driving layer 120, as the case may be.

It should be understood that "same layer arrangement" in this application refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern and then using the same mask plate through a single patterning process, that is, a single patterning process corresponds to one mask plate (also referred to as a reticle). Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. Thereby simplifying the manufacturing process, saving the manufacturing cost and improving the production efficiency.

The alignment layer 150 covers all the above film structures, and when the array substrate and the opposite substrate form a display panel, the alignment layer 150 may contact the liquid crystal layer to achieve the desired orientation of the liquid crystal. The alignment layer 150 may be made of polyimide by inkjet printing.

In the present application, the raised portion 160 is disposed at the via hole on one side of the flat layer 130, and when the flat layer 130 is formed, the raised portion 160 causes a portion of the flat layer 130 away from the raised portion 160 to protrude to surround the via hole to form a retaining wall, so that the alignment liquid is blocked by the retaining wall and is difficult to diffuse into the via hole in the subsequent process of applying the alignment liquid to form the alignment layer 150, and thus the design can improve the uneven thickness of the alignment layer 150 around the via hole, thereby improving the display quality of the display panel.

Referring to fig. 1, the array substrate further includes a color resistor 170, and the color resistor 170 is disposed between the flat layer 130 and the driving layer 120, that is, the driving layer 120, the color resistor 170 and the flat layer 130 are sequentially formed. The color resistor 170 includes a plurality of different color resistors including, for example, a red color resistor, a green color resistor, a blue color resistor, and so on.

In this embodiment, the color resistor 170 is disposed between the planarization layer 130 and the driving layer 120, that is, the array substrate of this embodiment adopts a COA (color Filter on array) technology, and compared with a scheme in which the color resistor 170 is disposed on the opposite substrate, the alignment difficulty between the opposite substrate and the array substrate can be properly reduced by the COA technology of this embodiment, that is: the difficulty of box processing in the preparation process of the display panel is reduced, so that the error of box processing can be reduced, the line width of the shielding layer (namely, a black matrix) can be properly reduced, and the display aperture ratio is improved. Meanwhile, the color resistor 170 is disposed on the array substrate, so that the distance between the electrode layer 140 and the driving layer 120 can be increased, and thus the parasitic capacitance generated between the electrode layer 140 and the driving layer 120 can be reduced, thereby improving the display effect.

The height portion 160 is disposed on the same layer as at least one of the color resistors of different colors, and as for the red color resistor, the green color resistor or the blue color resistor, the present embodiment is not limited as the case may be. The color resistor 170 may be made of an organic material.

The pad height part 160 and at least one color resistance of a plurality of color resistances with different colors are arranged in the same layer, and the formation of the pad height part 160 and the color resistance 170 can be completed in the same process, so that the formation process of the array substrate can be simplified, the production cost is reduced, and meanwhile, the alignment liquid is blocked by a retaining wall formed by the pad height part 160 and is difficult to diffuse into the via hole, so that the design can improve the phenomenon of uneven thickness of the alignment layer 150 at the periphery of the via hole, and the display image quality of the display panel is improved.

In addition, since the color resistor 170 is made of an organic material, by disposing the pad-up portion 160 and the color resistor 170 in the same layer, the thickness of the pad-up portion 160 can be increased appropriately compared to the inorganic film layer, so that the thickness difference between the retaining wall and other positions is more significant, and the effect of blocking the diffusion of the alignment liquid is also more significant.

Illustratively, the driving layer 120 specifically includes a first metal layer 121, an insulating layer 122, an active layer 123, a second metal layer 124 and a passivation layer 125 sequentially formed on the substrate base plate 110, wherein the insulating layer 122 and the passivation layer 125 may be full-surface film layers, and the first metal layer 121, the active layer 123 and the second metal layer 124 may be non-full-surface film layers.

In this embodiment, the first metal layer 121 may include a gate 1211 and a common line 1212, and the second metal layer 124 may include a source 1241 and a drain 1242, wherein the source 1241, the drain 1242, the gate 1211, and the active layer 123 may be configured as a transistor, that is, the driving layer 120 may include a transistor. It should be understood that the driving layer 120 is not limited to include a transistor, and may further include a scan line (not shown) disposed on the same layer as the gate 1211 and connected thereto, and a data line (not shown) disposed on the same layer as the source 1241 and the drain 1242, the data line being connected to the source 1241 or the drain 1242.

The electrode layer 140 may include a pixel electrode 141 and a common electrode 142 disposed on the same layer, and it should be understood that the pixel electrode 141 and the common electrode 142 may be both slit electrodes, and electrode strips of the two slit electrodes are alternately arranged, so that the pixel electrode 141 and the common electrode 142 are disposed on the same layer, which may increase a viewing angle and improve a display effect.

The via hole may include a first via hole 133 and a second via hole 134, the pixel electrode 141 is electrically connected to the source electrode 1241 or the drain electrode 1242 of the transistor through the first via hole 133, and the common electrode 142 is electrically connected to the common line 1212 through the second via hole 134.

The pad up 160 may include a first pad up 161, and the first pad up 161 may be disposed between the passivation layer 125 and the planarization layer 130. The flat layer 130 is protruded at a position opposite to the first raised portion 161 and far away from the first raised portion 161 to form a first retaining wall 131 surrounding the first via 133.

The aforementioned first via 133 may penetrate through the planarization layer 130 and the first pad-up portion 161, and may also penetrate through the passivation layer 125 of the driving layer; the pixel electrode 141 is electrically connected to the source 1241 or the drain 1242 of the transistor through the first via 133. It should be understood that the position of the first via 133 is a non-light-transmitting region, and the position of the color resistor 170 on the side of the first raised portion 161 is a light-transmitting region, so as to perform a light-emitting display.

In this embodiment, by providing the first raised portion 161, when the planarization layer 130 is formed, the first raised portion 161 can make a portion of the planarization layer 130 away from the first raised portion 161 protrude to form the first wall 131 surrounding the first via 133, and the first wall 131 surrounds the first via 133, so that the alignment liquid is blocked by the first wall 131 and is difficult to diffuse into the first via 133 in the subsequent process of applying the alignment liquid to form the alignment layer 150, and this design can improve the uneven thickness of the alignment layer 150 around the first via 133, thereby improving the display quality of the display panel; since the first via 133 is not used for displaying, the alignment layer 150 may have a non-uniform thickness but does not substantially affect the overall display effect.

In some embodiments, the raised portion 160 may further include a second raised portion 162, and the second raised portion 162 may be disposed between the passivation layer 125 and the planarization layer 130. The position of the planarization layer 130 opposite to the second raised portion 162 and far away from the second raised portion 162 is convex to form a second blocking wall 132 surrounding the second via 134.

The second raised portion 162 may be disposed on the same layer as the first raised portion 161, and the aforementioned second via 134 may penetrate through the planarization layer 130 and the second raised portion 162, and may also penetrate through the passivation layer 125 and the insulating layer 122 of the driving layer; and the common electrode 142 is electrically connected to the common line 1212 through the second via 134.

It should be understood that the position of the second via 134 is a non-light-transmitting region, and the position of the color resistor 170 on the side of the second raised portion 162 is a light-transmitting region, so as to perform a light-emitting display. In this embodiment, after the alignment liquid is coated, the alignment liquid is blocked by the second blocking wall 132 and cannot diffuse into the second via hole 134, so that the non-uniform thickness of the alignment layer 150 around the second via hole 134 can be improved, and the display quality of the display panel can be improved; however, since the second via 134 is not used for displaying, the alignment layer 150 does not have a uniform thickness but does not affect the display.

In addition, the second raised portion 162 may be disposed on the same layer as the first raised portion 161, for example: are all arranged in the same layer as the color resistor 170, so that the thicknesses of the second raised portion 162 and the first raised portion 161 are substantially the same, and thus the thicknesses of the first retaining wall 131 and the second retaining wall 132 formed by the flat layer 130 are substantially the same, and the blocking effects of the first retaining wall 131 and the second retaining wall 132 are substantially the same.

It should be understood that the second raised portion 162 is not limited to being disposed at the same layer as the first raised portion 161, and the second raised portion 162 and the first raised portion 161 may be disposed at different layers, such as: the first pad-up portion 161 may be disposed at the same layer as at least one of the red color resistor, the green color resistor and the blue color resistor, and the second pad-up portion 162 may be formed during the fabrication of the second metal layer 124, that is, the second pad-up portion 162 may be disposed at the same layer as the data line, the source electrode 1241 or the drain electrode 1242, as the case may be.

In the present embodiment, the raised portion 160 is disposed around the via, and specifically, the first raised portion 161 may be disposed around the first via 133, and the second raised portion 162 may be disposed around the second via 134, that is, both the first raised portion 161 and the second raised portion 162 are annular structures.

Wherein, the outer diameter of the first raised portion 161 and the second raised portion 162 may be 16 micrometers to 60 micrometers, preferably 16 micrometers to 40 micrometers, such as: 16 microns, 30 microns, 35 microns, 40 microns and the like, it should be understood that the outer diameters of the first retaining wall 131 and the second retaining wall 132 can be substantially equal to the outer diameters of the first raised portion 161 and the second raised portion 162, so that the design can avoid the situation that the radial sizes of the raised portion and the retaining wall are too large to squeeze the space occupied by the light transmission region, thereby ensuring the pixel aperture ratio, and can avoid the situation that the radial sizes of the raised portion and the retaining wall are too small to facilitate the processing of the via hole.

The inner diameters of the first raised portion 161 and the second raised portion 162 may be set to 8 micrometers to 50 micrometers, preferably 10 micrometers to 26 micrometers, such as: 10 microns, 16 microns, 26 microns and the like, it should be understood that the inner diameters of the first retaining wall 131 and the second retaining wall 132 may be slightly larger than or substantially equal to the inner diameters of the first raised portion 161 and the second raised portion 162 for process reasons, that is, the inner diameters of the first retaining wall 131 and the second retaining wall 132 are also set to be 8 microns to 50 microns, preferably 10 microns to 26 microns, so that the design can prevent the situation that the inner diameters of the raised portion and the retaining wall are too large to cause more alignment liquid to easily flow into the via hole on one hand, and the inner diameters of the raised portion and the retaining wall are too small to cause the electrode at the via hole to easily break on the other hand.

The thickness of the first raised portion 161 and the second raised portion 162 may be 0.5 to 3 micrometers, preferably 1 to 2 micrometers, such as: 1 micron, 1.5 microns, 2 microns and the like, it should be understood that the thickness of the first retaining wall 131 and the second retaining wall 132 may be substantially equal to the thickness of the first raised portion 161 and the second raised portion 162, so that the design can avoid the situation that the electrodes at the via holes are easy to break due to the excessive thickness of the raised portions and the retaining walls on one hand, and can avoid the situation that the alignment liquid is difficult to block flowing into the via holes due to the insufficient thickness of the raised portions and the retaining walls on the other hand.

In this embodiment, the inner wall of the raised portion 160 may belong to a part of the hole wall of the via hole, and it should be understood that the inner wall of the retaining wall corresponding to the raised portion 160 may also belong to a part of the hole wall of the via hole, that is, before the via hole is made, the protruding portion corresponding to the raised portion 160 on the planar layer 130 and the raised portion 160 are not designed to be opened, and the opening thereon is formed together when the via hole is made, so that the alignment difficulty during the via hole making can be reduced, that is: since the raised portion 160 is not perforated in advance, alignment between the via and the raised portion can be omitted, thereby properly reducing the alignment difficulty during via fabrication.

Example two

Fig. 2 is a schematic structural diagram of an array substrate in a second embodiment of the present application, and referring to fig. 1 and fig. 2, the difference between the structure of the array substrate in the second embodiment and the structure of the array substrate in the first embodiment is: in the second embodiment, a light shielding portion 180 is further disposed between the driving layer 120 and the planarization layer 130 of the array substrate.

The orthographic projection of the light shielding part 180 on the substrate 110 covers at least part of the non-light-transmitting structure of the driving layer 120, the non-light-transmitting structure may include the transistors, the scan lines, the data lines and the common lines 1212 mentioned in the first embodiment, and the transistors, the scan lines, the data lines and the common lines 1212 may be located in the display region of the entire substrate. It should be understood that the substrate may further include a non-display region disposed around the display region, and the non-display region may also include some non-light-transmitting structures, such as: metal traces and pads, etc.

Specifically, the light shielding portion 180 may completely cover the non-light-transmitting structure on the driving layer 120 in the display region, that is: the structures such as transistors, scanning lines, data lines and common lines 1212 of the driving layer 120 can be completely covered, and the light shielding part 180 is disposed on the array substrate, so that a black matrix in the display area of the opposite substrate can be eliminated, that is, the light shielding part 180 can replace the black matrix in the display area of the opposite substrate, and the design properly reduces the alignment difficulty of the array substrate and the opposite substrate in the box alignment process, thereby properly reducing the box alignment error, and properly designing the line width of the light shielding part 180 according to the size of the shielded non-light-transmitting structure to improve the aperture ratio.

The light shielding portion 180 is not limited to be located in the display region, and may be located in the non-display region to shield the non-light-transmitting structure in the non-display region. It should be understood that if the non-display area of the array substrate is not provided with the light shielding portion 180, a black matrix may be provided in the non-display area of the opposite substrate to shield the non-display area of the array substrate after the cell is set, as the case may be.

In one example, the light shielding portion 180 may include a raised portion 160, that is, the raised portion 160 may belong to a portion of the light shielding portion 180, and the raised portion 160 not only enables the flat layer 130 to form a retaining wall, but also shields the non-light-transmitting structure of the driving layer 120.

In another example, the raised portion 160 is disposed separately from the light shielding portion 180, and specifically, the raised portion 160 may be located on a side of the light shielding portion 180 away from the driving layer 120, that is, the light shielding portion 180 is formed on the substrate 110 first, and then the raised portion 160 is formed. The orthographic projection of the raised portion 160 on the substrate 110 is located within the orthographic projection of the light shielding portion 180 on the substrate 110, that is, the size of the raised portion 160 is smaller than that of the light shielding portion 180, the light shielding portion 180 is mainly used for shielding the metal structure of the driving layer 120, and the raised portion 160 is mainly used for enabling the flat layer 130 to form a retaining wall around the via hole.

In the embodiment, by providing the light-shielding portion 180, when the flat layer 130 is formed, the area of the flat layer 130 corresponding to the light-shielding portion 180 is protruded compared with other areas (i.e., the area including the light-emitting area), and the via hole is located in the area where the light-shielding portion 180 is located, so that the alignment liquid in the light-emitting area can be prevented from flowing into the via hole; further, the raised portion 160 is formed in a local region of the light shielding portion 180, so that when the planarization layer 130 is formed, a region of the planarization layer 130 corresponding to the raised portion 160 is protruded compared to regions corresponding to other regions of the light shielding portion 180, and thus is protruded more significantly compared to a light emitting region not corresponding to the light shielding portion 180, and therefore, the alignment liquid can be further blocked from flowing into the via hole.

For example, the light shielding portion 180 may include a first film layer 181 and a second film layer 182 sequentially stacked, and specifically, the first film layer 181 is formed on the passivation layer 125, and the second film layer 182 is formed on the first film layer 181.

The first film layer 181 is disposed on the same layer as the red color resist, and the second film layer 182 is disposed on the same layer as the blue color resist, that is, the light shielding portion 180 of the present embodiment can be formed along with the red color resist and the blue color resist, so that the process can be simplified and the cost can be reduced while the shielding effect is achieved.

Further, the present embodiment utilizes the stacked red color resists and blue color resists as the light shielding portion 180, and the light shielding portion 180 is formed to have a darker light shielding color than the scheme utilizing the stacked red color resists and green color resists as the light shielding portion 180 or the scheme utilizing the stacked blue color resists and green color resists as the light shielding portion 180, that is: the mixed color of red plus blue is magenta (or magenta), the mixed color of blue plus green is cyan, the mixed color of red plus green is yellow, and the light-shielding property of magenta (or magenta) is greater than that of cyan and yellow, so that the light-shielding effect is better by using the stacked red color resist and blue color resist as the light-shielding portion 180.

The light shielding portion 180 is not limited to the red color resist and the blue color resist, and other light shielding materials such as a black matrix material may be used as appropriate.

When the light shielding portion 180 is disposed in the same layer as the red color resist and the blue color resist, and the orthographic projection of the raised portion 160 on the substrate 110 is located within the orthographic projection of the light shielding portion 180 on the substrate 110, the raised portion 160 may be disposed in the same layer as the green color resist. That is, on the passivation layer 125, the first film 181 of the red color barrier of the light transmission region and the non-light transmission region is formed, the second film 182 of the blue color barrier of the light transmission region and the non-light transmission region is formed, and the step-up portion 160 of the green color barrier of the light transmission region and the non-light transmission region is formed.

It should be understood that the positions of the first and second film layers 181 and 182 may be reversed, that is, the second film layer 182 is formed on the passivation layer 125 first, and then the first film layer 181 is formed on the first film layer 181. That is, the color resists 170 may be formed in the order of red, blue, and green resists, or may be formed in the order of blue, red, and green resists.

EXAMPLE III

Fig. 3 is a schematic structural diagram of an array substrate in a third embodiment of the present application, and fig. 4 is an enlarged structural diagram of a via hole position of the array substrate in the third embodiment of the present application, and referring to fig. 3 and fig. 4, the main difference between the third embodiment and the first embodiment is that: the mating relationship of the raised portion 160 and the vias is different.

Specifically, in the first embodiment, the inner wall of the raised portion 160 belongs to a part of the hole wall of the via hole; in the third embodiment, there is a gap between the inner wall of the raised portion 160 and the hole wall of the via hole, it should be understood that, since the raised portion 160 is raised to form a retaining wall on the side of the flat layer 130, there is a gap between the inner wall of the retaining wall and the hole wall of the via hole, that is: the aperture of the via hole is smaller than the inner diameters of the raised portion 160 and the retaining wall, and a step surface located inside the retaining wall is formed between the via hole and the retaining wall.

In other words, before the via hole is formed, the dam and the raised portion have been formed with an opening, which is larger than the via hole.

In this embodiment, since a gap is formed between the inner wall of the retaining wall and the hole wall of the via hole, a step surface for connecting the inner wall of the retaining wall and the hole wall of the via hole is formed between the inner wall of the retaining wall and the hole wall of the via hole, and the step surface is used for relieving the capability of the alignment liquid entering the via hole due to tension.

For example, when the inner diameter of the raised portion 160 is set to 10 to 26 micrometers, the gap between the inner wall of the retaining wall and the wall of the via hole may be 5 to 15 micrometers, that is, the width of the step surface may be 5 to 15 micrometers, preferably 8 to 13 micrometers, such as: 8 microns, 10 microns, 13 microns etc. so the design can avoid on the one hand the step face size undersize and be difficult to alleviate the condition of the alignment liquid because of tension reason gets into the ability in the via hole, and on the other hand can avoid the step face size oversize and the condition of extrusion light transmission area shared space to can guarantee the pixel aperture opening rate.

Example four

Fig. 5 is a schematic structural diagram of a display panel according to a fourth embodiment of the present disclosure, and referring to fig. 1 to 5, the display panel includes an array substrate 100, an opposite substrate 200, and a liquid crystal layer 300. The opposite substrate 200 and the array substrate 100 are disposed opposite to each other, and the liquid crystal layer 300 is disposed between the array substrate 100 and the opposite substrate 200, wherein the specific structure of the array substrate 100 can refer to the contents described in the first embodiment, the second embodiment, or the third embodiment, and will not be described repeatedly herein.

The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present application have been shown and described, it is understood that the above embodiments are illustrative and should not be construed as limiting the present application and that various changes, modifications, substitutions and alterations can be made therein by those skilled in the art within the scope of the present application, and therefore all changes and modifications that come within the meaning of the claims and the description of the invention are to be embraced therein.

Claims

1. The utility model provides an array substrate, includes the substrate base plate and forms in proper order drive layer, flat layer, electrode layer and the alignment layer on the substrate base plate, the electrode layer through running through the via hole on flat layer with the drive layer electricity is connected, its characterized in that, array substrate includes:

2. The array substrate of claim 1,

the array substrate further comprises a color resistor, the color resistor is arranged between the flat layer and the driving layer, and the color resistor comprises a plurality of color resistors with different colors;

3. The array substrate of claim 2,

the driving layer includes a transistor;

the raised portion comprises a first raised portion;

4. The array substrate of claim 3,

the driving layer further includes a common line disposed at the same layer as the gate electrode of the transistor;

5. The array substrate of claim 2, wherein a light shielding portion is further disposed between the driving layer and the flat layer, and an orthographic projection of the light shielding portion on the substrate covers a non-light-transmitting structure of the driving layer, the non-light-transmitting structure comprising at least one of a transistor, a scanning line, a data line, and a common line; wherein,

the shading part comprises the raised part; or

6. The array substrate of claim 5,

the color resistances of the different colors comprise a red color resistance and a blue color resistance;

7. The array substrate of claim 6, wherein the plurality of different color resists further comprises a green color resist;

8. The array substrate of claim 1, wherein when the raised portion is disposed around the via:

9. The array substrate of claim 8, wherein the raised portion has an outer diameter of 16 to 60 microns, an inner diameter of 8 to 50 microns, and a thickness of 0.5 to 3 microns;

10. A display panel, comprising:

an array substrate according to any one of claims 1 to 9;