CN103456747A - Array substrate, manufacturing method of array substrate and display device - Google Patents
Array substrate, manufacturing method of array substrate and display device Download PDFInfo
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- CN103456747A CN103456747A CN2013104123379A CN201310412337A CN103456747A CN 103456747 A CN103456747 A CN 103456747A CN 2013104123379 A CN2013104123379 A CN 2013104123379A CN 201310412337 A CN201310412337 A CN 201310412337A CN 103456747 A CN103456747 A CN 103456747A
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Abstract
The invention provides an array substrate, a manufacturing method of the array substrate and a display device, and belongs to the technical field of display. Public electrodes and active layers of the array substrate are located on the same layer and simultaneously formed through the once picture composition technology. By means of the technical scheme of the array substrate, the manufacturing method of the array substrate and the display device, the number of the times of the picture composition technology when the ADS array substrate is manufactured can be reduced, the production efficiency is improved, and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to the Display Technique field, particularly a kind of array base palte and preparation method thereof, display unit.
Background technology
Along with the progress of TFT industry and the improvement of technique, AD-ADS(ADvanced Super Dimension Switch, senior super Wei Chang conversion, abbreviation ADS) the wide viewing angle technology has been applied in the middle of increasing product, comprise mobile phone, digital camera, panel computer, notebook computer, reach LCD TV etc., its good display characteristic is praised highly by increasing user, and the market competitiveness is very strong.
The ADS technology is by the electric field formation multi-dimensional electric field of the electric field that in same plane, the gap electrode edge produces and gap electrode layer and the generation of plate electrode interlayer, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve TFT-LCD(Thin Film Transistor-Liquid Crystal Display, the Thin Film Transistor (TFT) liquid crystal display) picture quality of product, have high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
Due to ADS self, the TN(twisted-nematic that its Array array processes is more traditional) the product complexity, composition and Tact Time(pitch time) all increase to some extent, so cost is higher.The array base palte of existing ADS product needs 6 times or 7 composition techniques are made, the composition complex process, and cost of manufacture is higher.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, display unit, and in the time of can reducing preparation ADS array base palte, the number of times of composition technique, enhance productivity, and reduces cost of manufacture.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
On the one hand, provide a kind of array base palte, public electrode and the active layer of described array base palte are positioned at same layer, for form by a composition technique simultaneously.
Further, the public electrode of described array base palte and active layer are for adopting the transparent metal oxide semi-conducting material to make.
Further, described transparent metal oxide semi-conducting material is amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO
2, one or more in SnO, CdSnO.
Further, described array base palte specifically comprises:
Underlay substrate;
Gate electrode on described underlay substrate and grid line;
Gate insulation layer on described gate electrode and described grid line;
Public electrode on described gate insulation layer and active layer;
Data wire on described public electrode and active layer, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
Further, described array base palte specifically comprises:
Underlay substrate;
Gate electrode on described underlay substrate and grid line;
Gate insulation layer on described gate electrode and described grid line;
Public electrode on described gate insulation layer and active layer;
Channel protective layer on described public electrode and active layer;
Data wire on described channel protective layer, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
Further, described array base palte specifically comprises:
Underlay substrate;
Public electrode on described underlay substrate and active layer;
Gate insulation layer on described public electrode and active layer;
Gate electrode on described gate insulation layer and grid line;
Interlayer insulating film on described gate electrode and described grid line, described interlayer insulating film includes the public electrode wire via hole of the source electrode via hole of corresponding described active layer and drain electrode via hole, corresponding described public electrode; Described source electrode via hole, drain electrode via hole, public electrode wire via hole also run through gate insulation layer;
Data wire on described interlayer insulating film, source electrode, drain electrode and public electrode wire, described source electrode is connected with described active layer with the drain electrode via hole by described source electrode via hole respectively with drain electrode, and described public electrode wire is connected with described public electrode by described public electrode wire via hole;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
The embodiment of the present invention also provides a kind of display unit, comprises array base palte as above.
The embodiment of the present invention also provides a kind of manufacture method of array base palte, forms the figure of public electrode and active layer by composition technique simultaneously.
Further, described manufacture method comprises:
Deposit transparent metal oxide semiconductor layer on underlay substrate;
Form the figure of described public electrode and described active layer by described transparent metal oxide semiconductor layer of composition technology utilization simultaneously.
Further, described on underlay substrate the deposit transparent metal oxide semiconductor layer, the figure that simultaneously forms described public electrode and described active layer by described transparent metal oxide semiconductor layer of composition technology utilization comprises:
Depositing a layer thickness on underlay substrate by sputtering method is
the transparent metal oxide semiconductor layer;
Apply photoresist on described transparent metal oxide semiconductor layer, the described transparent metal oxide semiconductor layer of etching after exposure imaging, and stripping photoresist, the described public electrode that formation is comprised of described transparent metal oxide semiconductor layer and the figure of active layer.
Further, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of gate electrode and grid line by a composition technique on described underlay substrate;
Form the figure of described public electrode and active layer by a composition technique on the underlay substrate that is formed with described gate electrode and grid line;
Form the figure of data wire, source electrode, drain electrode and public electrode wire on the underlay substrate that is formed with described public electrode and active layer by composition technique, described public electrode wire is connected with described public electrode;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
Further, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of gate electrode and grid line by a composition technique on described underlay substrate;
Form the figure of described public electrode and active layer by a composition technique on the underlay substrate that is formed with described gate electrode and grid line;
Form the figure of channel protective layer by a composition technique on the underlay substrate that is formed with described public electrode and active layer;
Be formed with on the underlay substrate of described channel protective layer by a composition technique figure that forms data wire, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
Further, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of described public electrode and active layer by a composition technique on described underlay substrate;
Form the figure of gate electrode and grid line by a composition technique on the underlay substrate that is formed with described public electrode and active layer;
Form the figure of the interlayer insulating film that comprises active electrode via hole, drain electrode via hole and public electrode wire via hole by a composition technique on the underlay substrate that is formed with described gate electrode and grid line; Described source electrode via hole, drain electrode via hole, public electrode wire via hole also run through gate insulation layer;
Be formed with on the underlay substrate of described interlayer insulating film by a composition technique figure that forms data wire, source electrode, drain electrode and public electrode wire, described source electrode is connected with described active layer with the drain electrode via hole by described source electrode via hole respectively with drain electrode, and described public electrode wire is connected with described public electrode by described public electrode wire via hole;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
Embodiments of the invention have following beneficial effect:
In such scheme, public electrode and the active layer of ADS array base palte are positioned at same layer, for form by a composition technique simultaneously.When the present invention can reduce preparation ADS array base palte, the number of times of composition technique, enhance productivity, and reduces cost of manufacture.
The accompanying drawing explanation
The floor map of the ADS array base palte that Fig. 1 is the embodiment of the present invention one;
The generalized section of the ADS array base palte that Fig. 2 is the embodiment of the present invention one channel-etch type;
The generalized section of the ADS array base palte that Fig. 3 is the embodiment of the present invention one raceway groove protection type;
Fig. 4 is that the embodiment of the present invention one forms the floor map of structure for the first time after composition technique;
Fig. 5 is that the embodiment of the present invention one forms the generalized section of structure for the first time after composition technique;
Fig. 6 is that the embodiment of the present invention one forms the floor map of structure for the second time after composition technique;
Fig. 7 is that the embodiment of the present invention one forms the generalized section of structure for the second time after composition technique;
Fig. 8 is that the embodiment of the present invention one forms the floor map of structure for the third time after composition technique;
Fig. 9 is that the embodiment of the present invention one forms the generalized section of structure for the third time after composition technique;
Figure 10 forms the floor map of structure after the 4th composition technique of the embodiment of the present invention 1;
Figure 11 forms the generalized section of structure after the 4th composition technique of the embodiment of the present invention 1;
The floor map of the ADS array base palte that Figure 12 is the embodiment of the present invention two;
The generalized section of the ADS array base palte that Figure 13 is the embodiment of the present invention two;
Figure 14 is that the embodiment of the present invention two forms the floor map of structure for the first time after composition technique;
Figure 15 is that the embodiment of the present invention two forms the generalized section of structure for the first time after composition technique;
Figure 16 is that the embodiment of the present invention two forms the floor map of structure for the second time after composition technique;
Figure 17 is that the embodiment of the present invention two forms the generalized section of structure for the second time after composition technique;
Figure 18 is that the embodiment of the present invention two forms the floor map of structure for the third time after composition technique;
Figure 19 is that the embodiment of the present invention two forms the generalized section of structure for the third time after composition technique;
Figure 20 forms the floor map of structure after the 4th composition technique of the embodiment of the present invention 2;
Figure 21 forms the generalized section of structure after the 4th composition technique of the embodiment of the present invention 2;
Figure 22 forms the floor map of structure after the 5th composition technique of the embodiment of the present invention 2;
Figure 23 forms the generalized section of structure after the 5th composition technique of the embodiment of the present invention 2.
Reference numeral
110,210 underlay substrate 120,220 grid line 121,221 gate electrodes
122,215 gate insulation layer 131,211 active layer 132,212 public electrodes
140,240 data wire 141,241 source electrode 142,242 drain electrodes
143,243 public electrode wire 151,219 passivation layer 152,251 passivation layer via hole
161,261 pixel electrode 231 source electrode via hole 232 drain electrode via holes
233 public electrode wire via hole 135 etching barrier layers
Embodiment
For technical problem, technical scheme and advantage that embodiments of the invention will be solved is clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Embodiments of the invention for prior art when the preparation ADS array base palte, the composition complex process, the problem that cost of manufacture is higher, a kind of array base palte and preparation method thereof, display unit are provided, the number of times of composition technique while reducing preparation ADS array base palte, enhance productivity, reduce cost of manufacture.
The embodiment of the present invention provides a kind of array base palte, and public electrode and the active layer of described array base palte are positioned at same layer, for form by a composition technique simultaneously.
Public electrode and the active layer of array base palte of the present invention are positioned at same layer, for form by a composition technique simultaneously.When the present invention can reduce preparation ADS array base palte, the number of times of composition technique, enhance productivity, and reduces cost of manufacture.
Further, the public electrode of described array base palte and active layer are for adopting the transparent metal oxide semi-conducting material to make.Described transparent metal oxide semi-conducting material can be amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO
2, one or more in SnO, CdSnO.
Further, described array base palte specifically can comprise:
Underlay substrate;
Gate electrode on described underlay substrate and grid line;
Gate insulation layer on described gate electrode and described grid line;
Public electrode on described gate insulation layer and active layer;
Data wire on described public electrode and active layer, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
Further, described array base palte specifically can comprise:
Underlay substrate;
Gate electrode on described underlay substrate and grid line;
Gate insulation layer on described gate electrode and described grid line;
Public electrode on described gate insulation layer and active layer;
Channel protective layer on described public electrode and active layer;
Data wire on described channel protective layer, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
Further, described array base palte specifically can comprise:
Underlay substrate;
Public electrode on described underlay substrate and active layer;
Gate insulation layer on described public electrode and active layer;
Gate electrode on described gate insulation layer and grid line;
Interlayer insulating film on described gate electrode and described grid line, described interlayer insulating film includes the public electrode wire via hole of the source electrode via hole of corresponding described active layer and drain electrode via hole, corresponding described public electrode; Described source electrode via hole, drain electrode via hole, public electrode wire via hole also run through gate insulation layer;
Data wire on described interlayer insulating film, source electrode, drain electrode and public electrode wire, described source electrode is connected with described active layer with the drain electrode via hole by described source electrode via hole respectively with drain electrode, and described public electrode wire is connected with described public electrode by described public electrode wire via hole;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
The embodiment of the present invention also provides a kind of display unit, comprises above-mentioned array base palte.Wherein, the structure of array base palte, with above-mentioned embodiment, does not repeat them here.In addition, the structure of other parts of display unit can, with reference to prior art, be not described in detail this this paper.This display unit can be: liquid crystal panel, Electronic Paper, LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any Presentation Function.
The embodiment of the present invention provides a kind of manufacture method of array base palte, forms the figure of public electrode and active layer by composition technique simultaneously.
The manufacture method of array base palte of the present invention when preparation ADS array base palte, forms public electrode and the active layer of array base palte simultaneously by composition technique.When the present invention can reduce preparation ADS array base palte, the number of times of composition technique, enhance productivity, and reduces cost of manufacture.
Particularly, the embodiment of the present invention adopts the transparent metal oxide semiconductor layer to prepare public electrode and active layer, at first deposit transparent metal oxide semiconductor layer on underlay substrate; Form afterwards the figure of described public electrode and described active layer by described transparent metal oxide semiconductor layer of composition technology utilization simultaneously.Described transparent metal oxide semiconductor layer can adopt amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO
2, one or more in SnO, CdSnO make.
Particularly, when making the channel-etch type ADS array base palte of bottom grating structure, described manufacture method comprises:
One underlay substrate is provided;
Form the figure of gate electrode and grid line by a composition technique on described underlay substrate;
Form the figure of described public electrode and active layer by a composition technique on the underlay substrate that is formed with described gate electrode and grid line;
Form the figure of data wire, source electrode, drain electrode and public electrode wire on the underlay substrate that is formed with described public electrode and active layer by composition technique, described public electrode wire is connected with described public electrode;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
Particularly, when making the raceway groove protection type ADS array base palte of bottom grating structure, described manufacture method comprises:
One underlay substrate is provided;
Form the figure of gate electrode and grid line by a composition technique on described underlay substrate;
Form the figure of described public electrode and active layer by a composition technique on the underlay substrate that is formed with described gate electrode and grid line;
Form the figure of channel protective layer by a composition technique on the underlay substrate that is formed with described public electrode and active layer;
Be formed with on the underlay substrate of described channel protective layer by a composition technique figure that forms data wire, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
Particularly, the described figure that forms described public electrode and active layer by composition technique on the underlay substrate that is formed with described gate electrode and grid line comprises:
Depositing a layer thickness on the underlay substrate that is formed with described gate electrode and grid line by sputtering method is
the transparent metal oxide semiconductor layer;
Apply photoresist on described transparent metal oxide semiconductor layer, the described transparent metal oxide semiconductor layer of etching after exposure imaging, and stripping photoresist, the described public electrode that formation is comprised of described transparent metal oxide semiconductor layer and the figure of active layer.
Further, when making the ADS array base palte of top gate type, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of described public electrode and active layer by a composition technique on described underlay substrate;
Form the figure of gate electrode and grid line by a composition technique on the underlay substrate that is formed with described public electrode and active layer;
Form the figure of the interlayer insulating film that comprises active electrode via hole, drain electrode via hole and public electrode wire via hole by a composition technique on the underlay substrate that is formed with described gate electrode and grid line; Described source electrode via hole, drain electrode via hole, public electrode wire via hole also run through gate insulation layer;
Be formed with on the underlay substrate of described interlayer insulating film by a composition technique figure that forms data wire, source electrode, drain electrode and public electrode wire, described source electrode is connected with described active layer with the drain electrode via hole by described source electrode via hole respectively with drain electrode, and described public electrode wire is connected with described public electrode by described public electrode wire via hole;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
Below in conjunction with specific embodiment, array base palte of the present invention and preparation method thereof is described in detail:
Embodiment mono-
Can make the channel-etch type ADS array base palte of bottom grating structure by the present embodiment, as shown in Figure 1, Fig. 2 is along the generalized section of the hatching I-I ' position of two ends arrow in Fig. 1 to the structure of the channel-etch type ADS array base palte of this bottom grating structure.In the present embodiment, adopt transparent metal oxide semi-conducting material manufacturing public electrode and active layer, adopt the making that 5 times composition technique can complete channel-etch type ADS array base palte, manufacture craft is simple, can reduce production costs.
The manufacture method of the array base palte of the present embodiment comprises the following steps:
Step a1 a: underlay substrate 110 is provided, by a composition technique, forms the figure of gate electrode 121 and grid line 120 on underlay substrate 110;
One underlay substrate 110 is provided, forms the figure that comprises gate electrode and the grid line be connected with gate electrode formed by the grid metal level on underlay substrate 110.Wherein, underlay substrate 110 can be glass substrate or quartz base plate.
Particularly, can adopt the method for sputter or thermal evaporation to deposit a layer thickness on underlay substrate 110 to be
the grid metal level, the grid metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, the grid metal level can be single layer structure or sandwich construction, sandwich construction is such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Apply one deck photoresist on the grid metal level, adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of grid line and gate electrode, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away the not grid metallic film of reserve area of photoresist fully by etching technics, peel off remaining photoresist, form the figure of grid line 120 and gate electrode 121, as shown in Figure 4 and Figure 5.
Step a2: by a composition technique, form the figure of public electrode 132 and active layer 131 on underlay substrate 110;
Particularly, can strengthen chemical vapour deposition (CVD) (PECVD) method by using plasma, on the underlay substrate 110 through step a1, deposit thickness is about
gate insulation layer 122, wherein, the gate insulation layer material can be selected oxide, nitride or nitrogen oxide, gate insulation layer can be individual layer, bilayer or sandwich construction.Particularly, gate insulation layer can be SiNx, SiOx or Si (ON) x.
On gate insulation layer, adopt afterwards magnetron sputtering, thermal evaporation or other film build method deposition a layer thickness to be about
the transparent metal oxide semiconductor layer, the transparent metal oxide semiconductor layer can be selected amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO2, SnO, CdSnO or other metal oxide semiconductor materials.Apply photoresist on the transparent metal oxide semiconductor layer, exposed, developed, etching transparent metal oxide semiconductor layer, and stripping photoresist, the active layer 131 that formation is comprised of the transparent metal oxide semiconductor layer and the figure of public electrode 132, as shown in Figure 6 and Figure 7.
Step a3: form the figure of data wire 140, source electrode 141, drain electrode 142 and public electrode wire 143 by a composition technique on underlay substrate 110, public electrode wire 143 is connected with public electrode 132;
Particularly, on the underlay substrate 110 through step a2, adopt magnetron sputtering, thermal evaporation or other film build method deposition a layer thickness to be about
source leak metal level, it can be Cu that metal level is leaked in source, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metal such as W and these metals.It can be single layer structure or sandwich construction that metal level is leaked in source, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Leak on metal level and apply one deck photoresist in source, adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of source electrode, drain electrode, public electrode wire and data wire, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away photoresist fully by etching technics and do not leak metallic film in the source of reserve area, peel off remaining photoresist, form the figure of data wire 140, source electrode 141, drain electrode 142 and public electrode wire 143, as shown in Figure 8 and Figure 9, public electrode wire 143 is electrically connected with public electrode 132.
Step a4: by a composition technique, form the figure of the passivation layer 151 that includes passivation layer via hole 152 on underlay substrate 110;
Particularly, on the underlay substrate 110 through step a3, adopt magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness to be
passivation material, wherein, passivation material can be selected oxide, nitride or nitrogen oxide, particularly, passivation layer can be SiNx, SiOx or Si (ON) x.Passivation layer can be single layer structure, can be also the double-layer structure that adopts silicon nitride and silica to form.
Coating one deck photoresist on passivation material; Adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of passivation layer, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away the not passivation material of reserve area of photoresist fully by etching technics, peel off remaining photoresist, form the figure of the passivation layer 151 that comprises passivation layer via hole 152, as shown in Figure 10 and Figure 11.
Step a5: form the figure of pixel electrode 161 by a composition technique on underlay substrate 110, pixel electrode 161 is connected with drain electrode 142 by passivation layer via hole 152.
Particularly, on the underlay substrate 110 through step a4, adopt magnetron sputtering, thermal evaporation or other film build method deposit thickness to be
transparency conducting layer, transparency conducting layer can be ITO or IZO.Coating one deck photoresist on transparency conducting layer; Adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of pixel electrode 161, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away the not transparency conducting layer of reserve area of photoresist fully by etching technics, peel off remaining photoresist, form the figure of pixel electrode 161, as depicted in figs. 1 and 2.Pixel electrode 161 is electrically connected by passivation layer via hole 152 and the drain electrode 142 of thin-film transistor.
Can produce array base palte as depicted in figs. 1 and 2 by above-mentioned steps a1-a5, in the array base palte of the present embodiment, the metal oxide thin-film transistor of channel-etch type is formed on the infall of grid line 120 and data wire 140, on the pixel electrode 161 of ADS array base palte, has regularly arranged slit.The ADS array base palte of the present embodiment, public electrode 132 adopts the transparent metal oxide semi-conducting material to make, the transparent metal oxide semiconductive thin film has good light permeability, and active layer 131 and public electrode 132, forming with in a composition technique, can reduce the number of times of composition technique.
Further; utilize the manufacture method of the present embodiment can also make the raceway groove protection type ADS array base palte of bottom grating structure; as shown in Figure 3; raceway groove protection type ADS array base palte has etching barrier layer 135; with channel-etch type ADS array base palte, compare, make raceway groove protection type ADS array base palte only need increase the step that forms etching barrier layer between step a2 and a3.
Wherein, the step of formation etching barrier layer specifically comprises:
By magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness on underlay substrate 110, be about
insulating barrier, this insulating barrier can adopt oxide, nitride or nitrogen oxide, particularly, this insulating barrier can be SiNx, SiOx or Si (ON) x.Apply photoresist on this insulating barrier, exposed, develop, etching insulating barrier, and stripping photoresist, the figure of formation channel protective layer 35.
Other composition techniques in other composition techniques in the manufacture method of raceway groove protection type ADS array base palte and the manufacture method of channel-etch type ADS array base palte are identical.
Embodiment bis-
Can make the ADS array base palte of top gate structure by the present embodiment.As shown in figure 12, Figure 13 is along the generalized section of the hatching I-I ' position of two ends arrow in Figure 12 to the structure of the ADS array base palte of existing top gate structure.In the present embodiment, adopt transparent metal oxide semi-conducting material manufacturing public electrode and active layer, adopt the making that 6 times composition technique can complete top gate structure ADS array base palte, manufacture craft is simple, can reduce production costs.
The manufacture method of the array base palte of the present embodiment comprises the following steps:
Step b1 a: underlay substrate 210 is provided, by a composition technique, forms the figure of public electrode 212 and active layer 211 on underlay substrate 210;
Provide a underlay substrate 210, the public electrode 212 that formation is comprised of the transparent metal oxide semi-conducting material on underlay substrate 210 and the figure of active layer 211.Wherein, underlay substrate 210 can be glass substrate or quartz base plate.
Particularly, on underlay substrate 210, adopt magnetron sputtering, thermal evaporation or other film build method deposition a layer thickness to be about
the transparent metal oxide semiconductor layer, the transparent metal oxide semiconductor layer can be selected amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO2, SnO, CdSnO or other metal oxide semiconductor materials.Apply photoresist on the transparent metal oxide semiconductor layer, exposed, developed, etching transparent metal oxide semiconductor layer, and stripping photoresist, the public electrode 212 that formation is comprised of the transparent metal oxide semiconductor layer and the figure of active layer 211, as shown in Figure 14 and Figure 15.
Step b2: by a composition technique, form the figure of gate electrode 221 and grid line 220 on underlay substrate 210;
Particularly, can adopt the PECVD method, on the underlay substrate 210 through step b1, deposit thickness is about
gate insulation layer 215, wherein, the gate insulation layer material can be selected oxide, nitride or nitrogen oxide, gate insulation layer can be individual layer, bilayer or sandwich construction.Particularly, gate insulation layer can be SiNx, SiOx or Si (ON) x, the double-layer structure that gate insulation layer can adopt silicon nitride and silica to form.
Form the figure that comprises gate electrode and the grid line be connected with gate electrode formed by the grid metal level on gate insulation layer 215.Particularly, can adopt the method for sputter or thermal evaporation to deposit a layer thickness on gate insulation layer 215 to be
the grid metal level, the grid metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, the grid metal level can be single layer structure or sandwich construction, sandwich construction is such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Apply one deck photoresist on the grid metal level, adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of grid line and gate electrode, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away the not grid metallic film of reserve area of photoresist fully by etching technics, peel off remaining photoresist, form the figure of grid line 220 and gate electrode 221, as shown in Figure 16 and Figure 17.
Step b3: by a composition technique, form the figure of the interlayer insulating film 217 that comprises source electrode via hole 231, drain electrode via hole 232, public electrode wire via hole 233 on underlay substrate 210; Described source electrode via hole 231, drain electrode via hole 232, public electrode wire via hole 233 also run through gate insulation layer 215;
Particularly, on the underlay substrate 210 through step b2, adopt magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness to be
insulating layer material, wherein, insulating layer material can be selected oxide, nitride or nitrogen oxide, particularly, insulating layer material can be SiNx, SiOx or Si (ON) x.Interlayer insulating film can be single layer structure, can be also the double-layer structure that adopts silicon nitride and silica to form.
Coating one deck photoresist on interlayer insulating film; Adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of interlayer insulating film, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away photoresist not interlayer insulating film and the gate insulation layer of reserve area fully by etching technics, peel off remaining photoresist, formation comprises the figure of the interlayer insulating film 217 of source electrode via hole 231, drain electrode via hole 232, public electrode wire via hole 233, as shown in Figure 18 and Figure 19.
Step b4: by a composition technique, form the figure of data wire 240, source electrode 241, drain electrode 242 and public electrode wire 243 on underlay substrate 210, public electrode wire 243 is connected with public electrode 212 by public electrode wire via hole 233, and source electrode 241, drain electrode 242 are connected with active layer 211 by source electrode via hole 231, drain electrode via hole 232 respectively;
Particularly, on the underlay substrate 210 through step b3, adopt magnetron sputtering, thermal evaporation or other film build method deposition a layer thickness to be about
source leak metal level, it can be Cu that metal level is leaked in source, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metal such as W and these metals.It can be single layer structure or sandwich construction that metal level is leaked in source, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.Leak on metal level and apply one deck photoresist in source, adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of source electrode, drain electrode, public electrode wire and data wire, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away photoresist fully by etching technics and do not leak metallic film in the source of reserve area, peel off remaining photoresist, form the figure of data wire 240, source electrode 241, drain electrode 242 and public electrode wire 243, as shown in Figure 20 and Figure 21, public electrode wire 243 is electrically connected by public electrode wire via hole 233 and public electrode 212, and source electrode 241, drain electrode 242 are connected with active layer 211 by source electrode via hole 231, drain electrode via hole 232 respectively.
Step b5: by a composition technique, form the figure of the passivation layer 219 that includes passivation layer via hole 251 on underlay substrate 210;
Particularly, on the underlay substrate 210 through step b4, adopt magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness to be
passivation material, wherein, passivation material can be selected oxide, nitride or nitrogen oxide, particularly, passivation layer can be SiNx, SiOx or Si (ON) x.Passivation layer can be single layer structure, can be also the double-layer structure that adopts silicon nitride and silica to form.
Coating one deck photoresist on passivation material; Adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of passivation layer, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away the not passivation material of reserve area of photoresist fully by etching technics, peel off remaining photoresist, form the figure of the passivation layer 219 that comprises passivation layer via hole 251, as shown in Figure 22 and Figure 23.
Step b6: form the figure of pixel electrode 261 by a composition technique on underlay substrate 210, pixel electrode 261 is connected with drain electrode 242 by passivation layer via hole 251.
Particularly, on the underlay substrate 210 through step b5, adopt magnetron sputtering, thermal evaporation or other film build method deposit thickness to be
transparency conducting layer, transparency conducting layer can be ITO or IZO.Coating one deck photoresist on transparency conducting layer; Adopt mask plate to be exposed to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, the photoresist reserve area is corresponding to the figure region of pixel electrode 261, photoresist not reserve area corresponding to the zone beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; Etch away the not transparency conducting layer of reserve area of photoresist fully by etching technics, peel off remaining photoresist, form the figure of pixel electrode 261, as shown in Figure 12 and Figure 13.Pixel electrode 261 is electrically connected by passivation layer via hole 251 and the drain electrode 242 of thin-film transistor.
Can produce array base palte as shown in Figure 12 and Figure 13 by above-mentioned steps b1-b6, in the array base palte of the present embodiment, metal oxide thin-film transistor is formed on the infall of grid line 220 and data wire 240, on the pixel electrode 261 of ADS array base palte, has regularly arranged slit.The ADS array base palte of the present embodiment, public electrode 212 adopts the transparent metal oxide semi-conducting material to make, the transparent metal oxide semiconductive thin film has good light permeability, and active layer 211 and public electrode 212, forming with in a composition technique, can reduce the number of times of composition technique.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (13)
1. an array base palte, is characterized in that, public electrode and the active layer of described array base palte are positioned at same layer, for form by a composition technique simultaneously.
2. array base palte according to claim 1, is characterized in that, the public electrode of described array base palte and active layer are for adopting the transparent metal oxide semi-conducting material to make.
3. array base palte according to claim 2, is characterized in that, described transparent metal oxide semi-conducting material is amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO
2, one or more in SnO, CdSnO.
4. according to the described array base palte of any one in claim 1-3, it is characterized in that, described array base palte specifically comprises:
Underlay substrate;
Gate electrode on described underlay substrate and grid line;
Gate insulation layer on described gate electrode and described grid line;
Public electrode on described gate insulation layer and active layer;
Data wire on described public electrode and active layer, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
5. according to the described array base palte of any one in claim 1-3, it is characterized in that, described array base palte specifically comprises:
Underlay substrate;
Gate electrode on described underlay substrate and grid line;
Gate insulation layer on described gate electrode and described grid line;
Public electrode on described gate insulation layer and active layer;
Channel protective layer on described public electrode and active layer;
Data wire on described channel protective layer, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
6. according to the described array base palte of any one in claim 1-3, it is characterized in that, described array base palte specifically comprises:
Underlay substrate;
Public electrode on described underlay substrate and active layer;
Gate insulation layer on described public electrode and active layer;
Gate electrode on described gate insulation layer and grid line;
Interlayer insulating film on described gate electrode and described grid line, described interlayer insulating film includes the public electrode wire via hole of the source electrode via hole of corresponding described active layer and drain electrode via hole, corresponding described public electrode; Described source electrode via hole, drain electrode via hole, public electrode wire via hole also run through gate insulation layer;
Data wire on described interlayer insulating film, source electrode, drain electrode and public electrode wire, described source electrode is connected with described active layer with the drain electrode via hole by described source electrode via hole respectively with drain electrode, and described public electrode wire is connected with described public electrode by described public electrode wire via hole;
Passivation layer on described data wire, source electrode, drain electrode and public electrode wire, described passivation layer includes the passivation layer via hole of corresponding described drain electrode;
Pixel electrode on described passivation layer, described pixel electrode is electrically connected to described drain electrode by described passivation layer via hole.
7. a display unit, is characterized in that, comprises array base palte as described as any one in claim 1-6.
8. the manufacture method of an array base palte, is characterized in that, forms the figure of public electrode and active layer by composition technique simultaneously.
9. the manufacture method of array base palte according to claim 8, is characterized in that, described manufacture method comprises:
Deposit transparent metal oxide semiconductor layer on underlay substrate;
Form the figure of described public electrode and described active layer by described transparent metal oxide semiconductor layer of composition technology utilization simultaneously.
10. the manufacture method of array base palte according to claim 9, it is characterized in that, described on underlay substrate the deposit transparent metal oxide semiconductor layer, the figure that simultaneously forms described public electrode and described active layer by described transparent metal oxide semiconductor layer of composition technology utilization comprises:
Depositing a layer thickness on underlay substrate by sputtering method is
the transparent metal oxide semiconductor layer;
Apply photoresist on described transparent metal oxide semiconductor layer, the described transparent metal oxide semiconductor layer of etching after exposure imaging, and stripping photoresist, the described public electrode that formation is comprised of described transparent metal oxide semiconductor layer and the figure of active layer.
11. according to Claim 8-10, the manufacture method of the described array base palte of any one, is characterized in that, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of gate electrode and grid line by a composition technique on described underlay substrate;
Form the figure of described public electrode and active layer by a composition technique on the underlay substrate that is formed with described gate electrode and grid line;
Form the figure of data wire, source electrode, drain electrode and public electrode wire on the underlay substrate that is formed with described public electrode and active layer by composition technique, described public electrode wire is connected with described public electrode;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
12. according to Claim 8-10, the manufacture method of the described array base palte of any one, is characterized in that, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of gate electrode and grid line by a composition technique on described underlay substrate;
Form the figure of described public electrode and active layer by a composition technique on the underlay substrate that is formed with described gate electrode and grid line;
Form the figure of channel protective layer by a composition technique on the underlay substrate that is formed with described public electrode and active layer;
Be formed with on the underlay substrate of described channel protective layer by a composition technique figure that forms data wire, source electrode, drain electrode and public electrode wire, described public electrode wire is connected with described public electrode;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
13. according to Claim 8-10, the manufacture method of the described array base palte of any one, is characterized in that, described manufacture method specifically comprises:
One underlay substrate is provided;
Form the figure of described public electrode and active layer by a composition technique on described underlay substrate;
Form the figure of gate electrode and grid line by a composition technique on the underlay substrate that is formed with described public electrode and active layer;
Form the figure of the interlayer insulating film that comprises active electrode via hole, drain electrode via hole and public electrode wire via hole by a composition technique on the underlay substrate that is formed with described gate electrode and grid line; Described source electrode via hole, drain electrode via hole, public electrode wire via hole also run through gate insulation layer;
Be formed with on the underlay substrate of described interlayer insulating film by a composition technique figure that forms data wire, source electrode, drain electrode and public electrode wire, described source electrode is connected with described active layer with the drain electrode via hole by described source electrode via hole respectively with drain electrode, and described public electrode wire is connected with described public electrode by described public electrode wire via hole;
Form the figure of the passivation layer that includes passivation layer via hole by a composition technique on the underlay substrate that is formed with described data wire, source electrode, drain electrode and public electrode wire;
Be formed with by a composition technique figure that forms pixel electrode on the underlay substrate of described passivation layer, described pixel electrode is connected with described drain electrode by described passivation layer via hole.
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| CN104835782A (en) * | 2015-05-20 | 2015-08-12 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method of array substrate and display device |
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| CN107507868A (en) * | 2017-08-30 | 2017-12-22 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device |
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