CN203232230U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203232230U CN203232230U CN 201320155800 CN201320155800U CN203232230U CN 203232230 U CN203232230 U CN 203232230U CN 201320155800 CN201320155800 CN 201320155800 CN 201320155800 U CN201320155800 U CN 201320155800U CN 203232230 U CN203232230 U CN 203232230U
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Abstract
The utility model provides an array substrate and a display device. The array substrate comprises a substrate; a plurality of transversely and longitudinally staggered gate lines and data lines and a plurality of uniformly arranged pixel units are arranged on the substrate; every pixel unit comprises a thin film transistor, a pixel electrode and a common electrode; the pixel electrodes and the public electrodes are used for forming into electric fields; at least one of the public electrode and the pixel electrode of every pixel unit comprises a bent slip electrode; one gate line is arranged at a bending position of the slip electrode; source electrodes of the thin film transistors of the pixel units which are arranged on bilateral sides of the data lines are connected to a same data line; gate electrodes are respectively connected with different gate lines. The display device comprises the array substrate. The array substrate has the advantages of compensating the color cast and avoiding light leak.
Description
Technical field
The utility model relates to the display technique field, is specifically related to a kind of array base palte and display device.
Background technology
Along with the development of display fabrication techniques, LCD Technology development has replaced traditional crt display unit gradually and has become the main flow of following flat-panel monitor rapidly.In the LCD Technology field, TFT-LCD(Thin Film Transistor Liquid Crystal Display, Thin Film Transistor-LCD) with its large scale, highly integrated, powerful, technology flexibly, advantage such as low cost and be widely used in fields such as televisor, computer, mobile phone.
Wherein, ADS(ADvanced Super Dimension Switch, ADSDS, a senior super dimension switch technology, abbreviation ADS) type TFT-LCD is widely used in field of liquid crystal owing to have high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, no water of compaction ripple advantages such as (push Mura).The electric field that the electric field that ADS type TFT-LCD produces by slit-shaped electrode edge in the same plane and slit-shaped electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between the slit-shaped electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal work efficiency and increased light transmission efficiency, and then improved the picture quality of TFT-LCD product.
Thereby in order to improve the transmitance that aperture opening ratio improves display device, a kind of HADS(High aperture ADS has appearred, a high aperture-senior super dimension switch technology) type TFT-LCD.Further, in order to shorten the pixel duration of charging to realize low cost, high-quality picture shows, the display panel of existing HADS type TFT-LCD adopts double grid type of drive (Dual Gate) usually, array base palte wherein comprises underlay substrate, be formed on the grid line on the underlay substrate, data line and evenly distributed a plurality of pixel cells, each pixel cell includes thin film transistor (TFT) (TFT), with the pixel electrode that is used to form electric field (Pixel electrode) and public electrode (Com electrode), described pixel electrode and public electrode are used for driving the liquid crystal deflecting element of this pixel cell correspondence; The source electrode that is arranged in the thin film transistor (TFT) of a data line both sides adjacent unit pixel all is connected to this data line (Data line), grid is connected to different grid line (Gate line) respectively, makes to be provided with two grid lines between per two row adjacent unit pixel.
The pixel cell of existing HADS type TFT-LCD is generally one-domain structure (1-Domain), wherein, the direction unanimity of the multi-dimensional electric field that produces between the pixel electrode in each pixel cell and the public electrode is so the yawing moment of the liquid crystal molecule of each pixel cell correspondence is also consistent.But the refractive index difference of liquid crystal molecule under different visual angles, its optical path difference are also different, cause it to see through the optical wavelength range difference, thereby cause when different visual angles, and the colourity of liquid crystal molecule is variant, also namely produces color offset phenomenon.For example, when being parallel to the optical axis direction of liquid crystal molecule, it is less than normal to see through optical wavelength, produces blue partially phenomenon (Bluish), and perpendicular to the optical axis direction of liquid crystal molecule the time, it is bigger than normal to see through optical wavelength, produces yellow partially phenomenon (Yellowish).That is to say that owing to adopt one-domain structure, the yawing moment of the liquid crystal molecule of each pixel cell correspondence is all consistent, causes the whole colour cast of liquid crystal panel comparatively serious.
The utility model content
Technical problem to be solved in the utility model is at existing above-mentioned defective in the prior art, provides a kind of and can either compensate colour cast, can avoid array base palte and the display device of light leak again.
Solve the technical scheme that the utility model technical matters adopts:
Described array base palte comprises underlay substrate, be formed with horizontal vertical staggered many grid lines and data line on the described underlay substrate, and evenly distributed a plurality of pixel cells, each pixel cell includes thin film transistor (TFT), with the pixel electrode that is used to form electric field and public electrode, wherein, the described public electrode of each pixel cell and pixel electrode have a gap electrode that comprises bending at least, and be provided with a grid line in the bending place of described gap electrode, the source electrode that is arranged in the thin film transistor (TFT) of the adjacent described pixel cell in data line both sides all is connected to same data line, and grid is connected to different grid lines respectively.
Preferably, the bending place of the described gap electrode in each pixel cell all is positioned at the middle part of described pixel cell.
Preferably, the slit of the described gap electrode in the same pixel cell all be arranged in parallel.
Preferably, adjacent two positions of pixel cell on underlay substrate all are in staggered distribution on the grid line direction, so that described grid line is straight line, and the distance between adjacent two grid lines equals the length of described pixel cell on the direction vertical with grid line half.
Preferably, the slit overbending direction of the gap electrode in adjacent two pixel cells is opposite on the described grid line direction; Identical with the slit overbending direction of gap electrode in adjacent two pixel cells on the vertical direction of grid line.
Preferably, described array base palte also comprises the public electrode wire that is formed on the underlay substrate, and the public electrode in each pixel cell all links to each other with public electrode wire;
Described public electrode wire and data line are alternately arranged on underlay substrate and are parallel to each other;
Pixel electrode in each pixel cell and public electrode are all between a data line and a public electrode wire adjacent with this data line.
Preferably, the data line that links to each other with the source electrode of thin film transistor (TFT) in each pixel cell, and the public electrode wire that links to each other with public electrode in each pixel cell, all with this pixel cell in the slit of gap electrode of corresponding part parallel.
Preferably, the drain electrode of thin film transistor (TFT) all is connected with pixel electrode in this pixel cell in each pixel cell;
Described array base palte also comprises passivation layer, and described passivation layer is arranged between public electrode and the pixel electrode.
Preferably, the public electrode in each pixel cell is the gap electrode that comprises bending, and pixel electrode is plate electrode;
Perhaps, the pixel electrode in each pixel cell is the gap electrode that comprises bending, and public electrode is plate electrode;
Perhaps, the public electrode in each pixel cell and pixel electrode are the gap electrode that comprises bending.
The utility model also provides a kind of display device that comprises above-mentioned array base palte simultaneously.
Beneficial effect:
Public electrode on the array base palte described in the utility model in each pixel cell and pixel electrode have a gap electrode that comprises bending at least, make the direction of an electric field that forms between public electrode in each pixel cell and the pixel electrode comprise two kinds of directions, thereby make the yawing moment of liquid crystal molecule of each pixel cell correspondence also be divided into two kinds, therefore each pixel cell all can be divided into two zones that the visual angle is different, has compensated effectively because of liquid crystal molecule only to have the colour cast that single yawing moment causes;
The bending place of the gap electrode in each pixel cell is provided with a grid line, has avoided the caused light leakage phenomena in dark space that forms in the bending place of gap electrode effectively.
Description of drawings
Fig. 1 is the planar structure synoptic diagram of array base palte behind the completing steps s101 among the utility model embodiment 2;
Fig. 2 is the planar structure synoptic diagram of array base palte behind the completing steps s102 among the utility model embodiment 2;
Fig. 3 is the planar structure synoptic diagram of array base palte behind the completing steps s103 among the utility model embodiment 2;
Fig. 4 is the planar structure synoptic diagram of array base palte behind the completing steps s104 among the utility model embodiment 2;
Fig. 5 is the planar structure synoptic diagram of array base palte behind the completing steps s105 among the utility model embodiment 2.
Wherein: the 1-grid; The 2-grid line; The 3-semiconductor layer; The 4-source electrode; The 5-drain electrode; The 6-data line; The 7-public electrode wire; The 8-pixel electrode; The 9-public electrode.
Embodiment
For making those skilled in the art understand the technical solution of the utility model better, below in conjunction with drawings and Examples array base palte described in the utility model and display device are described in further detail.
Embodiment 1:
Present embodiment provides a kind of array base palte, comprise underlay substrate, be formed on horizontal vertical staggered many grid lines and data line and evenly distributed a plurality of pixel cells on the described underlay substrate, each pixel cell includes thin film transistor (TFT) and is used to form pixel electrode and the public electrode of electric field.
The described public electrode of each pixel cell and pixel electrode have a gap electrode that comprises bending at least, make the direction of an electric field that forms between public electrode in each pixel cell and the pixel electrode comprise two kinds of directions, thereby make the yawing moment of liquid crystal molecule of each pixel cell correspondence also be divided into two kinds, and the pixel cell that causes having the liquid crystal molecule correspondence of two kinds of yawing moments is divided into two zones that the visual angle is different, compensated the caused colour cast of liquid crystal molecule that only has single yawing moment effectively;
The bending place of the gap electrode in each pixel cell is provided with a grid line, with the caused light leakage phenomena of avoiding forming in the bending place of described gap electrode in dark space;
The source electrode that is arranged in the thin film transistor (TFT) of the adjacent described pixel cell in data line both sides all is connected to same data line, grid is connected to different grid lines respectively, and (this different grid line can be adjacent grid line, also can be non-conterminous grid line), namely described array base palte adopts the double grid type of drive.
Preferably, the bending place of the described gap electrode in each pixel cell all is positioned at the middle part of described pixel cell; The slit of the described gap electrode in the same pixel cell all be arranged in parallel.Make the Electric Field Distribution scope identical (or almost identical) of two kinds of directions forming between public electrode and the pixel electrode in each pixel cell, thereby compensate colour cast better.
Preferably, adjacent two positions of pixel cell on underlay substrate all are in staggered distribution on the grid line direction, so that described grid line is straight line, and the distance between adjacent two grid lines equals the length of described pixel cell on the direction vertical with grid line half, and namely adjacent two grid lines are equidistant arbitrarily.In the array base palte of existing employing double grid type of drive, grid line all is arranged between the adjacent two row pixel cells, and in the present embodiment, every grid line all is arranged alternately between the middle part and adjacent two row pixel cells of pixel cell, so the arrangement mode of grid line has compared with prior art increased aperture opening ratio in the present embodiment.
Preferably, the slit overbending direction of the gap electrode in adjacent two pixel cells is opposite on the described grid line direction; Identical with the slit overbending direction of gap electrode in adjacent two pixel cells on the vertical direction of grid line, in order to can arrange more pixel cell on the underlay substrate.
Preferably, described array base palte also comprises the public electrode wire that is formed on the underlay substrate, and the public electrode in each pixel cell all links to each other with public electrode wire; Described public electrode wire and data line are alternately arranged on underlay substrate and are parallel to each other; Pixel electrode in each pixel cell and public electrode are all between a data line and a public electrode wire adjacent with this data line.The data line that links to each other with the source electrode of thin film transistor (TFT) in each pixel cell, and the public electrode wire that links to each other with public electrode in each pixel cell, all with this pixel cell in the slit of gap electrode of corresponding part parallel.Adopt pixel cell aperture opening ratio when underlay substrate is arranged of this structure higher, also be conducive to pixel cell arranging on underlay substrate.
Preferably, the drain electrode of thin film transistor (TFT) all is connected with pixel electrode in this pixel cell in each pixel cell; Described array base palte also comprises passivation layer, and described passivation layer is arranged between public electrode and the pixel electrode.
Preferably, the public electrode in each pixel cell is the gap electrode that comprises bending, and pixel electrode is plate electrode;
Perhaps, the pixel electrode in each pixel cell is the gap electrode that comprises bending, and public electrode is plate electrode;
Perhaps, the public electrode in each pixel cell and pixel electrode are the gap electrode that comprises bending.
Present embodiment also provides a kind of display device that comprises above-mentioned array base palte simultaneously.Described display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Embodiment 2:
Present embodiment provides a kind of array base palte, comprises underlay substrate, is formed on horizontal vertical staggered many grid lines and data line, public electrode wire, gate insulator, passivation layer and evenly distributed a plurality of pixel cells on the underlay substrate.
Each pixel cell includes thin film transistor (TFT) and is used to form pixel electrode and the public electrode of electric field; Wherein, public electrode in each pixel cell is the gap electrode that comprises bending, pixel electrode is plate electrode, bending place at described public electrode (being gap electrode) is provided with a grid line, with the dark space light leak of avoiding described bending place to form, and the bending place of described public electrode is positioned at the middle part of described pixel cell, also is the middle part that described grid line is positioned at described pixel cell; The slit of the public electrode in the same pixel cell all be arranged in parallel; Each thin film transistor (TFT) includes grid, semiconductor layer (being also referred to as active layer), source electrode and drain electrode.
The source electrode that is arranged in the thin film transistor (TFT) of same data line both sides and adjacent unit pixel all is connected to this same data line, grid is connected to two different grid lines respectively, and (grid of two adjacent pixel unit as shown in Figure 5 is to be connected on two adjacent grid lines, this is a kind of situation wherein just), drain electrode all with the connection of corresponding pixel electrode, the i.e. described array base palte employing of present embodiment double grid type of drive.Adjacent two positions of pixel cell on underlay substrate all are in staggered distribution on the grid line direction, so that described grid line is straight line, and the distance between adjacent two grid lines equals the length of described pixel cell on the direction vertical with grid line half.The slit overbending direction of the public electrode on the grid line direction in adjacent two pixel cells is opposite; Identical with the slit overbending direction of public electrode in adjacent two pixel cells on the vertical direction of grid line.
Described public electrode wire links to each other with public electrode in each pixel cell, is used to public electrode that voltage is provided; Described public electrode wire and data line are alternately arranged on underlay substrate and are parallel to each other; Pixel electrode in each pixel cell and public electrode are all between a data line and a public electrode wire adjacent with this data line.The data line that links to each other with the source electrode of thin film transistor (TFT) in each pixel cell, and the public electrode wire that links to each other with public electrode in each pixel cell, all with this pixel cell in the slit of gap electrode of corresponding part parallel.
Described gate insulator is arranged between the grid and semiconductor layer of thin film transistor (TFT) in each pixel cell, and described passivation layer is arranged between public electrode and the pixel electrode, all plays the effect of insulation.
Present embodiment also provides a kind of display device that comprises above-mentioned array base palte simultaneously.Described display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Describe the method for making of the described array base palte of present embodiment in detail below in conjunction with accompanying drawing 1-Fig. 5.Though be formed with a plurality of evenly distributed pixel cells on the described array base palte of present embodiment, for ease of describing and understanding, a kind of situation of adjacent two pixel cell structures only be shown among accompanying drawing 1-Fig. 5.And, for convenient each layer pattern of observing, the pixel electrode 8 in the accompanying drawing and public electrode 9 have all been carried out translucentization processing.
This method comprises the steps:
S100., one underlay substrate is provided.
Described underlay substrate should be through the dustless inclusion-free ion in clean back.Described underlay substrate can adopt transparency carriers such as glass substrate, quartz base plate, plastic base.
S101. as shown in Figure 1, by the figure of composition technology at underlay substrate (not shown) formation grid 1 and grid line 2, described grid 1 is continuous with corresponding grid line 2.
S102. as shown in Figure 2, on the underlay substrate of completing steps s101, form the figure of gate insulator (not shown) and semiconductor layer 3 successively by composition technology, described gate insulator covers on the underlay substrate of completing steps s101 fully, therefore also cover on grid 1 and the grid line 2, described semiconductor layer 3 be arranged on corresponding grid 1 directly over.
S103. as shown in Figure 3, form the figure of source electrode 4, drain electrode 5, data line 6 and public electrode wire 7 at the underlay substrate of completing steps s102 by composition technology, described source electrode 4 links to each other with semiconductor layer 3 respectively with drain electrode 5, and described source electrode 4 and drain and be formed with raceway groove between 5, described source electrode 4 links to each other with corresponding data line 6.
Wherein, step s102 and step s103 can utilize the normal masks plate technique and adopt twice composition technology to finish, and also can utilize duotone mask plate (as half-tone mask plate (Half Tone Mask) or gray mask plate (Gray Tone Mask)) technology to finish in a composition technological process.
S104. as shown in Figure 4, by the figure of composition technology at the tabular pixel electrode 8 of underlay substrate formation of completing steps s103, described pixel electrode 8 is continuous with corresponding drain electrode 5.
S105. as shown in Figure 5, on the underlay substrate of completing steps s104, form the passivation layer (not shown) successively and public electrode 9(is gap electrode by composition technology) figure, described passivation layer covers on the underlay substrate of completing steps s104 fully, and is formed with on the described passivation layer for connecting the via hole of public electrode 9 with public electrode wire 7.
Other structures in the present embodiment and effect are all identical with embodiment 1, repeat no more here.The above composition technology generally includes technologies such as photoresist coating, exposure, development, etching, photoresist lift off.
Be understandable that above embodiment only is the illustrative embodiments that adopts for principle of the present utility model is described, yet the utility model is not limited thereto.For those skilled in the art, under the situation that does not break away from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement also are considered as protection domain of the present utility model.
Claims (10)
1. array base palte, comprise underlay substrate, be formed with horizontal vertical staggered many grid lines and data line on the described underlay substrate, and evenly distributed a plurality of pixel cells, each pixel cell includes thin film transistor (TFT), with the pixel electrode that is used to form electric field and public electrode, it is characterized in that, the described public electrode of each pixel cell and pixel electrode have a gap electrode that comprises bending at least, and be provided with a grid line in the bending place of described gap electrode, the source electrode that is arranged in the thin film transistor (TFT) of the adjacent described pixel cell in data line both sides all is connected to same data line, and grid is connected to different grid lines respectively.
2. array base palte according to claim 1 is characterized in that,
The bending place of the described gap electrode in each pixel cell all is positioned at the middle part of described pixel cell.
3. array base palte according to claim 2 is characterized in that, the slit of the described gap electrode in the same pixel cell all be arranged in parallel.
4. array base palte according to claim 2 is characterized in that,
Adjacent two positions of pixel cell on underlay substrate all are in staggered distribution on the grid line direction, so that described grid line is straight line, and the distance between adjacent two grid lines equals the length of described pixel cell on the direction vertical with grid line half.
5. array base palte according to claim 4 is characterized in that,
The slit overbending direction of the gap electrode on the described grid line direction in adjacent two pixel cells is opposite; Identical with the slit overbending direction of gap electrode in adjacent two pixel cells on the vertical direction of grid line.
6. array base palte according to claim 1 is characterized in that,
Described array base palte also comprises the public electrode wire that is formed on the underlay substrate, and the public electrode in each pixel cell all links to each other with public electrode wire;
Described public electrode wire and data line are alternately arranged on underlay substrate and are parallel to each other;
Pixel electrode in each pixel cell and public electrode are all between a data line and a public electrode wire adjacent with this data line.
7. array base palte according to claim 6 is characterized in that,
The data line that links to each other with the source electrode of thin film transistor (TFT) in each pixel cell, and the public electrode wire that links to each other with public electrode in each pixel cell, all with this pixel cell in the slit of gap electrode of corresponding part parallel.
8. array base palte according to claim 1 is characterized in that,
The drain electrode of thin film transistor (TFT) all is connected with pixel electrode in this pixel cell in each pixel cell;
Described array base palte also comprises passivation layer, and described passivation layer is arranged between public electrode and the pixel electrode.
9. according to each described array base palte among the claim 1-8, it is characterized in that,
Public electrode in each pixel cell is the gap electrode that comprises bending, and pixel electrode is plate electrode;
Perhaps, the pixel electrode in each pixel cell is the gap electrode that comprises bending, and public electrode is plate electrode;
Perhaps, the public electrode in each pixel cell and pixel electrode are the gap electrode that comprises bending.
10. a display device comprises each described array base palte as claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320155800 CN203232230U (en) | 2013-03-29 | 2013-03-29 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320155800 CN203232230U (en) | 2013-03-29 | 2013-03-29 | Array substrate and display device |
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| CN203232230U true CN203232230U (en) | 2013-10-09 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235452A (en) * | 2013-03-29 | 2013-08-07 | 合肥京东方光电科技有限公司 | Array substrate and display device |
| CN106681064A (en) * | 2016-11-25 | 2017-05-17 | 厦门天马微电子有限公司 | Array baseplate and display panel |
| WO2018152872A1 (en) * | 2017-02-22 | 2018-08-30 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device |
| CN110850627A (en) * | 2019-11-29 | 2020-02-28 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114563892A (en) * | 2020-11-27 | 2022-05-31 | 福州京东方光电科技有限公司 | Array substrate, display panel and display device |
-
2013
- 2013-03-29 CN CN 201320155800 patent/CN203232230U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235452A (en) * | 2013-03-29 | 2013-08-07 | 合肥京东方光电科技有限公司 | Array substrate and display device |
| WO2014153844A1 (en) * | 2013-03-29 | 2014-10-02 | 合肥京东方光电科技有限公司 | Array substrate and display device |
| CN103235452B (en) * | 2013-03-29 | 2016-06-08 | 合肥京东方光电科技有限公司 | A kind of array base palte and display device |
| CN106681064A (en) * | 2016-11-25 | 2017-05-17 | 厦门天马微电子有限公司 | Array baseplate and display panel |
| CN106681064B (en) * | 2016-11-25 | 2019-08-13 | 厦门天马微电子有限公司 | Array substrate and display panel |
| WO2018152872A1 (en) * | 2017-02-22 | 2018-08-30 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device |
| CN110850627A (en) * | 2019-11-29 | 2020-02-28 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114563892A (en) * | 2020-11-27 | 2022-05-31 | 福州京东方光电科技有限公司 | Array substrate, display panel and display device |
| CN114563892B (en) * | 2020-11-27 | 2023-12-19 | 福州京东方光电科技有限公司 | Array substrate, display panel and display device |
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Granted publication date: 20131009 |