CN202159214U - Array substrate and liquid crystal display - Google Patents
Array substrate and liquid crystal display Download PDFInfo
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- CN202159214U CN202159214U CN2011200146039U CN201120014603U CN202159214U CN 202159214 U CN202159214 U CN 202159214U CN 2011200146039 U CN2011200146039 U CN 2011200146039U CN 201120014603 U CN201120014603 U CN 201120014603U CN 202159214 U CN202159214 U CN 202159214U
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Abstract
The utility model discloses an array substrate and a liquid crystal display. The array substrate consists of an substratum substrate; data lines and grid lines which are horizontally and longitudinally crossed are arranged on the substratum substrate; the data lines and the grid lines form sub-pixel units which are arranged in an array manner in an enclosing way; each sub-pixel unit consists of a TFT (thin film transistor) switch, a pixel electrode and a public electrode, as well as public electrode lines which are arranged at the same layer of the data lines at intervals, the public electrode lines are respectively connected with the public electrodes in all sub-pixel units. For the array substrate and the liquid crystal display, the public electrode lines and the data lines are arranged at the same layer and at intervals, so that the number of the public electrode lines is consistent with that of the data lines, the number of the public electrode lines is reduced when the product cost is reduced by increasing the grid lines and the data lines, and the aperture opening ratio of pixel units can not be reduced excessively, so that the reduction of transmissivity and the increase of driving power consumption can be avoided.
Description
Technical field
The utility model relates to lcd technology, relates in particular to a kind of array base palte and LCD.
Background technology
LCD is a flat-panel monitor commonly used at present, and wherein Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display is called for short TFT-LCD) is the main product in the LCD.Be to improve competitiveness of product, the method that reduces cost of products through employing new technology is the most also to be one of effective method.Because the cost of data-signal drive IC is higher than the cost of scanning gate signal drive IC,, thereby reduce the quantity of data wire size drive IC so a kind of mode that prior art reduces cost is to be the quantity that cost reduces data line to increase grid line as far as possible.
Be illustrated in figure 1 as the fragmentary top TV structure synoptic diagram of a kind of array base palte in the prior art, show the layout of the trichromatic sub-pixel of RGB on the array base palte (RGB) and the approximate location of data line 5 and grid line 2.In this array base palte; RGB three sub-pixel elements that constitute a pixel cell are vertically arranged along data line 5 directions; Then each pixel cell needs three grid lines 2 and a data line 5 to control, and this mode can be through increasing the quantity that grid line 2 quantity reduce data line 5.Than the transversely arranged mode of RGB sub-pixel unit, grid line 2 increases to original three times.
In recent years, fringing field change-over switch technology (Fringe Field Switching is called for short FFS) and senior ultra dimension field switch technology (Advanced-Super Dimensional Switching; Be called for short: AD-SDS) wide visual angle technology becomes the research direction; The longitudinal electric field that parallel electric field that AD-SDS is produced through same plane interior pixel electrode edge and pixel electrode layer and public electrode interlayer produce forms the hyperspace compound field; Make between liquid crystal cell interior pixel electrode, directly over the electrode and all aligned liquid-crystal molecules of liquid crystal cell top can both produce the rotation conversion, thereby to have improved planar orientation be the liquid crystal work efficiency and increased light transmission efficiency.Senior ultra dimension field switch technology can improve the TFT-LCD picture quality, has advantages such as high permeability, wide visual angle, high aperture, low aberration, low-response time, no water of compaction ripple (push Mura) ripple.More than the array base palte of two kinds of technology comprise underlay substrate; Be formed with horizontal vertical data line crossing and grid line on the underlay substrate; Data line and grid line enclose and form the sub-pixel unit that matrix form is arranged; Each sub-pixel unit comprises TFT switch, first transparency electrode and second transparency electrode, and the TFT switch comprises gate electrode, active layer, source electrode and drain electrode.The example hierarchy relation of various patterns is to begin from underlay substrate, comprises first transparency electrode (1st ITO) successively; Grid line and gate electrode (Gate); Active layer, source electrode, drain electrode and data line (Multi & SD); Passivation layer (PVX); Second transparency electrode (2 nd ITO) promptly can be designated as the structure of 1st ITO/Gate/Multi & SD/PVX/2 nd ITO usually.Wherein, first transparency electrode is generally public electrode, and second transparency electrode is generally pixel electrode; Because the resistance of public electrode 10 materials is bigger; For guarantee voltage on the public electrode 10 evenly, can on array base palte, adopt good conductive material prepare public electrode wire 12 usually, as shown in Figure 1; Adopt the material of grid line 2 to form public electrode wire 12 with layer; Respectively with each sub-pixel unit in public electrode 10 link to each other, public electrode wire 12 is connected to the circuit of array substrate peripheral, to supply with common electric voltage.
But there is certain defective in said structure, because the quantity of grid line increases, so the also corresponding increase of public electrode wire quantity that forms with layer and adjacent spaces with grid line.In three times of grid lines (Triple Gate) structure shown in Figure 1; For a pixel cell; It needs three public electrode wires, causes the aperture opening ratio of pixel cell to descend, and transmitance reduces; Then just need to improve driving power consumption for avoiding brightness to reduce, this obviously is unfavorable for the reduction of overall product cost.
The utility model content
The utility model provides a kind of array base palte and LCD, to improve the aperture opening ratio of pixel cell in the array base palte.
The utility model provides a kind of array base palte, comprises underlay substrate; Be formed with horizontal vertical data line crossing and grid line on the underlay substrate; Data line and grid line enclose and form the sub-pixel unit that matrix form is arranged; Each sub-pixel unit comprises TFT switch, pixel electrode and public electrode, wherein, also comprises:
Public electrode wire, with said data line with layer and form at interval, said public electrode wire respectively with each sub-pixel unit in public electrode link to each other.
The quantity of said public electrode wire is corresponding with the quantity of data line, and parallel with data line.
Aforesaid array base palte, preferably:
Said pixel electrode is formed directly on the said underlay substrate, and covers under the gate insulation layer;
Said public electrode is formed on the passivation layer that covers said data line and public electrode wire;
Said public electrode wire links to each other with said public electrode through first via hole in the said passivation layer.
Aforesaid array base palte preferably also comprises: adopt the material of public electrode process and with integrated first bonding line of public electrode, said first bonding line connects adjacent public electrode and public electrode wire through first via hole.
Aforesaid array base palte, preferably:
Said public electrode is formed directly on the said underlay substrate, and covers under the gate insulation layer;
Said pixel electrode is formed on the passivation layer that covers said data line and public electrode wire;
Said public electrode wire links to each other with said public electrode through second via hole in the said gate insulation layer.
Aforesaid array base palte preferably also comprises: adopt the material of pixel electrode to process second bonding line, said second bonding line is connected adjacent public electrode and public electrode wire through passivation layer with second via hole in the gate insulation layer.
Aforesaid array base palte, preferably: every said public electrode wire respectively with adjacent two row sub-pixel unit in public electrode be connected.
Aforesaid array base palte, preferably: each sub-pixel elements that constitutes same pixel cell is vertically arranged along the data line direction.
The utility model also provides a kind of LCD, comprises liquid crystal panel, and wherein: said liquid crystal panel comprises the array base palte that color membrane substrates and the utility model provided to the box setting.
Array base palte that the utility model provides and LCD; Through public electrode wire and data line are formed with layer and interval; Make that the quantity of public electrode wire is corresponding with the quantity of data line, when the mode that reduces data line through the increase grid line reduces cost of products, the also corresponding minimizing of the quantity of public electrode wire; Can too much not reduce the aperture opening ratio of pixel cell, thereby can avoid transmitance to descend and the driving power consumption increase.
Description of drawings
Shown in Figure 1 is the fragmentary top TV structure synoptic diagram of a kind of array base palte in the prior art;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 2 provides for the utility model embodiment one;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 3 provides for the utility model embodiment two;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 4 provides for the utility model embodiment three;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 5 provides for the utility model embodiment.
Reference numeral:
The 1-underlay substrate; The 2-grid line; 3-first via hole;
4-first bonding line; The 5-data line; 6-second via hole;
7-second bonding line; The 10-public electrode; The 11-pixel electrode;
The 12-public electrode wire.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model embodiment clearer; To combine the accompanying drawing among the utility model embodiment below; Technical scheme among the utility model embodiment is carried out clear, intactly description; Obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
The utility model embodiment provides a kind of array base palte, comprises underlay substrate; Be formed with horizontal vertical data line crossing and grid line on the underlay substrate; Data line and grid line enclose and form the sub-pixel unit that matrix form is arranged; Each sub-pixel unit comprises TFT switch, pixel electrode and public electrode, and this array base palte also comprises public electrode wire, with data line with layer and form at interval, public electrode wire respectively with each sub-pixel unit in public electrode link to each other.
The technical scheme of the utility model is through forming public electrode wire and data line with layer and interval; Make that the quantity of public electrode wire is corresponding with the quantity of data line; When the mode that reduces data line through the increase grid line reduces cost of products; The yet corresponding minimizing of the quantity of public electrode wire can too much not reduce the aperture opening ratio of pixel cell, thereby can avoid transmitance to descend and the driving power consumption increase.The embodiment of the invention illustrates with FFS type or AD-SDS type technology.
Embodiment one
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 2 provides for the utility model embodiment one.In the present embodiment, array base palte comprises underlay substrate 1; Be formed with horizontal vertical data line crossing 5 and grid line 2 on the underlay substrate 1; Data line 5 encloses with grid line 2 and forms the sub-pixel unit that matrix form is arranged; Each sub-pixel unit comprises TFT switch, pixel electrode 11 and public electrode 10.The TFT switch comprises gate electrode, active layer, source electrode and drain electrode.Public electrode wire 12 and data line 5 are with layer and form at interval, public electrode wire 12 respectively with each sub-pixel unit in public electrode 10 link to each other.In the present embodiment, public electrode 10 is the pattern that bulk has slit, and the public electrode wire 12 that is adjacent links to each other.
Particularly, pixel electrode 11 is formed directly on the underlay substrate 1, and covers under the gate insulation layer.Grid line 2 can be formed on the underlay substrate 1 before or after pixel electrode 11 forms with gate electrode, kept also covering under the gate insulation layer at interval with pixel electrode 11.Data line 5, active layer, source electrode, drain electrode and public electrode wire 12 are formed on the gate insulation layer, cover passivation layer on it.Public electrode 10 is formed on the passivation layer of cover data line 5 and public electrode wire 12; Public electrode wire 12 links to each other with public electrode 10 through first via hole 3 in the passivation layer; And it is that the material that specifically can adopt public electrode 10 is processed and connect adjacent public electrode 10 and public electrode wire 12 through first via hole 3 with one-body molded first bonding line of public electrode 10 4, the first bonding lines 4.Pixel electrode 11 preferably adopts the via hole of material in passivation layer and gate insulation layer of public electrode 10 to come cross-over connection pixel electrode 11 and source electrode with the connected mode of source electrode.But the connected mode that those skilled in the art should understand that both is not limited to this, does not specifically illustrate the details that is connected of pixel electrode 11 and source electrode in the accompanying drawing of each embodiment of the utility model.
The technical scheme of present embodiment is a kind of preferred structure of array base palte, and public electrode wire and data line form with layer, can reduce the quantity of public electrode wire, improves the aperture opening ratio of pixel cell.And; Present embodiment is exchanged the position of public electrode and pixel electrode for cooperating the position of public electrode wire, and public electrode is arranged on the passivation layer; Be positioned at the top of public electrode wire, be easy to adopt the material filled vias of public electrode to connect public electrode wire.
In the practical application, public electrode is not limited to blocky, and is preferably the monoblock electrode that has slit that is laid on the whole array base palte; But not corresponding to the blocky of each pixel cell; Adopt the advantage of this technical scheme to be: when public electrode covers the whole base plate surface, when especially covering the public electrode wire top, to be equipotential electric field at the gap location of pixel electrode and data line; Promptly can drives liquid crystal molecules do not reverse and light leakage phenomenon occurs; So need not to block with black matrix, thereby can reduce the black matrix width on the color membrane substrates, thereby the transmitance and the aperture opening ratio of raising pixel cell at gap location.
Embodiment two
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 3 provides for the utility model embodiment two.The similar of present embodiment and embodiment one, difference is: public electrode 10 is formed directly on the underlay substrate 1, and covers under the gate insulation layer; Pixel electrode 11 is formed on the passivation layer of cover data line 5 and public electrode wire 12, and pixel electrode 11 is the block pattern that has slit, and pixel electrode 11 can link to each other with the source electrode through the via hole in the passivation layer; Public electrode wire 12 links to each other with public electrode 10 through second via hole 6 in the gate insulation layer.Preferably, can adopt material preparation second bonding line 7 of pixel electrode 11, in passivation layer and gate insulation layer, form second via hole, 6, the second bonding lines 7 and connect adjacent public electrode 10 and public electrode wire 12 through second via hole 6.
Perhaps, also can adopt the one-body molded bonding line of material of public electrode wire, connect the public electrode of below through the via hole in the gate insulation layer.
The technical scheme of present embodiment is the another kind of preferred structure of array base palte, and public electrode wire and data line form with layer, can reduce the quantity of public electrode wire, improves the aperture opening ratio of pixel cell.
Embodiment three
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 4 provides for the utility model embodiment three.The difference of present embodiment and the foregoing description is, every public electrode wire respectively with adjacent two row sub-pixel unit in public electrode be connected.
To be similar to the structure of embodiment one, public electrode 10 is formed on the passivation layer and describes for example.Every public electrode wire 12 links to each other with two adjacent row public electrodes 10 through first via hole 3 in the passivation layer; And it is that the material that specifically can adopt public electrode 10 is processed and connect two adjacent row public electrodes 10 and public electrode wires 12 through first via hole 3 with one-body molded first bonding line of public electrode 10 4, the first bonding lines 4.The public electrode 10 of two adjacent row blockies, its pattern separately links to each other through first bonding line 4, and links to each other with public electrode wire 12 through first via hole 3, and this first bonding line 4 strides across the connection that data line 5 is realized two public electrodes 10.This technical scheme is particularly useful for the public electrode 10 of blocky, can further reduce the quantity of public electrode wire 10.
The array base palte of each embodiment of the utility model can be laid grid line and data line in different ways, the restriction of the corresponding increase of public electrode wire when having avoided the increase grid line.Each sub-pixel elements that preferably constitutes same pixel cell is vertically arranged along the data line direction, and is as shown in Figure 5, perhaps also can adopt other to increase grid lines and reduces the layout type of data line.
The utility model embodiment also provides a kind of LCD, comprises liquid crystal panel, and this liquid crystal panel comprises the array base palte that the color membrane substrates of box setting and the utility model any embodiment are provided.Public electrode wire and data line form with layer, can reduce the quantity of public electrode wire, improve the aperture opening ratio of pixel cell, thereby have good transmitance, avoid increasing driving power consumption and improve brightness.
What should explain at last is: above embodiment is only in order to the technical scheme of explanation the utility model, but not to its restriction; Although the utility model has been carried out detailed explanation with reference to previous embodiment; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of each embodiment technical scheme of essence disengaging the utility model of relevant art scheme.
Claims (9)
1. an array base palte comprises underlay substrate; Be formed with horizontal vertical data line crossing and grid line on the underlay substrate; Data line and grid line enclose and form the sub-pixel unit that matrix form is arranged; Each sub-pixel unit comprises TFT switch, pixel electrode and public electrode, it is characterized in that, also comprises:
Public electrode wire, with said data line with layer and form at interval, said public electrode wire respectively with each sub-pixel unit in public electrode link to each other.
2. array base palte according to claim 1 is characterized in that: the quantity of said public electrode wire is corresponding with the quantity of data line, and parallel with data line.
3. array base palte according to claim 1 is characterized in that:
Said pixel electrode is formed directly on the said underlay substrate, and covers under the gate insulation layer;
Said public electrode is formed on the passivation layer that covers said data line and public electrode wire;
Said public electrode wire links to each other with said public electrode through first via hole in the said passivation layer.
4. array base palte according to claim 3 is characterized in that, also comprises:
Adopt the material of public electrode process and with integrated first bonding line of public electrode, said first bonding line connects adjacent public electrode and public electrode wire through first via hole.
5. array base palte according to claim 1 is characterized in that:
Said public electrode is formed directly on the said underlay substrate, and covers under the gate insulation layer;
Said pixel electrode is formed on the passivation layer that covers said data line and public electrode wire;
Said public electrode wire links to each other with said public electrode through second via hole in the said gate insulation layer.
6. array base palte according to claim 5 is characterized in that, also comprises:
Adopt the material of pixel electrode to process second bonding line, said second bonding line is connected adjacent public electrode and public electrode wire through passivation layer with second via hole in the gate insulation layer.
7. according to the arbitrary described array base palte of claim 1～6, it is characterized in that: every said public electrode wire respectively with adjacent two row sub-pixel unit in public electrode be connected.
8. according to the arbitrary described array base palte of claim 1～6, it is characterized in that: each sub-pixel elements that constitutes same pixel cell is vertically arranged along the data line direction.
9. a LCD comprises liquid crystal panel, it is characterized in that: said liquid crystal panel comprises color membrane substrates and the arbitrary described array base palte of claim 1～8 that box is provided with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200146039U CN202159214U (en) | 2010-10-14 | 2011-01-18 | Array substrate and liquid crystal display |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020568053.0 | 2010-10-14 | ||
| CN201020568053 | 2010-10-14 | ||
| CN2011200146039U CN202159214U (en) | 2010-10-14 | 2011-01-18 | Array substrate and liquid crystal display |
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| Publication Number | Publication Date |
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| CN202159214U true CN202159214U (en) | 2012-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011200146039U Expired - Lifetime CN202159214U (en) | 2010-10-14 | 2011-01-18 | Array substrate and liquid crystal display |
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| CN (1) | CN202159214U (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102937768A (en) * | 2012-11-13 | 2013-02-20 | 京东方科技集团股份有限公司 | Array substrate and manufacture method and display device thereof |
| CN102981333A (en) * | 2012-11-21 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device thereof |
| CN103018993A (en) * | 2012-12-31 | 2013-04-03 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, liquid crystal display and display device |
| CN104536227A (en) * | 2012-11-16 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method |
| CN105489616A (en) * | 2016-01-15 | 2016-04-13 | 重庆京东方光电科技有限公司 | Display substrate, manufacturing method thereof and display device comprising display substrate |
| WO2016061817A1 (en) * | 2014-10-21 | 2016-04-28 | 深圳市华星光电技术有限公司 | Liquid crystal panel, drive method therefor, and liquid crystal display |
| WO2017133179A1 (en) * | 2016-02-01 | 2017-08-10 | Boe Technology Group Co., Ltd. | Display substrate, fabricating method thereof, and display apparatus |
| WO2018068542A1 (en) * | 2016-10-14 | 2018-04-19 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| CN112540484A (en) * | 2020-11-24 | 2021-03-23 | 惠科股份有限公司 | Display panel and display device |
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2011
- 2011-01-18 CN CN2011200146039U patent/CN202159214U/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102937768A (en) * | 2012-11-13 | 2013-02-20 | 京东方科技集团股份有限公司 | Array substrate and manufacture method and display device thereof |
| CN102937768B (en) * | 2012-11-13 | 2015-02-25 | 京东方科技集团股份有限公司 | Array substrate and manufacture method and display device thereof |
| CN104536227A (en) * | 2012-11-16 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method |
| CN104536227B (en) * | 2012-11-16 | 2018-02-16 | 京东方科技集团股份有限公司 | Array base palte, display device and preparation method |
| CN102981333A (en) * | 2012-11-21 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device thereof |
| CN102981333B (en) * | 2012-11-21 | 2015-04-29 | 京东方科技集团股份有限公司 | Array substrate, and manufacturing method and display device thereof |
| CN103018993A (en) * | 2012-12-31 | 2013-04-03 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, liquid crystal display and display device |
| CN103018993B (en) * | 2012-12-31 | 2015-07-15 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, liquid crystal display and display device |
| WO2016061817A1 (en) * | 2014-10-21 | 2016-04-28 | 深圳市华星光电技术有限公司 | Liquid crystal panel, drive method therefor, and liquid crystal display |
| CN105489616A (en) * | 2016-01-15 | 2016-04-13 | 重庆京东方光电科技有限公司 | Display substrate, manufacturing method thereof and display device comprising display substrate |
| US10199399B2 (en) | 2016-01-15 | 2019-02-05 | Boe Technology Group Co., Ltd. | Display substrate and manufacturing method thereof, and display apparatus |
| CN105489616B (en) * | 2016-01-15 | 2019-04-05 | 重庆京东方光电科技有限公司 | Display base plate and preparation method thereof and display device |
| WO2017133179A1 (en) * | 2016-02-01 | 2017-08-10 | Boe Technology Group Co., Ltd. | Display substrate, fabricating method thereof, and display apparatus |
| US10325934B2 (en) | 2016-02-01 | 2019-06-18 | Boe Technology Group Co., Ltd. | Display substrate, fabricating method thereof, and display apparatus |
| WO2018068542A1 (en) * | 2016-10-14 | 2018-04-19 | 京东方科技集团股份有限公司 | Array substrate and display device |
| US10546879B2 (en) | 2016-10-14 | 2020-01-28 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| US10274801B2 (en) | 2017-03-27 | 2019-04-30 | Au Optronics Corporation | Display panel |
| CN112540484A (en) * | 2020-11-24 | 2021-03-23 | 惠科股份有限公司 | Display panel and display device |
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Granted publication date: 20120307 |