CN102879962A - Array substrate and display device - Google Patents
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- CN102879962A CN102879962A CN2012103711970A CN201210371197A CN102879962A CN 102879962 A CN102879962 A CN 102879962A CN 2012103711970 A CN2012103711970 A CN 2012103711970A CN 201210371197 A CN201210371197 A CN 201210371197A CN 102879962 A CN102879962 A CN 102879962A
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Abstract
The invention provides an array substrate and a display device and belongs to the technical field of display. The array substrate and the display device solve the problems of low aperture ratio and high energy consumption of existing display devices. The array substrate comprises gate lines, data lines, public electrode lines and a pixel unit array, the gate lines and the data lines are in latticed cross arrangement, the public electrode lines are parallel to the gate lines, each pixel unit is connected with one gate line and one data line, each gate line is simultaneously connected with N rows of pixel units, N data lines simultaneously connected with one row of pixel units, N pixel units which are connected with a same gate line and in one row of the pixel units are respectively connected with N different data lines, and each public electrode line is used for supplying power for a public electrode of N rows of pixel units connected with a same gate line. The display device comprises the array substrate. The array substrate can be used for display devices in TN (twisted nematic) mode, VA (vertical alignment) mode, IPS (in-plane switching) mode, ADS (address and display separation) mode and the like.
Description
Technical field
The invention belongs to the display technique field, be specifically related to a kind of array base palte and display device.
Background technology
Display panels mainly is comprised of box array base palte and color membrane substrates.Wherein, as shown in Figure 1, array base palte is provided with cross arrangement and is latticed gate line 2 and data line 3 (because they are arranged in different layers, can conducting when the old friend pitches), each intersection point of gate line 2 and data line 3 limits a pixel cell 1, thereby a plurality of pixel cell is arranged in matrix form; To color liquid crystal display panel, a sub-pixel (claiming again sub-pix) of each pixel cell 1 corresponding display screen, and three sub-pixels of the RGB that is close together consist of a visible pixel on the display screen; To the achromaticity display, pixel cell 1 pixel on also can direct corresponding display screen.
Each pixel cell 1 comprises a thin film transistor (TFT) 11 and a pixel electrode 12 that links to each other with thin film transistor (TFT) 11 drain electrodes, the grid of the thin film transistor (TFT) 11 of one-row pixels unit 1 links to each other with same gate line 2, and the source electrode of the thin film transistor (TFT) 11 of a row pixel cell 1 links to each other with same data lines 3.When certain root gate line 2 conducting, as long as the signal of each data line 3 of control can make these gate line 2 corresponding one-row pixels unit 1 show simultaneously required content, as long as therefore make each in turn conducting of root gate line 2 (claiming again scanning), can demonstrate required content.Wherein, according to the difference of display model etc., gate line 2 width are at 5 ~ 80 μ m usually, and data line 3 width are at 2 ~ 30 μ m.
In addition, be used in addition the public electrode wire 4 of public electrode power supply on the array base palte, it is parallel to gate line 2, (it also is in different layers from data line 3 can be positioned at gate line 2 sidepieces, can conducting when the old friend pitches) yet, also can be positioned at as shown in Figure 1 pixel electrode 12 belows, thereby play simultaneously the effect (this moment, public electrode wire 4 should adopt transparent material to make) of storage capacitor electrode, every public electrode wire 4 is used to the public electrode power supply of one-row pixels unit 1.Wherein, according to the difference of display mode, public electrode can be positioned at (for example for TN pattern, VA pattern) on the color membrane substrates, also can be located on (for example for IPS mould, ADS pattern) on the array base palte with public electrode wire 4 one.
Because the zone at the places such as gate line, data line, public electrode wire can not make liquid crystal molecule that correct deflection occurs, therefore these zones can produce light leak, therefore, black matrix (BM need to be set above these zones, Black Matrix) to cover the light that is seen through by these zones, black matrix can be positioned on the color membrane substrates, also can be positioned at (BM on Array) on the array base palte.Wherein, in order to guarantee shaded effect, the black matrix width of gate line is usually at 50 ~ 120 μ m, and the black matrix width of data line is usually at 20 ~ 80 μ m.
The inventor finds that there are the following problems at least in the prior art: the gate line width on the existing array base palte is large and quantity is many, therefore the shared total area of the black matrix of gate line is inevitable larger, causes thus the aperture opening ratio of display device low, the efficiency of light energy utilization is low, energy consumption is high.
Summary of the invention
Technical matters to be solved by this invention comprises, the problem low for display device aperture opening ratio of the prior art, that energy consumption is high provides a kind of array base palte that improves display device aperture opening ratio, reduction energy consumption, improves refresh rate.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and it comprises: cross arrangement is latticed gate line and data line; The public electrode wire parallel with described gate line; Be arranged as the pixel cell of matrix, wherein each pixel cell connects a gate line and a data lines; Wherein
Every gate line connects the capable pixel cell of N simultaneously, and N is the integer more than or equal to 2;
The N data lines connects a row pixel cell simultaneously, and N the pixel cell that is connected with same gate line in the row pixel cell links to each other with N root different pieces of information line respectively;
Every described public electrode wire is used to the public electrode power supply of the capable pixel cell of N that links to each other with same gate line.
Two " row " pixel cell of the mutual homeotropic alignment of wherein said " a row pixel cell " and " one-row pixels unit " expression, but only represent the relative position relation between this two " row " pixel cell, and do not represent that " OK " is parallel to ground or " row " perpendicular to ground etc.
In the array base palte of the present invention, a gate line is controlled the capable pixel cell of N simultaneously, therefore its gate line sum is reduced to original 1/N, accordingly, the area of the black matrix of gate line also is reduced to original 1/N, and every public electrode wire be the capable pixel cell power supply of N simultaneously, and the quantity of public electrode wire and corresponding area of deceiving matrix also must reduce, make thus the aperture opening ratio of display device significantly improve Energy Intensity Reduction; Simultaneously, when showing with array base palte of the present invention, have the together conducting and show required content of the capable pixel cell of N during every gate line conducting, but that is to say the capable pixel of its single pass N, therefore if it is constant to scan the required time of every gate line, it scans the required time of whole display panel and can be reduced to original 1/N, that is to say that it can also play the effect that improves refresh rate, improves display quality.
Certainly, because this moment, every row pixel cell was wanted corresponding N data lines, therefore data line quantity can rise, but because the pixel cell quantity that connects on every data lines reduces (being that load reduces), therefore the width of every data lines also can be reduced to original 1/N, the total area of the black matrix of data line just increases a little (owing between adjacent data line several microns interval must be arranged like this, and black matrix will cover this interval, therefore black matrix area has increased slightly), but the black matrix total area is still minimizing; And as previously mentioned, the width of the black matrix of Width data line of the black matrix of gate line is large, even therefore the data line width is constant, the present invention also is equivalent to increase thinner data line and reduces wider gate line, therefore the black matrix total area still can reduce.
Also can learn by above analysis, with respect to reducing data line and increasing the mode (can be regarded as the mode with the present invention's " opposite ") of gate line, the minimizing gate line that the present invention adopts and the mode that increases data line have the following advantages at least: at first, because gate line Width data line width is large, therefore it is more obvious to the effect that reduces black matrix area, increase aperture opening ratio to reduce the quantity of gate line; Secondly, the present invention also can play the effect that improves refresh rate, and as for reducing data line and increasing the mode of gate line, its delegation's pixel cell will could scan several times to be finished, and has reduced on the contrary refresh rate and display quality.
Preferably, described N is 2.
Further preferably, every gate line connects the two row pixel cells that are positioned at its both sides simultaneously.
Further preferably, be used to the public electrode wire of the public electrode power supply of the two row pixel cells that link to each other with same gate line to be positioned at the same side of described two row pixel cells.
Further preferably, each pixel cell comprises a thin film transistor (TFT), and described film crystal is positioned at the sidepiece of described pixel cell, and described sidepiece is near the gate line that links to each other with described pixel cell.
Further preferably, in a row pixel cell, each pixel cell links to each other with two data lines that are positioned at these row pixel cell both sides in turn.
Further preferably, each pixel cell comprises a thin film transistor (TFT), and described film crystal is positioned at the sidepiece of described pixel cell, and described sidepiece is near the data line that links to each other with described pixel cell.
Preferably, described array base palte also comprises: the passivation layer that is formed by organic insulation.
Technical matters to be solved by this invention also comprises, the problem low for display device aperture opening ratio of the prior art, that energy consumption is high provides the display device that a kind of aperture opening ratio is high, energy consumption is low, refresh rate is high.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display device, and it comprises above-mentioned array base palte.
Because display device of the present invention adopts above-mentioned array base palte, so its aperture opening ratio is large, energy consumption is low, and refresh rate is high, and display quality is good.
The present invention can be used in the display device of any patterns such as TN pattern (twisted nematic pattern), VA pattern (vertically pattern of rows and columns), IPS pattern (along the face switching mode), ADS pattern (being the FFS pattern, fringe field switching mode).
Description of drawings
Fig. 1 is the plan structure schematic diagram of existing array base palte;
Fig. 2 is the plan structure schematic diagram of the array base palte of the embodiment of the invention 2;
Fig. 3 is that existing array base palte is in the cross-sectional view at data line place;
Fig. 4 is that the array base palte of the embodiment of the invention 2 is in the cross-sectional view at data line place;
Fig. 5 is the plan structure schematic diagram of the array base palte of embodiments of the invention 3.
Wherein Reference numeral is: 1, pixel cell; 11, thin film transistor (TFT); 12, pixel electrode; 2, gate line; 3, data line; 31, data line connecting line; 32, data line insulation course; 4, public electrode wire; 7, passivation layer; 8, gate protection film; 9, glass substrate.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte, and it comprises: cross arrangement is latticed gate line and data line; The public electrode wire parallel with described gate line; Be arranged as the pixel cell of matrix, wherein each pixel cell connects a gate line and a data lines.
Wherein, every gate line connects the capable pixel cell of N simultaneously, and N is the integer more than or equal to 2;
The N data lines connects a row pixel cell simultaneously, and N the pixel cell that is connected with same gate line in the row pixel cell links to each other with N root different pieces of information line respectively;
Every described public electrode wire is used to the public electrode power supply of the capable pixel cell of N that links to each other with same gate line.
In the array base palte of the present embodiment, a gate line is controlled the capable pixel cell of N simultaneously, therefore its gate line sum is reduced to original 1/N, accordingly, the area of the black matrix of gate line also is reduced to original 1/N, and every public electrode wire be the capable pixel cell power supply of N simultaneously, and the quantity of public electrode wire and corresponding area of deceiving matrix also must reduce, make thus the aperture opening ratio of display device significantly improve Energy Intensity Reduction; Simultaneously, when the array base palte with the present embodiment shows, have the together conducting and show required content of the capable pixel cell of N during every gate line conducting, but that is to say the capable pixel of its single pass N, therefore if it is constant to scan the required time of every gate line, it scans the required time of whole display panel and can be reduced to original 1/N, that is to say that it can also play the effect that improves refresh rate, improves display quality.
Embodiment 2:
The present embodiment provides a kind of array base palte, and such as Fig. 2, shown in Figure 4, it comprises glass substrate 9, and glass substrate 9 is being provided with:
The gate line 2 of many transversely arranged (arranging along " OK " direction in other words).
The data line 3 of many longitudinal arrangements (arranging along " row " direction in other words), itself and gate line 2 form latticed.Obviously, although the array base palte of the present embodiment is 2 transversely arranged with gate line, data line 3 longitudinal arrangements as an example, also be feasible if adopt gate line 2 longitudinal arrangements, data line 3 transversely arranged modes.
The array of pixel cell 1, a sub-pixel on each pixel cell 1 corresponding display device wherein, three sub-pixels form a pixel.Each pixel cell 1 comprises a thin film transistor (TFT) 11 and a pixel electrode 12 that links to each other with the drain electrode of thin film transistor (TFT) 11, wherein the grid of each thin film transistor (TFT) 11 connects a gate line 2, and source electrode connects a data lines 3 (being that each pixel cell 1 connects a gate line 2 and a data lines 3).
Wherein, as shown in Figure 2, every gate line 2 links to each other with two row pixel cells 1 simultaneously, in other words, and per two row pixel cells, 1 corresponding gate line 2.Simultaneously, one row pixel cell, 1 corresponding two data lines 3, in other words, two data lines 3 connect a row pixel cell 1 simultaneously, and two pixel cells 1 that connect same gate line 2 in this row pixel cell 1 link to each other with two data lines 3 respectively, thereby guarantee that two pixel cells 1 can be subjected to respectively the control of two data lines 3 when this gate line 2 conducting.
As seen, by taking with upper type, gate line 2 quantity have reduced half, therefore the area of the black matrix of its correspondence also can reduce half, thereby have improved the aperture opening ratio of display device, have reduced energy consumption.Certainly, the quantity of data line 3 has increased by one times simultaneously, but because pixel cell 1 number that connects on every data lines 3 has reduced half, therefore its load has also reduced half, therefore the width of every data lines 3 also can be reduced to original half, therefore, as long as the width of the black matrix of data line has increased slightly, this increase is in order to cover the gap of 3 of adjacent data lines, and this gap width only is several microns (such as 3 μ m), the reducing to compare of the increase of the black matrix area of data line that is therefore caused by this gap and the black matrix area of gate line is much smaller, therefore the black matrix total area still can obviously reduce, aperture opening ratio can obviously improve.And for gate line 2, because its original width is just larger, therefore although pixel cell 1 quantity that connects thereon increases, its width also need not increase.Through test, the array base palte of the present embodiment can make the aperture opening ratio of display device improve approximately 4 ~ 5%.
Simultaneously, as shown in Figure 2, array base palte also comprises public electrode wire 4, and public electrode wire 4 is parallel to gate line 2, and every public electrode wire 4 is used to the public electrode of the 2 row pixel cells 1 that link to each other with same gate line 2 to power.
Because gate line 2 corresponding two row pixel cells 1 in the present embodiment, therefore public electrode wire 4 public electrode of corresponding two row pixel cells 1 simultaneously, therefore the quantity of public electrode wire 4 has also reduced, thereby can further reduce the area of deceiving matrix, improve aperture opening ratio.
Preferably, every gate line 2 connects the two row pixel cells 1 that are positioned at its both sides (up and down both sides) simultaneously.That is to say, the two row pixel cells 1 that link to each other with every gate line 2 preferably just in time lay respectively at the up and down both sides of this gate line 2, can guarantee that like this gate line 2 can both be easy to link to each other with two row pixel cells 1, and wiring is even, and can reduce the intersection of lead-in wire as far as possible.
Preferably, public electrode wire 4 is positioned at corresponding with it two the same sides of pixel cell at once.That is to say, corresponding its two row pixel cells 1 of both sides up and down of gate line 2, then the public electrode wire 4 corresponding with this two row pixel cell 1 is preferably placed at upside or the downside of this two row pixel cell 1, and not with gate line 2 together.The advantage of this structure is, public electrode wire 4 is located at different positions with gate line 2, can make the distance of 1 of each row pixel cell more even; Simultaneously, because process technology limit, two row pixel cells 1 obviously can not very accurate complete slitless connection together, must there be the gap therebetween, therefore also black matrix must be set, in fact take full advantage of the black matrix that 1 of each row pixel cell must have and public electrode wire 4 and gate line be arranged in 2 minutes, thereby reduced the total area of black matrix, improved aperture opening ratio.
Preferably, the thin film transistor (TFT) 11 in the pixel cell 1 is positioned at a sidepiece (namely not being in the middle of being positioned at) of this pixel cell 1, and this sidepiece is near the gate line 2 that links to each other with this pixel cell 1.That is to say, in two row pixel cells 1 that certain gate line 2 links to each other, thin film transistor (TFT) 11 all is positioned at the side near this gate line 2, in the one-row pixels unit 1 such as gate line 2 upsides, thin film transistor (TFT) 11 is positioned at the downside of pixel cell 1, and in the one-row pixels unit 1 of gate line 2 downsides, thin film transistor (TFT) 11 is positioned at the upside of pixel cell 1.The purpose of design is in order to make thin film transistor (TFT) 11 as far as possible near coupled gate line 2, to make things convenient for it to be connected with gate line 2 like this.
Preferably, in every row pixel cell 1, each pixel cell 1 links to each other with two data lines 3 that are positioned at these row pixel cell 1 both sides in turn.That is to say, in a row pixel cell 1, each pixel cell 1 links to each other with two data lines 3 on right side with its left side in turn.Arrange like this and can guarantee that this row pixel cell 1 and two data lines 3 all can be easy to link to each other, and wiring evenly, and can avoid the intersection that goes between as far as possible.Simultaneously, when adopting this wiring form, must cause 3 two of data lines is one group arranged together, and per like this two data lines 3 can be by a black Matrix cover, thereby the preparation technology of black matrix is simplified.Wherein, be in contact with one another for fear of adjacent data line 3, two-phase is faced 3 of data lines should leave certain gap as previously mentioned, and this gap is generally several microns (as being 3 μ m).
Preferably, the thin film transistor (TFT) 11 in the pixel cell 1 is positioned at a sidepiece (namely not being in the middle of being positioned at) of this pixel cell 1, and this sidepiece is near the data line 3 that links to each other with this pixel cell 1.That is to say, in pixel cell 1 that different pieces of information line 3 links to each other, thin film transistor (TFT) 11 all is positioned at the side near data line 3.In a row pixel cell 1, the thin film transistor (TFT) 11 of the pixel cell 1 that links to each other with the data line 3 in left side is positioned at pixel cell 1 left side, and the thin film transistor (TFT) 11 of the pixel cell 1 that links to each other with the data line 3 on right side is positioned at pixel cell 1 left side.The purpose of design is in order to make thin film transistor (TFT) 11 as far as possible near coupled data line 3, to make things convenient for it to be connected with data line 3 like this.Obviously, if also will make as previously mentioned simultaneously thin film transistor (TFT) 11 near gate line 2, then each thin film transistor (TFT) 11 all should be positioned at the bight of pixel cell 1.
Preferably, as shown in Figure 4, the array base palte of the present embodiment comprises the passivation layer 7 that is formed by organic insulation.Wherein, organic insulation can be known passivation layer 7 materials such as acrylate resin, and it can form by common process such as coatings.As shown in Figure 3, between data line 3 and gate protection film 8 (Gate Insulation) certain difference in height is arranged, therefore can form step, adopting traditional silicon nitride material (SiN
X) during as passivation layer 7, because passivation layer 7 thinner thicknesses can not be eliminated this step, again because near the liquid crystal deflecting element of step can causing is unusual, thus above data line 3, need to arrange the obviously black matrix larger than data line width, thus cause aperture opening ratio to reduce; Simultaneously, gate line 2 places also have the problem of above-mentioned step.And as shown in Figure 4, when adopting organic insulation to form passivation layer 7, because it forms by applying, thickness can be larger, and material is softer, has certain flexibility, therefore can fill and lead up step, form flat surface, therefore the black matrix width above data line 3, gate line 2 only slightly gets final product greater than live width, thereby can further reduce the area of black matrix, improve aperture opening ratio.
Embodiment 3:
The present embodiment provides a kind of array base palte, and it has and the similar structure of the array base palte of embodiment 2.As shown in Figure 5, the difference of itself and embodiment 2 is:
At first, in the array base palte of the present embodiment, per three row pixel cells, 1 corresponding gate line 2, namely every gate line 2 links to each other with three row pixel cells 1 simultaneously.Simultaneously, a row pixel cell 1 corresponding three data lines 3, namely three data lines 3 connect a row pixel cell 1 simultaneously, and three pixel cells 1 of same gate line 2 of connection link to each other with three data lines 3 respectively in this row pixel cell 1.A because row pixel cell 1 corresponding three data lines 3 in the array base palte of the present embodiment, therefore when this row pixel cell 1 links to each other with data line 3 by connecting line 31, must there be part connecting line 31 to intersect with data line 3, this just need to arrange insulation course 32 or similar structures in the part position of segment data line 3, in order to avoid connecting line 31 is with 3 conductings of different data lines; Therefore, when making the array base palte of the present embodiment, three data lines 3 need to form in different composition technique (photoetching-depositing operation), and also will increase the step that forms insulation course 32.Because the technique at the enterprising row wiring of array base palte and formation insulation course etc. is known, therefore no longer be described in greater detail at this.
Secondly, in the array base palte of the present embodiment, gate line 2 is positioned at the same side of three coupled row pixel cells 1; Three data lines 3 that link to each other with a row pixel cell 1 also are positioned at the same side of this row pixel cell 1.
Three, in the array base palte of the present embodiment, public electrode wire 4 is positioned at gate line 2 sidepieces.
In the array base palte of the present embodiment, the corresponding gate line 2 of per three row pixel cells 1, so its gate line 2 can be reduced to original 1/3, therefore its reduce black matrix area, effect of improving aperture opening ratio is more obvious.
Obviously, the array base palte of the various embodiments described above also can carry out many variations: can be four lines or corresponding gate line of pixel cell of multirow more, and a row pixel cell corresponding four or more data line; Gate line, data line and can change with relative position relation between pixel cell that they link to each other, can lay respectively at gate line both sides (such as embodiment 2) such as the multirow pixel cell that links to each other with a gate line, also can be positioned at the same side (such as embodiment 3) of gate line, the many data lines that link to each other with a row pixel cell can lay respectively at the both sides (such as embodiment 2) of this row pixel cell, also can be positioned at the same side (such as embodiment 3) of this row pixel cell; Also can be provided with special other structures such as storage capacitor electrode on the array base palte.
Embodiment 4:
The present embodiment provides a kind of display panels, and it comprises color membrane substrates and the described array base palte of above-mentioned any embodiment, and is provided with black matrix at least above the gate line of array base palte and data line.
Wherein, " above the gate line of array base palte and data line, being provided with black matrix at least " refer to this black matrix should be at least can covering gate polar curve and data line, thereby the light that stops backlight to send penetrates via gate line and data line place; Certainly, also can be provided with black matrix in positions such as public electrode wire, thin film transistor (TFT)s.Concrete, black matrix can be arranged on the color membrane substrates, also can be arranged on (BM on Array) on the array base palte.
Obviously, because what adopt in the display panels of the present embodiment is above-mentioned array base palte, therefore the quantity of its gate line and data line, position etc. are different from existing display panels, so the quantity of its grid drive chip (Gate Driver IC), data driving chip (Data Driver IC) etc., interface position etc. also will carry out respective change.
Certainly, also should comprise other known parts, such as chock insulator matter, liquid crystal material, framework etc. in the display panels of the present embodiment.
Because the display panels of the present embodiment adopts above-mentioned array base palte, so its aperture opening ratio is large, energy consumption is low, and refresh rate is high, and display quality is good.
Embodiment 5:
The present embodiment provides a kind of display device, and it comprises the described array base palte of above-mentioned any embodiment.
The embodiment of the invention also provides a kind of display device, and it comprises above-mentioned any one array base palte.Described display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Because the display device of the present embodiment adopts above-mentioned array base palte, so its aperture opening ratio is large, energy consumption is low, and refresh rate is high, and display quality is good.
Be understandable that, above embodiment only is the illustrative embodiments that adopts for principle of the present invention is described, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement also are considered as protection scope of the present invention.
Claims (9)
1. array base palte, comprising: cross arrangement is latticed gate line and data line; The public electrode wire parallel with described gate line; Be arranged as the pixel cell of matrix, wherein each pixel cell connects a gate line and a data lines; It is characterized in that,
Every gate line connects the capable pixel cell of N simultaneously, and N is the integer more than or equal to 2;
The N data lines connects a row pixel cell simultaneously, and N the pixel cell that is connected with same gate line in the row pixel cell links to each other with N root different pieces of information line respectively;
Every described public electrode wire is used to the public electrode power supply of the capable pixel cell of N that links to each other with same gate line.
2. array base palte according to claim 1 is characterized in that, described N is 2.
3. array base palte according to claim 2 is characterized in that, every gate line connects the two row pixel cells that are positioned at its both sides simultaneously.
4. array base palte according to claim 3 is characterized in that, is used to the public electrode wire of the public electrode power supply of the two row pixel cells that link to each other with same gate line to be positioned at the same side of described two row pixel cells.
5. array base palte according to claim 2 is characterized in that, each pixel cell comprises a thin film transistor (TFT), and described film crystal is positioned at the sidepiece of described pixel cell, and described sidepiece is near the gate line that links to each other with described pixel cell.
6. array base palte according to claim 2 is characterized in that, in a row pixel cell, each pixel cell links to each other with two data lines that are positioned at these row pixel cell both sides in turn.
7. array base palte according to claim 2 is characterized in that, each pixel cell comprises a thin film transistor (TFT), and described film crystal is positioned at the sidepiece of described pixel cell, and described sidepiece is near the data line that links to each other with described pixel cell.
8. the described array base palte of any one in 7 according to claim 1 is characterized in that, also comprises: the passivation layer that is formed by organic insulation.
9. a display device is characterized in that, comprising: the described array base palte of any one in the claim 1 to 8.
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| WO2016054897A1 (en) * | 2014-10-10 | 2016-04-14 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal display device |
| CN106483726A (en) * | 2016-12-21 | 2017-03-08 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method and display panels |
| CN106873276A (en) * | 2017-03-21 | 2017-06-20 | 昆山龙腾光电有限公司 | Display device and its driving method |
| WO2017121078A1 (en) * | 2016-01-14 | 2017-07-20 | Boe Technology Group Co., Ltd. | Array substrate, display panel, and display apparatus |
| CN110346995A (en) * | 2019-07-26 | 2019-10-18 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate |
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| CN112071276A (en) * | 2020-10-15 | 2020-12-11 | 武汉华星光电技术有限公司 | Backlight source, backlight module and display device |
| CN112820237A (en) * | 2019-10-31 | 2021-05-18 | 京东方科技集团股份有限公司 | Electronic substrate, driving method thereof and display device |
| US20220373851A1 (en) * | 2020-07-29 | 2022-11-24 | Beijing Boe Optoelectronics Technology Co., Ltd. | Electronic paper display screen and manufacturing method therefor, and display device |
| WO2023206167A1 (en) * | 2022-04-27 | 2023-11-02 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
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| CN112820237A (en) * | 2019-10-31 | 2021-05-18 | 京东方科技集团股份有限公司 | Electronic substrate, driving method thereof and display device |
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