KR102076841B1 - Thin Film Transistor Substrate For Flat Panel Display Having Additional Common Line - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a flat panel display device having a metallic auxiliary common wiring without decreasing transmittance. A thin film transistor substrate for a flat panel display according to the present invention includes a substrate; Gate wiring arranged in a horizontal direction on the substrate; Data lines arranged in a vertical direction on the substrate; A pixel region arranged in a matrix manner by the cross structure of the gate wiring and the data wiring; A pixel electrode formed to define at least two domain regions within the pixel region; An auxiliary common line formed over the composite angle region of the pixel electrode; And a plurality of line segments overlapping the pixel electrode in the pixel area, and including a common electrode connected to the auxiliary common line.

Description

Thin Film Transistor Substrate For Flat Panel Display Having Additional Common Line}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a flat panel display device having a metallic auxiliary common wiring without decreasing transmittance. In particular, the present invention provides a thin film transistor substrate for a flat panel display device having a common auxiliary wiring of a metal in a complex angle region that becomes a non-transmissive region by configuring two or more domains in a single pixel, thereby preventing an increase in planar resistance without decreasing transmittance. It is about.

A liquid crystal display of an active matrix driving type displays image information using a thin film transistor (or TFT) as a switching element. As liquid crystal displays are more compact than cathode ray tubes (CRTs), they are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes.

The liquid crystal display includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying data voltages to data lines of the liquid crystal display panel, and a gate of the liquid crystal display panel. And a gate drive IC for supplying a gate pulse (or scan pulse) to the wirings (or scan wirings), a control circuit for controlling the ICs, and a light source driving circuit for driving a light source of the backlight unit.

Thanks to the rapid development of the process technology and the driving technology of the liquid crystal display device, the manufacturing cost of the liquid crystal display device is lowered and the image quality is greatly improved. In particular, a double rate driving (DRD) technique has been proposed in which two subpixels existing in one horizontal line are connected to one data line, and a data voltage having the same polarity is supplied to the two subpixels. The DRD technology can control two subpixels through one data line, thereby reducing manufacturing costs by reducing the number of source drive ICs. In the DRD technology, the source drive IC is driven in a column inversion manner to supply data voltages having different polarities to adjacent data lines, and the liquid crystal display panel is driven in horizontal two dot inversion.

1 is a block diagram showing a liquid crystal display device according to the prior art. Referring to FIG. 1, a liquid crystal display includes a liquid crystal display panel 10 in which a pixel array PA is formed, source drive integrated circuits 12, and gate driving circuits 13. And a timing controller 11. A backlight unit for uniformly irradiating light onto the liquid crystal display panel 10 may be disposed under the liquid crystal display panel 10.

The liquid crystal display panel 10 includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer interposed therebetween. The pixel array PA is formed in the liquid crystal display panel 10. In the pixel array PA, pixel regions defined by a cross structure of data lines and gate lines are arranged in a matrix. Each pixel displays digital video data using thin film transistors and subpixels. The lower glass substrate of the pixel array PA includes data lines, gate lines, thin film transistors, a pixel electrode of a subpixel connected to the thin film transistor, a storage capacitor connected to the pixel electrode, and the like. Each of the subpixels of the pixel array PA adjusts the amount of light transmitted by driving the liquid crystal of the liquid crystal layer by a voltage difference between the pixel electrode charged with the data voltage and the common electrode applied with the common voltage through the thin film transistor. Display.

The black matrix and the color filter are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode is formed on the upper glass substrate in the case of the vertical electric field driving method such as TN (TwiPREd Nematic) mode and VA (Vertical Alignment) mode, and the In-Plane Switching (IPS) mode and the FFS (Fringe Field Switching) mode. In the case of the same horizontal electric field driving method, it is formed on the lower glass substrate together with the pixel electrode. Here, the horizontal field type liquid crystal display device will be described. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, or the like. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a tape carrier package (TCP) 15, bonded to a lower glass substrate of the liquid crystal display panel 10 by a tape automated bonding (TAB) process, and a source printed circuit board (PCB). 14). The source drive ICs 12 may be adhered onto the lower glass substrate of the liquid crystal display panel 10 by a chip on glass (COG) process.

Each of the source drive ICs 12 receives digital video data and a source timing control signal from the timing controller 11. The source drive ICs 12 convert digital video data into positive / negative data voltages in response to a source timing control signal, and supply the digital video data to data lines of the pixel array PA. The source drive ICs 12 output data voltages to the data lines in a column inversion manner under the control of the timing controller 11. The column inversion method refers to a method of supplying data voltages having opposite polarities to neighboring data lines and maintaining the same polarity of data voltages supplied to each of the data lines for one frame period. For example, the source drive ICs 12 may output data voltages whose polarities are inverted in a column inversion manner to the data lines as shown in FIG. 7.

The gate driving circuit 13 receives a gate timing control signal from the timing controller 11. The gate driving circuit 13 sequentially supplies gate pulses (or scan pulses) to gate lines of the pixel array in response to the gate timing control signal. The gate driving circuit 13 may be mounted on the TCP and bonded to the lower glass substrate of the liquid crystal display panel 10 by a TAB process. Alternatively, the gate driving circuit 13 may be directly formed on the lower glass substrate at the same time as the pixel array PA by a gate in panel (GIP) process. The gate driving circuit 13 may be disposed on one side of the pixel array PA or both sides of the pixel array PA as shown in FIG. 1.

The timing controller 11 receives digital video data and timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock from an external system board. The timing controller 11 includes a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing for controlling the operation timing of the gate driving circuit 13 based on the digital video data and the timing signals. Generate a control signal. The timing controller 11 supplies digital video data and a source timing control signal to the source drive ICs 12. The timing controller 11 supplies the gate timing control signal to the source drive ICs 12. The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 may be connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

2 is a schematic diagram illustrating the structure of a pixel array in a horizontal field type liquid crystal display panel according to the related art. For convenience of description, only some of the data lines and some of the gate lines of the pixel array are illustrated in FIG. 2. That is, FIG. 2 shows the first to fourth data lines D1, D2, D3, and D4 and the first to fourth gate lines G1, G2, G3, and G4 crossing them.

Referring to FIG. 2, pixel electrodes are formed in a pixel region defined by intersections of data lines and gate lines. Thin film transistors are formed at intersections of the data lines and the gate lines. Each of the pixel electrodes is connected to a thin film transistor to receive a data voltage applied to a data line.

Specifically, the source electrode of the thin film transistor formed at the intersection of the j-th data line Dj and the k-th gate line Gk is connected to the j-th data line Dj and the drain electrode is connected to the j-th data line Dj. It is connected to non-adjacent pixel electrodes, that is, pixel electrodes adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1. Meanwhile, the source electrode of the thin film transistor formed at the intersection of the j-th data line Dj and the k-th gate line Gk-1 or the k + 1th gate line Gk + 1 is the j-th data line Dj The drain electrode is connected to the pixel electrode adjacent to the j th data line Dj.

For example, as shown in FIG. 2, the source electrode of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1 and drain electrode. May be connected to the second pixel electrode PE2 adjacent to the second data line D2 and not adjacent to the first data line D1. In contrast, the source electrode of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the first data line D1, and the drain electrode is connected to the first data line. It may be connected to the first pixel electrode PE1 adjacent to (D1). TFT and j-th data line Dj and k-th gate line Gk-1 or k + 1 th gate line Gk formed at the intersection of j-th data line Dj and k-th gate line Gk A detailed description of the connection structure of the TFTs formed at the intersections of +1) will be given later with reference to FIG.

In addition, only one of the pixel electrodes adjacent to the j th data line Dj is connected to the j th data line Dj on the same horizontal line, and the other pixel electrode is the j-1 data line Dj-1 or It is connected to the j + 1th data line Dj + 1. For example, as shown in FIG. 2, only the third pixel electrode PE3, which is adjacent to the second data line D2 and the third pixel electrode PE3, is connected to the second data line D2. The second pixel electrode PE2 may be connected to the first data line D1. Further, only the tenth pixel electrode PE10 of the tenth pixel electrode PE10 and the eleventh pixel electrode PE11 adjacent to the third data line D3 is connected to the third data line D3, and the eleventh pixel electrode PE11 may be connected to the fourth data line D4.

Further, the pixel electrodes between the j-th data line Dj and the j-th data line Dj-1 or the j + 1th data line Dj + 1 may be connected only to the jth data line Dj or j-th. It is connected only to the -1 data line Dj-1 or the j + 1th data line Dj + 1. For example, as illustrated in FIG. 2, the first pixel electrode PE1 and the second pixel electrode PE2 between the first data line D1 and the second data line D2 are connected only to the first data line D1. Can be. In addition, the seventh pixel electrode PE7 and the eighth pixel electrode PE8 between the first data line D1 and the second data line D2 may be connected only to the second data line D2.

FIG. 3 is an enlarged plan view showing in detail a first subpixel including a first pixel electrode and a second subpixel including a second pixel electrode of FIG. 2. In FIG. 3, only the first subpixel including the first pixel electrode PE1 and the second subpixel including the second pixel electrode PE2 are illustrated for convenience of description.

Referring to FIG. 3, the data lines D1 and D2 are formed in a vertical direction (y axis direction). The gate lines G1 and G2 are formed in a horizontal direction (x-axis direction) to intersect the data lines D1 and D2. When implemented in the IPS mode as shown in FIG. 3, the first and second pixel electrodes PE1 and PE2 are formed on the entire pixel area, but the common electrode COM is formed in a slit shape on the pixel area. As a result, the first and second pixel electrodes PE1 and PE2 and the common electrode COM may form a horizontal electric field. The common electrode COM is formed over the entire surface of the substrate, and has a slit (or line segment) shape overlapping the pixel electrodes PE1 and PE2 only in the pixel region. Therefore, the common electrode VcomE has a structure connected to each other throughout the substrate.

TFTs T1 and T2 are formed at intersections of the data lines D1 and D2 and the gate lines G1 and G2. Each of the first and second pixel electrodes PE1 and PE2 is connected to a TFT to receive a data voltage applied to a data line. For example, the source electrode SE1 of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1, but is a drain electrode. The DE1 may not be adjacent to the first data line D1 and may be connected to the second pixel electrode PE2 adjacent to the second data line D2. In particular, the drain electrode DE1 extends from the second pixel electrode PE2 through the first contact electrode CE1 formed in the first contact hole CNT1 and the second contact hole CNT2. ) Can be connected. That is, the first contact electrode CE1 is connected to the drain electrode DE1 of the first TFT T1 in the first contact hole CNT1 and the first protruding electrode STE1 in the second contact hole CNT2. Connected. The length of the first protruding electrode STE1 may be longer than that of the drain electrode DE1 of the first TFT T1.

In addition, the source electrode SE2 of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the second data line D2, and the drain electrode DE2 is connected. ) May be connected to the first pixel electrode PE1 adjacent to the first data line D1. The drain electrode DE2 of the second TFT T2 is formed in the second protruding electrode STE2, the fourth contact hole CNT4, and the fifth contact hole CNT5 extending from the first pixel electrode PE1. It may be connected via the contact electrode CE2. That is, the second contact electrode CE2 is connected to the drain electrode DE2 of the second TFT T2 in the fourth contact hole CNT4 and the second protruding electrode STE2 in the fifth contact hole CNT5. Connected. In this case, the length of the second protrusion electrode STE2 may be shorter than the length of the first protrusion electrode PRE1 and shorter than the length of the drain electrode DE2 of the second TFT T2.

3, a portion of the first protrusion electrode STE1 overlaps a portion of the drain electrode DE1 of the first TFT T1, and a portion of the second protrusion electrode STE2 is the second TFT T2. It may be overlapped with a part of the drain electrode DE2 of, but is not limited thereto. That is, the first protruding electrode PRE1 may be formed so as not to overlap the drain electrode DE1 of the first TFT T1 at all, and the second protruding electrode PRE2 is the drain electrode of the second TFT T2. It may be formed so as not to overlap with DE2) at all.

In the horizontal field type liquid crystal display panel according to the related art as described above, the common electrode COM is integrally connected to each other over the entire substrate. In particular, the common electrode COM includes a transparent conductive material having excellent light transmittance. As a representative example of the transparent conductive material, Indium-Tin-Oxide or Indium-Zinc-Oxide is used. Since the oxide has a high resistance value, when implemented in a large area, the total resistance of the common electrode may be increased. As a result, spot defects in which brightness of image data is not constant over the entire screen area may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor substrate for a flat panel display device having an auxiliary common wiring for reducing the surface resistance of a common electrode. Another object of the present invention is to provide a thin film transistor substrate for a flat panel display device in which a horizontal auxiliary electric field type liquid crystal display device having a complex angle structure is provided with a metallic auxiliary common wiring to prevent an increase in planar resistance without decreasing transmittance. .

In order to achieve the above object, a thin film transistor substrate for a flat panel display device according to the present invention, the substrate; Gate wiring arranged in a horizontal direction on the substrate; Data lines arranged in a vertical direction on the substrate; A pixel region arranged in a matrix manner by the cross structure of the gate wiring and the data wiring; A pixel electrode formed to define at least two domain regions within the pixel region; An auxiliary common line formed over the composite angle region of the pixel electrode; And a plurality of line segments overlapping the pixel electrode in the pixel area, and including a common electrode connected to the auxiliary common line.

Two pixel regions of the pixel regions are disposed between two neighboring data lines among the data lines.

The auxiliary common line may include the same material as the gate line, may be disposed on the same layer as the gate line, and may be arranged in parallel with the gate line.

A gate insulating film coated on the gate wiring and the auxiliary common wiring; A semiconductor layer, a source electrode and a drain electrode formed on the gate insulating film; And a first passivation layer coated on the source electrode and the drain electrode, wherein the pixel electrode is formed on the first passivation layer and contacts the drain electrode.

The display device may further include a second passivation layer formed on the pixel electrode, wherein the common electrode contacts the auxiliary common line through a contact hole passing through the second passivation layer, the first passivation layer, and the gate insulating layer.

The thin film transistor substrate for a flat panel display device according to the present invention further includes a plurality of auxiliary common wirings crossing the substrate with the same material as the gate metal, so that the surface resistance of the common electrode can be reduced. Therefore, in the large-area flat panel display device, it is possible to provide high quality screen characteristics that ensure uniform luminance over the entire large-area display panel. In addition, in the present invention, since the metallic auxiliary common wiring is disposed in the complex angle region that becomes the non-transmissive region by configuring two or more domains in a single pixel, the thin film transistor substrate for a flat panel display device prevents an increase in planar resistance without decreasing transmittance. Can be provided.

1 is a block diagram showing a liquid crystal display device according to the prior art.
2 is a schematic view showing the structure of a pixel array in a horizontal field-type liquid crystal display panel according to the prior art.
3 is an enlarged plan view illustrating in detail a first subpixel including a first pixel electrode and a second subpixel including a second pixel electrode of FIG. 2;
4 is a schematic diagram illustrating a structure of a thin film transistor substrate of a horizontal field type liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 5 is an enlarged plan view illustrating in detail a first subpixel including a first pixel electrode and a second subpixel including a second pixel electrode of FIG. 4.
FIG. 6 is a cross-sectional view of the cross-sectional structure taken along the line II ′ and II-II ′ of FIG. 5. FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of the ease of preparation of the specification, and may be different from the actual component names.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 4 to 6. 4 is a schematic diagram illustrating a structure of a thin film transistor substrate of a horizontal field type liquid crystal display according to an exemplary embodiment of the present invention.

4 illustrates only some of the data lines and some of the gate lines formed in the pixel array for convenience of description. That is, FIG. 4 shows the first to fourth data lines D1, D2, D3, and D4 and the first to fourth gate lines G1, G2, G3, and G4 crossing them.

Referring to FIG. 4, pixel electrodes are formed in a pixel region defined by intersections of data lines and gate lines. Thin film transistors are formed at intersections of the data lines and the gate lines. Each of the pixel electrodes is connected to a thin film transistor to receive a data voltage applied to a data line.

Specifically, the source electrode of the thin film transistor formed at the intersection of the j-th data line Dj and the k-th gate line Gk is connected to the j-th data line Dj and the drain electrode is connected to the j-th data line Dj. It is connected to non-adjacent pixel electrodes, that is, pixel electrodes adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1. Meanwhile, the source electrode of the thin film transistor formed at the intersection of the j-th data line Dj and the k-th gate line Gk-1 or the k + 1th gate line Gk + 1 is the j-th data line Dj The drain electrode is connected to the pixel electrode adjacent to the j th data line Dj.

For example, as shown in FIG. 4, the source electrode of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1 and drain electrode. May be connected to the second pixel electrode PE2 adjacent to the second data line D2 and not adjacent to the first data line D1. In contrast, the source electrode of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the first data line D1, and the drain electrode is connected to the first data line. It may be connected to the first pixel electrode PE1 adjacent to (D1). TFT and j-th data line Dj and k-th gate line Gk-1 or k + 1 th gate line Gk formed at the intersection of j-th data line Dj and k-th gate line Gk A detailed description of the connection structure of the TFTs formed at the intersections of +1) will be given later with reference to FIG.

In addition, only one of the pixel electrodes adjacent to the j th data line Dj is connected to the j th data line Dj on the same horizontal line, and the other pixel electrode is the j-1 data line Dj-1 or It is connected to the j + 1th data line Dj + 1. For example, as shown in FIG. 4, only the third pixel electrode PE3, which is adjacent to the second data line D2 and the third pixel electrode PE3, is connected to the second data line D2. The second pixel electrode PE2 may be connected to the first data line D1. Further, only the tenth pixel electrode PE10 of the tenth pixel electrode PE10 and the eleventh pixel electrode PE11 adjacent to the third data line D3 is connected to the third data line D3, and the eleventh pixel electrode PE11 may be connected to the fourth data line D4.

Further, the pixel electrodes between the j-th data line Dj and the j-th data line Dj-1 or the j + 1th data line Dj + 1 may be connected only to the jth data line Dj or j-th. It is connected only to the -1 data line Dj-1 or the j + 1th data line Dj + 1. For example, as illustrated in FIG. 4, the first pixel electrode PE1 and the second pixel electrode PE2 between the first data line D1 and the second data line D2 are connected only to the first data line D1. Can be. In addition, the seventh pixel electrode PE7 and the eighth pixel electrode PE8 between the first data line D1 and the second data line D2 may be connected only to the second data line D2.

On the other hand, in the horizontal electric field type liquid crystal display device, as shown in FIG. 4, the common electrode COM has a line segment or slit shape and overlaps the pixel electrodes PE1, PE2,... In the pixel region. . The pixel electrodes PE1, PE2,..., Formed in each pixel region are connected to each other to form one structure over the entire area of the substrate.

Particularly, in the present invention, when the common electrode COM is formed of a material having a specific resistance higher than that of a metal material, such as indium-tin oxide or indium-zinc oxide, which is a transparent conductive material, it is formed of a metal material to lower the sheet resistance. It further includes an auxiliary common wiring (Acom). The auxiliary common wiring Acom may be formed of the same material as the gate wiring.

However, metal materials such as gate wirings have low light transmittance. Thus, in order to prevent the light transmittance from being lowered due to the auxiliary common wiring Acom, it is necessary to arrange the auxiliary common wiring Acom at a position other than the opening area. In the present invention, in the case of having a multi-domain pixel structure having a compound angle, the auxiliary common wiring Acom is disposed in the compound angle region corresponding to the non-display area. A detailed arrangement relationship of the auxiliary common wiring Acom will be described with reference to FIG. 5.

FIG. 5 is an enlarged plan view illustrating in detail a first subpixel including a first pixel electrode and a second subpixel including a second pixel electrode of FIG. 4. In FIG. 5, for convenience of description, only the first subpixel including the first pixel electrode PE1 and the second subpixel including the second pixel electrode PE2 of FIG. 2 are illustrated.

Referring to FIG. 5, the data lines D1 and D2 are formed in a vertical direction (y axis direction). The gate lines G1 and G2 are formed in a horizontal direction (x-axis direction) to intersect the data lines D1 and D2. When implemented in the IPS mode as shown in FIG. 5, the first and second pixel electrodes PE1 and PE2 are formed on the entire pixel area, but the common electrode COM is formed in a slit shape on the pixel area. As a result, the first and second pixel electrodes PE1 and PE2 and the common electrode COM may form a horizontal electric field. The common electrode COM is formed over the entire surface of the substrate, and has a slit (or line segment) shape overlapping the pixel electrodes PE1 and PE2 only in the pixel region. Therefore, the common electrode COM has a structure connected to each other throughout the substrate.

TFTs T1 and T2 are formed at intersections of the data lines D1 and D2 and the gate lines G1 and G2. Each of the first and second pixel electrodes PE1 and PE2 is connected to a TFT to receive a data voltage applied to a data line. For example, the source electrode SE1 of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1, but is a drain electrode. The DE1 may not be adjacent to the first data line D1 and may be connected to the second pixel electrode PE2 adjacent to the second data line D2. In particular, the drain electrode DE1 extends from the second pixel electrode PE2 through the first contact electrode CE1 formed in the first contact hole CNT1 and the second contact hole CNT2. ) Can be connected. That is, the first contact electrode CE1 is connected to the drain electrode DE1 of the first TFT T1 in the first contact hole CNT1 and the first protruding electrode STE1 in the second contact hole CNT2. Connected. The length of the first protruding electrode STE1 may be longer than that of the drain electrode DE1 of the first TFT T1.

In addition, the source electrode SE2 of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the second data line D2, and the drain electrode DE2 is connected. ) May be connected to the first pixel electrode PE1 adjacent to the first data line D1. The drain electrode DE2 of the second TFT T2 is formed in the second protruding electrode STE2, the fourth contact hole CNT4, and the fifth contact hole CNT5 extending from the first pixel electrode PE1. It may be connected via the contact electrode CE2. That is, the second contact electrode CE2 is connected to the drain electrode DE2 of the second TFT T2 in the fourth contact hole CNT4 and the second protruding electrode STE2 in the fifth contact hole CNT5. Connected. In this case, the length of the second protrusion electrode STE2 may be shorter than the length of the first protrusion electrode PRE1 and shorter than the length of the drain electrode DE2 of the second TFT T2.

In addition, as shown in FIG. 5, a portion of the first protrusion electrode STE1 overlaps with a portion of the drain electrode DE1 of the first TFT T1, and a portion of the second protrusion electrode STE2 is the second TFT T2. It may be overlapped with a part of the drain electrode DE2 of, but is not limited thereto. That is, the first protruding electrode PRE1 may be formed so as not to overlap the drain electrode DE1 of the first TFT T1 at all, and the second protruding electrode PRE2 is the drain electrode of the second TFT T2. It may be formed so as not to overlap with DE2) at all.

In particular, the auxiliary common wiring Acom is formed over the compound angle region CA. The compound angle area CA is an area where the upper domain and the lower domain meet in the pixel area. In this region, the liquid crystal array is not uniform, so that the liquid crystal is substantially non-transmissive. By arranging in the auxiliary common wiring Acom, the overall transmittance is not affected at all.

In addition, the auxiliary common wiring Acom may be electrically connected to the common electrode COM to perform its function. The auxiliary common wiring Acom and the common electrode COM are formed on different layers. That is, the auxiliary common wiring Acom is preferably formed on the same layer by the same metal as the gate wirings G1 and G2. Therefore, the auxiliary common wiring Acom and the common electrode COM are disposed in different layers with the insulating film interposed therebetween.

In order to contact the auxiliary common wiring Acom and the common electrode COM with each other, it is preferable to connect the third common hole CNT3 through the insulating layer. In addition, the position where the third contact hole CNT connecting the auxiliary common wiring Acom and the common electrode COM is formed is also preferably disposed where the transmittance of the display device is not lowered.

Where no data lines D1 and D2 are formed, that is, no wiring is disposed between two neighboring data lines D1 and D2, and the area is divided by the black matrix to distinguish neighboring pixels. . In particular, the common electrode COM is disposed in this portion. Therefore, it is preferable to form the third contact hole CNT3 connecting the common electrode COM and the auxiliary common wiring Acom to each other. A connection structure between the common electrode COM and the auxiliary common wiring Acom through the third contact hole CNT3 will be described in more detail with reference to FIG. 6.

FIG. 6 is a cross-sectional view illustrating a cross-sectional structure taken along cut lines I-I 'and II-II' of FIG. 5. 5 and 6, a gate metal pattern including a gate line, a gate electrode GE1 of the first TFT T1, and gate lines G1 and G2 is formed on the lower substrate SUB. In particular, in the present invention, the gate metal pattern further includes an auxiliary common wiring Acom in the composite angle region CA of the pixel electrode to be formed later in the pixel region.

A gate insulating film GI covering the gate metal pattern is formed on the entire surface of the lower substrate SUB. A semiconductor pattern SEM is formed on the gate insulating layer GI, and a data line, a source electrode SE1 and a drain electrode DE1 of the first TFT T1, and a source electrode of the second TFT T2 are formed on the semiconductor pattern GI. A source / drain metal pattern including SE2) and drain electrode DE2 is formed. A region exposed between the source electrode SE2 and the drain electrode DE of the semiconductor pattern SEM functions as a channel layer.

The first passivation layer PA1 covering the source / drain metal pattern is formed on the entire surface of the lower substrate SUB. After forming the first passivation layer PA1, a first contact hole CNT1 is formed through the first passivation layer PA1 to expose the drain electrode DE1 of the first TFT T1. In addition, a second contact hole CNT2 is formed through the first passivation layer PA1 to expose the drain electrode DE2 of the second TFT T2.

A transparent conductive material is coated on the first passivation layer PA1 and patterned to form a second pixel electrode PE2 contacting the drain electrode DE1 of the first TFT T1 through the first contact hole CNT1. . In particular, the first protruding electrode STE1 branched from the second pixel electrode PE2 is in contact with the drain electrode DE1. In addition, the first pixel electrode PE1 is formed to contact the drain electrode DE2 of the second TFT T2 through the second contact hole CNT2. Similarly, it is preferable that the second protruding electrode STE2 branched from the first pixel electrode PE1 contacts the drain electrode DE2. The second passivation layer PA2 is coated on the entire surface of the substrate SUB on which the pixel electrodes PE1, PE2,...

The second passivation layer PA2, the first passivation layer PA1, and the gate insulating layer GI are patterned to form a common electrode COM positioned between two pixel electrodes disposed between two adjacent data lines. A third contact hole CNT3 exposing a portion is formed. In particular, the third contact hole CNT3 may be disposed to be positioned inside the black matrix region disposed between the pixel electrodes.

The transparent conductive material is again coated and patterned on the second passivation layer PA2 to form a common electrode COM. In particular, the common electrode COM may be formed to have a line segment shape overlapping the pixel electrodes PE1, PE2,... On the other hand, the common electrode COM is preferably electrically connected to the auxiliary common wiring Acom formed of the gate wiring material through the third contact hole CNT3.

5 and 6 illustrate only the first sub-pixel including the first pixel electrode PE1 and the second sub-pixel including the second pixel electrode PE2 in FIG. 4. However, the seventh subpixel including the seventh pixel electrode PE7 and the eighth subpixel including the eighth pixel electrode PE8 may include TFTs connected to the pixel electrodes and a first protruding electrode STE1. ) And only the formation position of the second protruding electrode STE2 may be substantially the same as described with reference to FIGS. 5 and 6.

That is, the connection structure of the seventh TFT T7 connected to the seventh pixel electrode PE7 is a TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk, and the source electrode is j-th. The drain electrode connected to the data line Dj and not adjacent to the j th data line Dj, that is, the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1 It can be formed similarly to the first TFT (T1) of FIG. The connection configuration of the eighth TFT T8 connected to the eighth pixel electrode PE8 may include the j-th data line Dj and the k-th gate line Gk-1 or the k-th + 1th gate line Gk + 1 Of the second TFT of FIG. 2 illustrated as a TFT connected to a j th data line Dj and a drain electrode connected to a pixel electrode adjacent to the j th data line Dj. It can be formed similarly to T2).

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

10: LCD panel 11: timing controller
12: source drive integrated circuit 13: gate driving circuit

Claims (6)

Board;
Gate wiring arranged in a horizontal direction on the substrate;
Data lines arranged in a vertical direction on the substrate;
A pixel region arranged in a matrix manner by the cross structure of the gate wiring and the data wiring;
A pixel electrode formed to define at least two domain regions within the pixel region;
An auxiliary common line formed over the composite angle region of the pixel electrode; And
A plurality of line segments overlapping the pixel electrode in the pixel area, and including a common electrode connected to the auxiliary common line;
A thin film transistor substrate for a flat panel display, characterized in that two pixel electrodes arranged in the same row between adjacent data lines are connected to the same data line.
The method of claim 1,
2. The thin film transistor substrate of claim 1, wherein two columns of pixel areas are disposed between the two data lines adjacent to each other among the data lines.
The method of claim 1,
The auxiliary common wiring includes the same material as the gate wiring;
It is disposed on the same layer as the gate wiring,
And a thin film transistor substrate arranged in parallel with the gate wiring.
The method of claim 3, wherein
A gate insulating film coated on the gate wiring and the auxiliary common wiring;
A semiconductor layer, a source electrode and a drain electrode formed on the gate insulating film; And
Further comprising a first passivation layer on the source electrode and the drain electrode,
The pixel electrode is formed on the first passivation layer and contacts the drain electrode.
The method of claim 4, wherein
A second passivation layer coated on the pixel electrode;
And the common electrode is in contact with the auxiliary common wiring through a contact hole penetrating through the second passivation layer, the first passivation layer, and the gate insulating layer. The method of claim 1,
The data wires connected to the two pixel electrodes arranged in the first row of the adjacent rows between the data lines adjacent to each other are different from the data wires connected to the two pixel electrodes arranged in the second row. A thin film transistor substrate for flat panel displays.

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