KR102175279B1 - Liquid crystal display device - Google Patents

Abstract

The liquid crystal display of the present invention is a liquid crystal display of a double rate drive (DRD) structure to reduce manufacturing cost by reducing the number of data drive ICs. One data line is divided into two sub-data lines. On the other hand, by designing the channel direction of all the thin film transistors in the display area in one direction, this is to prevent parasitic capacitance fluctuations due to distortion of the overlay while maintaining the DRD structure. A display area in which a plurality of sub-pixels are arranged in a matrix form and A substrate divided into pad areas around the display area; A plurality of gate lines and a plurality of sub-data lines formed on the substrate and crossing each other to define the sub-pixels; A drain electrode formed on the substrate and positioned between the pair of source electrodes extending from the sub-data line and the pair of source electrodes to form a "U"-shaped channel; And a pixel electrode formed on the substrate on which the source/drain electrode and the data line are formed, and electrically connected to the drain electrode, and two adjacent sub-data lines are separated from one data line to provide the same data voltage. It is characterized by being approved.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a double rate drive (DRD) structure in which manufacturing costs are reduced by reducing the number of data drive ICs.

In recent years, as society enters the era of full-fledged information, the field of display processing and displaying a large amount of information has rapidly developed.In particular, thin film transistors with excellent performance of light weight, thinness, and low power consumption. TFT) Liquid Crystal Display (LCD) has been developed and is replacing the existing cathode ray tube (CRT).

In particular, an active matrix liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying a dynamic image.

Hereinafter, a structure of a general active matrix liquid crystal display device will be described in detail with reference to the drawings.

1 is a diagram illustrating a structure of a general active matrix type liquid crystal display by way of example.

Referring to FIG. 1, an active matrix type liquid crystal display device includes a liquid crystal panel 1 including a plurality of switching elements T provided at intersections of a plurality of gate lines GL and data lines DL, , The liquid crystal panel 1 converts a digital video signal into an analog signal based on a gamma voltage and supplies it to the data line DL and simultaneously supplies the gate signal to the gate line GL, thereby supplying the data signal to the liquid crystal cell C. ).

Although not shown in detail, the gate electrode of the switching element T is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the switching element T is a liquid crystal cell C. Is connected to the pixel electrode of.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell C through the common line CL. When the gate signal is applied to the gate line GL, the switching element T is turned on to form a channel between the source electrode and the drain electrode to supply the voltage on the data line DL to the pixel electrode of the liquid crystal cell C. do. At this time, the liquid crystal molecules of the liquid crystal cell C are arranged to be changed by the electric field between the pixel electrode and the common electrode to display an image according to incident light.

In this case, the liquid crystal panel 1 of the liquid crystal display is connected to a gate driver 2 for driving a plurality of gate lines GL and a data driver 3 for driving a plurality of data lines DL, and As the display device becomes larger and higher-resolution, the number of integrated circuits (ICs) constituting the required driver increases.

However, since the IC of the data driver 3 is relatively expensive compared to other devices, in recent years, a technology to reduce the number of data drive ICs has been researched and developed to lower the production cost of a liquid crystal display device. Instead of doubling the number of (GL), the number of data lines (DL) is halved, reducing the number of required ICs in half, while implementing the same resolution as the existing double rate drive (DRD). ) The structure is being developed.

2 is a plan view schematically showing a pixel structure of an array substrate for a liquid crystal display device having a general DRD structure.

Referring to FIG. 2, an array substrate for a liquid crystal display device includes a plurality of gate lines Gn-2, Gn-1, Gn, and Gn+1 extending in one direction and formed parallel to each other on the substrate. A plurality of data lines Dm and Dm+1 are formed so as to intersect with -2, Gn-1, Gn, and Gn+1 to define the sub-pixels P1 and P2.

For example, in the first sub-pixel P1, the gate electrode 21 connected to the gate line Gn, the active layer (not shown), the source electrode 22 connected to the data line Dm, and opposite the gate electrode 21 A thin film transistor including a drain electrode 23 forming a "U"-shaped channel is provided.

In addition, the drain electrode 23 of the thin film transistor is connected to the pixel electrode 18 of the first sub-pixel P1 through the contact hole 40.

A common voltage is supplied to the common electrode (not shown) of the first sub-pixel P1 through the common line CL. As described above, when the gate signal is applied to the gate line Gn, the thin film transistor is turned on to form a channel between the source electrode 22 and the drain electrode 23 to supply the voltage on the data line Dm to the first sub. -Supply to the pixel electrode 18 of the pixel P1. At this time, the liquid crystal molecules of the first sub-pixel P1 are arranged to be changed by the electric field between the pixel electrode 18 and the common electrode to display an image according to incident light.

At this time, in the case of the DRD technology, two sub-pixels P1 and P2 existing on a horizontal line are connected to one data line Dm, but each of the two sub-pixels P1 and P2 It is connected to the other gate lines Gn-1 and Gn.

That is, the first and second sub-pixels P1 and P2 are connected to the m-th data line Dm (m is a natural number satisfying 1 ≤ m ≤ M, M is the number of data lines on the liquid crystal display panel). However, the first sub-pixel P1 is connected to the n-th gate line Gn (where n is a natural number satisfying 1≦n≦N, and N is the number of gate lines of the liquid crystal display panel) and the second sub- The pixel P2 is connected to the m-1th gate line Gn-1.

As described above, the DRD technology has an advantage of significantly reducing manufacturing cost because the data drive IC is controlled to supply two pixel data voltages from one data line Dm.

However, in a general DRD structure, the channels in the sub-pixels P1 and P2 are designed in different directions, for example, in the left and right directions, and thus the parasitic capacitance between the sub-pixels P1 and P2 ( parasitic capacitance) deviation occurs.

When the compensation pattern 25 is added to control the fluctuation of the parasitic capacitance due to the distortion of the overlay, the parasitic capacitance increases and the horizontal aperture area decreases. Because of this parasitic capacitance, a voltage shift occurs as much as ΔVp (level-shift voltage or kickback voltage).

In addition, in large inches, the aperture ratio is further reduced due to the contact area 9 reducing the load of the common voltage.

An object of the present invention is to solve the above problem and to provide a liquid crystal display device having a double rate drive (DRD) structure in which the number of data drive ICs is reduced in half.

Another object of the present invention is to provide a liquid crystal display device capable of suppressing the occurrence of parasitic capacitance in a liquid crystal display device having a DRD structure.

In addition, other objects and features of the present invention will be described in the configuration and claims of the invention to be described later.

In order to achieve the above object, a liquid crystal display device according to an exemplary embodiment of the present invention includes a substrate divided into a display area in which a plurality of sub-pixels are arranged in a matrix form and a pad area around the display area; A plurality of gate lines and a plurality of sub-data lines formed on the substrate and crossing each other to define the sub-pixels; A drain electrode formed on the substrate and positioned between the pair of source electrodes extending from the sub-data line and the pair of source electrodes to form a "U"-shaped channel; And a pixel electrode formed on the substrate on which the source/drain electrode and the data line are formed, and electrically connected to the drain electrode, and two adjacent sub-data lines are separated from one data line to provide the same data voltage. It is characterized by being approved.

In this case, the one data line is divided into the two adjacent sub-data lines, and the same data voltage may be applied from the same data driver IC through a link wiring.

The pair of source electrodes may extend from the sub-data line in a direction parallel to the gate line.

In this case, the “U”-shaped channels may all face the same direction in the display area.

In this case, the “U”-shaped channel may be disposed at the same position with respect to one vertical line, and may be disposed in a vertical zigzag for one horizontal line.

M data drive ICs connected to the substrate to supply data voltages to each of the M data lines may be further included.

At this time, the M data lines are connected to 2M sub-data lines, and the m (=1, 2, 3,..., M)-th data line is connected to the 2m-1th and 2m-th sub-data lines. The same data voltage can be applied from the m-th data drive IC.

As described above, in the liquid crystal display device according to the embodiment of the present invention, in the liquid crystal display device of the DRD structure, one data line is divided into two sub-data lines, while channels of all thin film transistors in the display area By designing the direction in one direction, it is characterized in that the DRD structure is maintained and parasitic capacitance fluctuations due to the distortion of the overlay are prevented. Accordingly, since there is no need to form a compensation pattern, the aperture ratio is increased, and the quality is improved by decreasing the ΔVp value.

1 is a diagram illustrating a structure of a general active matrix type liquid crystal display by way of example.
2 is a plan view schematically showing a pixel structure of an array substrate for a liquid crystal display device having a general DRD structure.
3 is a diagram illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a circuit diagram illustrating a pixel array of a liquid crystal display according to an exemplary embodiment of the present invention.
5 is a plan view schematically showing a pixel structure of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 6 is a schematic view showing a cross section taken along line A-A' in the array substrate according to the embodiment of the present invention shown in FIG. 5.
7A to 7E are plan views sequentially showing a manufacturing process of the array substrate according to the embodiment of the present invention shown in FIG. 5.
8A to 8E are cross-sectional views sequentially showing a manufacturing process of the array substrate according to the embodiment of the present invention shown in FIG. 6.

Hereinafter, preferred embodiments of the liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity of description.

When an element or layer is another element or referred to as “on” or “on”, it includes both the case where another layer or other element is interposed in the middle as well as directly above the other element or layer. do. On the other hand, when a device is referred to as "directly on" or "directly on", it indicates that there is no intervening other device or layer in between.

The terms "below, beneath", "lower", "above", "upper", which are spatially relative terms, refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between the and other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, if an element shown in the figure is turned over, an element described as “below” or “beneath” of another element may be placed “above” another element. Accordingly, the exemplary term “below” may include both directions below and above.

The terms used in the present specification are for describing exemplary embodiments, and therefore, are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification, "comprise" and/or "comprising" refers to the presence of one or more other components, steps, actions and/or elements, and/or elements, steps, actions and/or elements mentioned. Or does not exclude additions.

3 is a diagram illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel in which a pixel array 100 is formed in a display area AA, data drive ICs 112, and a timing controller (not shown). do. A backlight unit (not shown) for uniformly irradiating light onto the liquid crystal display panel may be disposed under the liquid crystal display panel.

The liquid crystal display panel includes an upper glass substrate (not shown) and a lower glass substrate 110 facing each other with a liquid crystal layer therebetween.

A pixel array 100 is formed on the liquid crystal display panel. The pixel array 100 displays video data using sub-pixels arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL. In the lower glass substrate 110 of the pixel array 100, data lines DL, gate lines GL, thin film transistors (TFTs) (not shown), and pixel electrodes of sub-pixels connected to the TFT ( (Not shown) and a storage capacitor (not shown) connected to the pixel electrode.

Each of the sub-pixels of the pixel array 100 drives the liquid crystal in the liquid crystal layer by a voltage difference between the pixel electrode charged with the data voltage through the TFT and the common electrode applied with the common voltage to adjust the transmittance of light to obtain an image. Indicate. A detailed structure of the pixel array 100 will be described in detail with reference to FIGS. 4 to 6 below.

Although not shown, a black matrix and a color filter are formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and the same as IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) mode. In the case of the horizontal electric field driving method, it is formed on the lower glass substrate 110 together with the pixel electrode. The liquid crystal display device of the present invention may be implemented in any liquid crystal mode as well as TN mode, VA mode, IPS mode, and FFS mode.

A polarizing plate is attached to each of the upper and lower glass substrates 110 of the liquid crystal display panel, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal display of the present invention may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. In the transmissive liquid crystal display and the transflective liquid crystal display, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The data drive ICs 112 are mounted on a Tape Carrier Package (TCP) 115, bonded to the lower glass substrate 110 of a liquid crystal display panel by a TAB (Tape Automated Bonding) process, and a data PCB (Printed Circuit Board) Connected to (114). The data drive ICs 112 may be bonded to the lower glass substrate 110 of the liquid crystal display panel by a chip on glass (COG) process.

Each of the data drive ICs 112 receives digital video data and a source timing control signal from a timing controller. The data drive ICs 112 convert digital video data into positive/negative data voltages in response to a source timing control signal and supply them to the data lines DL of the pixel array 100. The data drive ICs 112 output data voltages in a column inversion method under the control of a timing controller. The column inversion method refers to a method of supplying data voltages of opposite polarities to neighboring data lines (DL) and maintaining the same polarity of data voltages supplied to each of the data lines (DL) for one frame period. do.

The gate driving circuit 113 receives a gate timing control signal from a timing controller. The gate driving circuit 113 sequentially supplies a gate pulse (or scan pulse) to the gate lines GL of the pixel array 100 in response to a gate timing control signal. The gate driving circuit 113 may be mounted on the TCP and bonded to the lower glass substrate 110 of the liquid crystal display panel by a TAB process. Alternatively, the gate driving circuit 113 may be directly formed on the lower glass substrate 110 at the same time as the pixel array 100 by a GIP (Gate In Panel) process. As shown, the gate driving circuit 113 may be disposed on both sides of the pixel array 100 or may be disposed on one side of the pixel array 100.

Although not shown, the timing controller receives digital video data and timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock from an external system board. The timing controller generates a source timing control signal for controlling the operation timing of the data drive ICs 112 and a gate timing control signal for controlling the operation timing of the gate driving circuit 113 based on digital video data and timing signals. do. The timing controller supplies digital video data and source timing control signals to the data drive ICs 112. The timing controller supplies gate timing control signals to the data drive ICs 112. The timing controller is mounted on the control PCB. The control PCB and the data PCB 114 are connected through a flexible circuit board such as FFC (Flexible Flat Cable) or FPC (Flexible Printed Circuit).

4 is a circuit diagram illustrating a pixel array of a liquid crystal display according to an exemplary embodiment of the present invention.

In this case, in FIG. 4, the m-1th (m is a natural number greater than or equal to 2) to the m+1th data lines Dm-1", Dm', Dm", Dm+1', Dm+1") and the A pixel array including sub-pixels surrounded by n-1 (n is a natural number greater than or equal to 2) th to n+3 th gate lines Gn-1, Gn, Gn+1, Gn+2, Gn+3 An example is shown.

5 is a plan view schematically showing a pixel structure of an array substrate for a liquid crystal display device according to an embodiment of the present invention, and FIG. 6 is a schematic view of the array substrate according to the embodiment of the present invention shown in FIG. It is a diagram schematically showing a cross section cut along line A'.

4 to 6, an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention includes a plurality of gate lines Gn-1, Gn, and Gn extending in one direction and parallel to each other. +1, Gn+2, Gn+3) and gate lines Gn-1, Gn, Gn+1, Gn+2, Gn+3, and a plurality of data lines Dm -1", Dm', Dm", Dm+1', Dm+1") are formed.

The pixel array according to the exemplary embodiment of the present invention has a form in which first and second sub-pixels P1 and P2 are regularly arranged. However, the present invention is not limited thereto.

At this time, the first sub-pixel P1 is connected to the n-th gate line Gn and the m-th data line Dm' through the first TFT T'. The gate electrode 121 ′ of the first TFT T′ is connected to the n-th gate line Gn, the source electrode 122 ′ is connected to the m-th data line Dm′, and the drain electrode ( 123') is connected to the pixel electrode 118' of the first sub-pixel P1 through the first contact hole 140'.

The second sub-pixel P2 is connected to the n+1 th gate line Gn+1 and the m th data line Dm" through a second TFT (T"). The gate electrode 121" of the second TFT (T") is connected to the n+1 th gate line (Gn+1), the source electrode 122" is connected to the m th data line (Dm"). , The drain electrode 123" is connected to the pixel electrode 118" of the second sub-pixel P2 through the second contact hole 140".

In this case, according to an embodiment of the present invention, the m-th data line Dm' of the first sub-pixel P1 and the m-th data line Dm" of the second sub-pixel P2 are the same data driver IC. A DRD structure is formed by receiving the same data voltage from 112 (see Fig. 3), that is, one data line DL is converted into two sub-data lines DL', DL"; Dm', Dm". ) And receiving the same data voltage from the same data driver IC 112 through the link wiring 111, thereby constructing a substantial DRD structure.

The point where one data line (DL) is divided into two sub-data lines (DL', DL"; Dm', Dm") may be a display area as shown in FIG. 3, but the present invention is limited thereto. It is not. In the pad area, one data line DL may be divided into two sub-data lines DL' and DL"; Dm' and Dm".

At this time, the second sub-data lines Dm" and Dm+1" are characterized in that it is possible to prevent a decrease in the aperture ratio by deleting the common line from the existing DRD structure and disposing it in the portion.

As described above, in the pixel array according to the exemplary embodiment of the present invention, two sub-pixels P1 and P2 existing on the same horizontal line are commonly connected to any one data line, but the first and second sub- It is characterized by being connected to the data lines (Dm', Dm+1', Dm", Dm+1").

Further, the two sub-pixels P1 and P2 consecutive in the vertical direction are connected to one of the four consecutive gate lines Gn-1, Gn, Gn+1, and Gn+2. However, the present invention is not limited to the arrangement of the sub-pixels P1 and P2.

For example, in such a pixel array, a red liquid crystal cell to which red data is applied, a green liquid crystal cell to which green data is applied, and a blue liquid crystal cell to which blue data is applied are arranged along a column direction. In this pixel array, one pixel includes adjacent red liquid crystal cells, green liquid crystal cells, and blue liquid crystal cells along a row direction orthogonal to a column direction.

At this time, a pair of liquid crystal cells sharing the same data line are respectively connected to adjacent gate lines Gn-1, Gn, Gn+1, Gn+2, and Gn+3.

According to this structure, for example, a liquid crystal display of a DRD structure minimizes flicker and reduces power consumption by one data line (Dm-1", Dm', Dm", Dm+1) during one frame. When a data signal of the same polarity is applied to', Dm+1"), column inversion may be implemented.

The liquid crystal display according to an embodiment of the present invention configured as described above may be implemented in any liquid crystal mode such as the TN mode, VA mode, IPS mode, or FFS mode described above.

In addition, the present invention can be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display.

Meanwhile, unlike the conventional DRD structure, the first and second TFTs (T', T") according to the embodiment of the present invention are characterized in that the "U"-shaped channel is designed to face the same direction. While maintaining the DRD structure, it is possible to prevent variations in parasitic capacitance due to twisting of the overlay between layers. Therefore, compared to the previous one, the aperture ratio is increased because there is no need to form a compensation pattern, and the quality is improved by a decrease in the ΔVp value. Provides an effect.

That is, in the past, two sub-pixels are arranged for one data line in order to implement the DRD technology, so that channels of adjacent sub-pixels have to be designed in different directions.

However, by dividing one data line into two sub-data lines as in the present invention, and designing the channel direction of all thin film transistors in the display area in one direction, the variation in parasitic capacitance due to distortion of the overlay while maintaining the DRD structure. It can be prevented from occurring.

In this way, since the parasitic capacitance does not vary, the conventional compensation pattern becomes unnecessary, so that the parasitic capacitance can be reduced. This decrease in parasitic capacitance results in a decrease in the value of ΔVp, thereby providing an effect of improving the quality of the liquid crystal display.

For reference, reference numerals 115a and 115b denote a gate insulating layer and a protective layer, respectively.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the drawings.

7A to 7E are plan views sequentially showing a method of manufacturing an array substrate according to the embodiment of the present invention shown in FIG. 5.

In addition, FIGS. 8A to 8E are cross-sectional views sequentially showing a method of manufacturing an array substrate according to the embodiment of the present invention shown in FIG. 6.

7A and 8A, gate electrodes 121 ′ and 121 ″ and gate lines Gn-1, Gn, Gn+1, and Gn+2 on a substrate 110 made of a transparent insulating material such as glass. ) To form.

The gate electrodes 121 ′ and 121 ″ may form part of the gate lines Gn-1, Gn, Gn+1, and Gn+2.

At this time, the gate electrodes 121 ′ and 121 ″ and the gate lines Gn-1, Gn, Gn+1, and Gn+2 are selectively deposited through a photolithography process after depositing a first conductive film on the entire surface of the substrate 110. It is formed by patterning.

The first conductive film is aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), molybdenum alloy, etc. It can be formed of a low-resistance opaque conductive material. In addition, the first conductive layer may be formed in a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIGS. 7B and 8B, a gate is formed on the entire surface of the substrate 110 on which the gate electrodes 121 ′ and 121 ″ and the gate lines Gn-1, Gn, Gn+1, and Gn+2 are formed. An insulating film 115a, an amorphous silicon thin film, and an n+ amorphous silicon thin film are formed.

Thereafter, the amorphous silicon thin film and the n+ amorphous silicon thin film are selectively removed through a photolithography process to form the active layers 124 ′ and 124 ″ made of amorphous silicon thin films on the substrate 110.

In this case, the active layers 124 ′ and 124 ″ may be formed using a polycrystalline silicon thin film or an oxide semiconductor instead of the amorphous silicon thin film.

When the active layers 124 ′ and 124 ″ are formed with an amorphous silicon thin film, an n+ amorphous silicon thin film patterned in substantially the same shape as the active layers 124 ′ and 124 ″ on the active layers 124 ′ and 124 ″ A pattern (not shown) is formed.

Next, as shown in FIGS. 7C and 8C, a second conductive layer is formed on the entire surface of the substrate 110 on which the active layers 124 ′ and 124 ″ and the n+ amorphous silicon thin film pattern are formed.

In this case, the second conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form the source electrode, the drain electrode, and the data line. In addition, the second conductive layer may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

Thereafter, by selectively removing the n+ amorphous silicon thin film and the second conductive film through a photolithography process, the source electrodes 122 ′ and 122 ″ and the drain electrodes 122 ′ and 122 ″ made of the second conductive film on the active layers 124 ′ and 124 ″ and the drain electrode ( 123', 123").

In this case, data lines Dm', Dm", Dm+1', and Dm+1" made of the second conductive layer are formed in the data line region of the substrate 110 through a photolithography process.

The source electrodes 122 ′ and 122 ″ are parallel to the gate lines Gn-1, Gn, Gn+1, Gn+2, and the data lines Dm', Dm", Dm+1', Dm+1 While extending in pairs from "), the drain electrodes 123' and 123" are disposed between the pair of source electrodes 122' and 122" to form a "U" shape together with the source electrodes 122' and 122". You will configure the channel.

In this case, in the embodiment of the present invention, one data line is divided into two sub-data lines (Dm', Dm", Dm+1', Dm+1").

In addition, unlike the conventional DRD structure, the thin film transistor according to the embodiment of the present invention is characterized in that the "U"-shaped channel is designed to face the same direction.

The "U"-shaped channel, that is, the thin film transistor, is arranged at the same position for one vertical line, while vertically zigzag for one horizontal line.

In addition, the active layers 124 ′ and 124 ″ are formed of an n+ amorphous silicon thin film, and the source/drain regions and the source/drain electrodes 122 ′, 122 ″ and 123 ′ of the active layers 124 ′ and 124 ″, 123"), an ohmic-contact layer (not shown) for ohmic-contacting is formed.

However, the present invention is not limited thereto, and the active layers 124', 124", source/drain electrodes 122', 122", 123', 123", and data lines Dm', Dm", and Dm+ 1', Dm+1") can be formed through the same mask process.

Thereafter, as shown in FIGS. 7D and 8D, source/drain electrodes 122', 122", 123', 123" and data lines Dm', Dm", Dm+1', Dm+1") A protective film 115b is formed on the entire surface of the formed substrate 110.

In this case, the protective layer 115b may be formed of an inorganic insulating layer such as a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ), or an organic insulating layer such as photoacrylic.

Thereafter, by selectively removing the protective layer 115b through a photolithography process, contact holes 140 ′ and 140 ″ exposing portions of the drain electrodes 123 ′ and 123 ″ are formed.

Next, as shown in FIGS. 7E and 8E, after forming a third conductive film on the entire surface of the substrate 110 on which the protective film 115b is formed, the third conductive film is selectively removed through a photolithography process to form a third conductive film on the substrate 110. Pixel electrodes 118' and 118' made of a conductive film are formed.

In this case, the third conductive layer is a transparent layer having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form the pixel electrodes 118' and 118'. It can be formed of a conductive material.

The pixel electrodes 118 ′ and 118 ″ are electrically connected to the drain electrodes 123 ′ and 123 ″ through the contact holes 140 ′ and 140 ″.

The array substrate according to the embodiment of the present invention configured as described above is bonded to face the color filter substrate by the sealant formed on the outer edge of the image display area, and at this time, the color filter substrate has colors for realizing red, green, and blue colors. A filter is formed.

In this case, the bonding of the color filter substrate and the array substrate is performed through the bonding key formed on the color filter substrate or the array substrate.

The present invention can be used not only for a liquid crystal display, but also for other display devices manufactured using a thin film transistor, for example, an organic light emitting display device in which organic light emitting diodes (OLEDs) are connected to a driving transistor.

Although many items are specifically described in the above description, this should be construed as an example of a preferred embodiment rather than limiting the scope of the invention. Accordingly, the invention should not be determined by the described embodiments, but should be defined by the claims and equivalents to the claims.

118',118": pixel electrode 121',121": gate electrode
122',122": source electrode 123',123": drain electrode
Dm',Dm",Dm+1',Dm+1": Data line
Gn-1,Gn,Gn+1,Gn+2: gate line

Claims (7)

A substrate divided into a display area in which a plurality of sub-pixels are arranged in a matrix form and a pad area around the display area;
A plurality of gate lines and a plurality of sub-data lines formed on the substrate and crossing each other to define the sub-pixels;
A pair of source electrodes formed on the substrate and extending from the sub-data line in a direction parallel to the gate line and a “U” along with the pair of source electrodes are positioned between the pair of source electrodes. A drain electrode forming a shaped channel; And
And a pixel electrode formed on a substrate on which the source/drain electrodes and data lines are formed, and electrically connected to the drain electrode,
Two neighboring sub-data lines are separated from one data line to receive the same data voltage,
The "U"-shaped channels are all arranged to face the same direction in the display area. The liquid crystal display of claim 1, wherein the one data line is divided into two adjacent sub-data lines to receive the same data voltage from the same data driver IC through a link wiring. delete delete The liquid crystal display device of claim 1, wherein the “U”-shaped channels are disposed at the same position with respect to one vertical line and vertically zigzag with respect to one horizontal line. The liquid crystal display of claim 1, further comprising M data drive ICs connected to the substrate to supply data voltages to each of the M data lines. The method of claim 6, wherein the M data lines are connected to 2M sub-data lines, and the m (=1, 2, 3, .., M)-th data line is 2m-1th, 2m-th sub-data A liquid crystal display connected to the line and receiving the same data voltage from the m-th data drive IC.

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