KR101946927B1 - Array substrate for lcd and fabricating method of the same - Google Patents

Abstract

The present invention discloses an array substrate for a liquid crystal display device. More particularly, the present invention relates to an array substrate for a DRD structure AH-IPS mode liquid crystal display device in which the aperture ratio is improved by changing the pixel structure, and a manufacturing method thereof.
An array substrate for a liquid crystal display according to an embodiment of the present invention includes a plurality of gate wirings and intersecting data wirings formed in one direction on a substrate, And a thin film transistor in which pixel electrodes respectively formed in the first and second regions, and neighboring data lines and source electrodes are electrically connected to each other. A common wiring is formed so as to be in electrical contact with the common electrode and the common electrode facing the pixel electrode and between the first and second regions. And a pixel electrode connection pattern electrically connecting the drain electrode of the thin film transistor of the first region and the pixel electrode of the second region.
Accordingly, the connection pattern of the pixel electrode of each pixel is formed and electrically connected to the thin film transistor of the neighboring pixel, so that the common wiring provided in the other layer is formed in the vertical direction between the respective pixels to improve the aperture ratio of the liquid crystal display device .

Description

Technical Field [0001] The present invention relates to an array substrate for a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display, and more particularly, to an array substrate for a DRD structure AH-IPS mode liquid crystal display device having an improved aperture ratio by changing a pixel structure and a manufacturing method thereof.

2. Description of the Related Art [0002] With the development of information devices such as potable devices such as mobile phones and notebook computers and high-resolution and high-quality images such as HDTVs, flat panel displays Display Device) is increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix type liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying dynamic images.

FIG. 1 schematically shows a structure of a conventional active matrix type liquid crystal display device. The active matrix type liquid crystal display device includes a plurality of switching elements provided at intersections of a plurality of gate lines GL and data lines DL, The liquid crystal panel 1 converts a digital video signal into an analog signal on the basis of a gamma voltage and supplies the analog signal to the data line DL, To the liquid crystal cell GL, thereby filling the liquid crystal cell C with the data signal.

Specifically, the gate electrode of the switching element T is connected to the gate wiring GL, the source electrode thereof is connected to the data line DL, and the drain electrode of the switching element T is connected to the gate electrode of the liquid crystal cell C And is connected to one electrode of the pixel electrode. A common voltage Vcom is supplied to the common electrode of the liquid crystal cell C through the common line CL. When a gate signal is applied to the gate line GL, a switching element is turned on to form a channel between the source electrode and the drain electrode to supply a voltage on the data line DL to the pixel electrode of the liquid crystal cell C. At this time, the liquid crystal molecules of the liquid crystal cell C are arranged by the electric field between the pixel electrode and the common electrode, and an image corresponding to the incident light is displayed.

Here, the TN mode or the IPS mode, which is the drive mode of the liquid crystal display, is determined depending on the positions of the common electrode and the pixel electrode of the liquid crystal panel 1. In particular, the common electrode and the pixel electrode are arranged in parallel on one substrate, The IPS mode for forming an electric field is advantageous in that the common electrode and the pixel electrode are arranged so as to oppose different substrates and have a wider viewing angle than a TN mode in which a vertical electric field is formed.

Recently, an AH-IPS (Advanced High-IPS) mode in which the above-described IPS mode is improved to maximize the luminance characteristic has been proposed. In the AH-IPS mode, a common electrode and a pixel electrode are arranged on different substrates in a staggered manner to form a fringe field, thereby realizing a higher image quality improvement characteristic than IPS.

Such an AH-IPS mode liquid crystal display device is formed in the same layer as the gate wiring GL of the liquid crystal panel 1, the common wiring CL and the pixel electrode in one mask process using a halftone mask.

The liquid crystal panel 1 of the liquid crystal display device is connected to a gate driver 2 for driving a plurality of gate lines GL and a data driver 3 for driving a plurality of data lines DL, As the size and resolution of a liquid crystal display device are increased, the number of ICs forming a required driving part is increasing.

Since the IC of the data driver 3 is relatively much more expensive than other devices, a technology capable of reducing the number of ICs has been recently developed to lower the production cost of a liquid crystal display device. A DRD (Double Rate Driving) structure that reduces the number of data lines (DLs) by a factor of two to reduce the number of ICs required by half, while realizing the same resolution as a conventional one, instead of doubling the number of wiring lines GL It was proposed.

2 is a diagram showing the pixel structure of the DRD structure liquid crystal display device.

As shown in the drawing, the DRD structure liquid crystal display device has a structure in which a plurality of pixels P1 and P2 arranged on one horizontal line are connected to two gate lines GL1 and GL2 and one data line DL2, A plurality of pixels P3 and P4 arranged on the horizontal line are connected to the two gate lines GL3 and GL4 and the data line DL2. For example, the liquid crystal display device of the DRD structure can refer to Application No. 10-2007-0121738.

According to such a structure, when a data signal of the same polarity is applied to one data line during one frame in order to minimize flicker and reduce power consumption, Z-inversion) is implemented.

However, when the AH-IPS mode is applied to the DRD structure liquid crystal display device having such a structure, the gate wiring GL and the common wiring CL described above are formed in the same layer, And is disposed between the wiring GL2 and the other gate wiring GL3. The same applies to the gate lines GL4 and GLn of the next line.

3 is a plan view showing a part of an array substrate for a conventional DRD structure AH-IPS mode liquid crystal display device.

As shown in the figure, an array substrate of a conventional DRD structure AH-IPS mode liquid crystal display comprises a plurality of gate wirings 13a and 13a 'formed on a substrate 11 and extending in one direction and formed parallel to each other, A plurality of data wirings 23a which are arranged so as to intersect the pixel electrodes 13a and 13a 'and define pixel regions are formed. A thin film transistor T including a gate electrode 13b, an active layer (not shown), a source electrode 23c and a drain electrode 23d connected to the extension wiring 23b of the data line 23a is formed in the pixel region Respectively.

Transparent pixel electrodes 15a and 15c are disposed on the front surface of the pixel region with a space separated from the gate wiring 13a and the data wiring 23a. An insulating film (not shown) is formed on the pixel electrodes 15a and 15c Shaped transparent common electrodes 29a are disposed with a space therebetween.

The pixel electrode 15c is electrically connected by the pixel electrode connection pattern 29d connected to the drain electrode 23d.

Further, the common electrode connection pattern 29b is electrically connected to the common electrode connection pattern 29b extending in the vertical direction across the pixel region of the plurality of rod-shaped common electrodes 29a, and the common electrode connection pattern 29b is electrically connected to the contact hole 29c And the common wiring 13c arranged in parallel with the gate wiring 13a.

Here, the common wiring 13c is formed between the gate wirings 13a and 13a 'in the horizontal direction together with the extended wirings 23b of the data wirings. This is because, in accordance with the DRD structure, two pixels are connected to one data line in one horizontal line and gate wirings 13a and 13a 'and common wirings 13c are formed on the same layer and the common wiring can not be formed in the vertical direction.

According to this structure, in the conventional DRD structure AH-IPS mode liquid crystal display device, the common wiring 13c is arranged horizontally between the upper and lower pixel intervals, and the extended wiring 23b of the data wiring is also horizontally The data extension wiring 23b and the common wiring 13c are continuously arranged in the horizontal direction in addition to the gate wirings 13a and 13a 'in the horizontal region of the pixel region, thereby lowering the aperture ratio of the liquid crystal panel.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device having a structure in which one data line is shared on the same horizontal line, And an object of the present invention is to provide an array substrate for an IPS mode liquid crystal display.

In order to achieve the above object, an array substrate for a DRD structure AH-IPS mode liquid crystal display according to a preferred embodiment of the present invention includes: a substrate; A plurality of gate wirings formed on the substrate in one direction; A plurality of data lines crossing the gate lines; A pixel region defined as a first region and a second region at an intersection of the gate and the data line; A thin film transistor in which pixel electrodes respectively formed in the first and second regions and adjacent data lines and source electrodes are electrically connected; A protection layer formed on the entire surface of the substrate including the pixel region; A common electrode formed on the protective film and facing the pixel electrode; A common wiring which is in electrical contact with the common electrode and is formed so as to pass between the first and second regions; And a pixel electrode connection pattern electrically connecting the drain electrode of the thin film transistor of the first region and the pixel electrode of the second region.

And the gate electrode has at least a double structure including a transparent conductive film in a lower portion.

And the pixel connection pattern is formed on the same layer as the transparent conductive film.

And the common wiring is formed on the same layer as the data wiring.

And the common wiring is electrically connected to the common electrode by a first contact hole formed between the spacing spaces between the pixels.

The pixel electrode connection pattern is characterized in that the thin film transistor and the pixel electrode are electrically connected to each other perpendicularly to the common wiring.

And the pixel electrode connection pattern is electrically connected to the common electrode through a second contact hole formed at the same time as the first contact hole.

In order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display according to a preferred embodiment of the present invention includes: a pixel region defined as first and second regions at intersections of a gate and a data line; A thin film transistor in which a pixel electrode and a data line adjacent to each other are electrically connected to a source electrode and a pixel electrode respectively formed in a first region and a second region, a pixel electrode electrically connecting the thin film transistor of the first region and the pixel electrode of the second region, A method of manufacturing an array substrate for an AH-IPS mode liquid crystal display device having a connection pattern, the method comprising the steps of: forming on a substrate a gate wiring having at least a double structure of a metal film and a transparent conductive film in one direction, ; Forming a thin film transistor, a data wiring, and a common wiring by depositing and patterning an insulating film, an amorphous silicon film, an amorphous silicon film doped with impurities, and a metal film over the entire surface of the substrate; Forming a protective film on the entire surface of the substrate on which the thin film transistor, the data wiring, and the common wiring are formed; Forming a contact hole exposing the pixel electrode connection pattern and the common wiring; And forming a common electrode by depositing and patterning a transparent conductive film on the entire surface of the substrate including the contact hole and electrically contacting the thin film transistor with the pixel electrode connection pattern and the common wiring with the common electrode.

The step of forming the gate wiring, the pixel electrode, and the pixel electrode connection pattern may include: forming a transparent conductive film, a metal film, and a photoresist film on the substrate; The photoresist film is selectively removed through a diffraction mask to form a photoresist pattern on the gate wiring, a region where a gate electrode extending from the gate wiring is to be formed, and a metal film pattern on a region where the pixel electrode and the pixel electrode connection pattern are to be formed ; Forming the pixel electrode and the pixel electrode connection pattern using the photoresist pattern and the metal film pattern as a mask; And removing the photoresist pattern to form the gate wiring and the gate electrode.

The forming of the thin film transistor, the data wiring, and the common wiring may include depositing an insulating film, an amorphous silicon film, an amorphous silicon film doped with an impurity, and a metal film over the entire surface of the substrate on which the gate wiring, the pixel electrode, step; Forming a photoresist pattern on a region where the thin film transistor is to be formed and on a region where the data wiring and the common wiring are to be formed using a diffraction mask; And forming the thin film transistor, the data wiring, and the common wiring using the photoresist pattern as a mask.

According to a preferred embodiment of the present invention, a connection pattern of pixel electrodes of each pixel is formed and electrically connected to a thin film transistor of a neighboring pixel, so that a common wiring provided in another layer can be formed in a vertical direction between each pixel . Thus, the aperture ratio of the AH-IPS mode liquid crystal display device of the DRD structure can be improved.

1 is a view schematically showing the structure of a conventional active matrix type liquid crystal display device.
2 is a diagram showing the pixel structure of the DRD structure liquid crystal display device.
3 is a plan view showing a part of an array substrate for a conventional DRD structure AH-IPS mode liquid crystal display device.
FIG. 4A is a plan view of an array substrate for an AH-IPS mode liquid crystal display of a DRD structure according to an embodiment of the present invention, and FIG. 4B is an enlarged view of a portion of FIG. 4A.
5 is a cross-sectional view of the array substrate shown in FIG. 4B taken along line VV 'and VI-VI'.
6A to 6M are cross-sectional views illustrating manufacturing steps of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an embodiment of the present invention.

Hereinafter, a structure of an array substrate for an AH-IPS mode liquid crystal display device having a DRD structure according to a preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 4A is a plan view of an array substrate for an AH-IPS mode liquid crystal display of a DRD structure according to an embodiment of the present invention, and FIG. 4B is an enlarged view of a portion of FIG. 4A.

As shown in the drawing, the array substrate for the AH-IPS mode liquid crystal display of the DRD structure of the present invention comprises a pair of adjacent pairs formed in parallel in one direction on a substrate 111, And a plurality of data wirings 123a which are arranged so as to intersect the plurality of pairs of gate wirings 103a and define pixel regions are formed. The first region P1 and the second region P2 are divided and operated on both sides of the common wiring connection pattern 129c in the center vertical direction in each pixel region, The thin film transistor T is turned on. That is, in the array substrate for the liquid crystal display of the DRD structure AH-IPS of the present invention, the pair of gate wirings 103a adjacent to the upper and lower portions of the pixel rows (the horizontal direction) And the data line 123a is arranged for each of the two pixels. In each of the regions P1 and P2, a gate electrode 103b, an active layer (see 109a in FIG. 5), a source electrode 123b extending from the data line 123a, and a drain electrode 123c (T). A transparent pixel electrode 115a is disposed on the front surface opposite to the first area P1 and the second area P2 with a space separated from the gate wiring 103a and the data wiring 123a, A plurality of rod-shaped transparent common electrodes 129a are disposed on the upper portion of the electrode 115a with an insulating film (see the gate insulating film 107 and the protective film 119 in Fig. 5) interposed therebetween. 4B and 4B show a state in which the rod-shaped transparent common electrodes 129a are arranged at a slight inclination from the horizontal direction and are connected to each other at the edge of the common electrode 129a, and as a result, between the plurality of common electrodes 129a Indicates a point having a slit. The pixel electrode 115a overlaps the common electrode 129a and is provided in the first region P1 and the second region P2, respectively.

The pixel electrode connection pattern 115b integrated with the pixel electrode 115a and extending from the pixel electrode 115a and intersecting the first region P1 is connected in the second region P2 adjacent to the drain electrode 123c described above have. In the same manner, the drain electrode 123c of the second region P2 is also integrated with the pixel electrode 115a in the adjacent first region P1 and extends from the pixel electrode 115a in the second region P2, The pattern 115b is connected. The first region P1 and the second region P2 are connected to a pair of gate wirings 103a and a common wiring connection pattern 129c in the center vertical direction in the pixel region defined by the data wirings 123a ). ≪ / RTI > That is, the pixel electrode connection pattern 115b in the second region P2 is formed integrally with the pixel electrode 115a in the second region P2 and extends to the neighboring first region, And extends to the drain electrode 123c of the thin film transistor T and is electrically connected to the thin film transistor T. In the same manner, the pixel electrode 115a of the first region P1 is electrically connected to the thin film transistor T of the crossed second region.

That is, the pixel electrode 115a of each pixel is electrically connected to the thin film transistor of the adjacent region, not the nearest thin film transistor, through the pixel electrode connection pattern 115b.

A plurality of rod-shaped common electrodes 129a are formed to be connected to each other between the pixels P1 and P2. In the figure, the long axis of the rod shape is formed in the transverse direction, that is, in a direction parallel to the gate wiring 103a However, the common electrode may be formed in the longitudinal direction so that the common electrode and the data wiring are parallel to each other.

4B shows an integral common wiring connection pattern 129c vertically disposed to the gate wiring 103a at the center of the common electrode 129a which is the boundary between the first area P1 and the second area P2. Passes through the upper portion of the gate wiring 103a and is in electrical contact with the common wiring 129b through the common wiring contact hole 121b (see FIG. 6K) located between the upper and lower pixels. The common wiring 129b is provided on the same layer as the data wiring 123a and overlaps with the common wiring connection pattern 129c to apply an electrical signal to the common electrode 129a. According to this structure, a common wiring connection pattern 129c in the vertical direction overlapping the data wiring 123a is formed between two adjacent regions P1 and P2 sharing the common electrode 129a, and the data wiring 123a The common wiring 129b formed on the same layer as the common wiring 129a can be disposed in the vertical direction and the common wiring 129b can be formed in the common wiring connection pattern 129c in the vertical direction, It is possible to improve the aperture ratio by removing the common wiring in the horizontal direction which should have the horizontal spacing space between the electrodes. The common electrode 129a and the common wiring connection pattern 129c are the same layer and the common wiring 129b is disposed on the other layer so that the overlapping configuration of the common wiring connection pattern 129c and the common wiring 129b It is possible.

In addition, when a data signal of the same polarity is applied to one data line during one frame, it operates in a column Z-inversion mode and is driven at a low power. Hereinafter, the structure of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an embodiment of the present invention will be described with reference to cross-sections of the array substrate shown in Figs. 4A and 4B.

5 is a cross-sectional view taken along line V-V 'and VI-VI' of the array substrate shown in FIG. 4B.

As shown in the figure, the array substrate for the AH-IPS mode liquid crystal display with the DRD structure includes a gate electrode 103b integrally connected to the gate wiring 103a, and a gate electrode 103b connected to the active layer 109a, the source electrode 123b, 123c are stacked in this order.

Here, a transparent conductive layer pattern 105a composed of a transparent conductive material, for example, ITO, is formed below the gate wiring 103a and the gate electrode 103b extending from the gate wiring 103a, It accomplishes. At this time, the transparent conductive layer pattern 105a may be formed on the whole or a part of the lower portion of the gate wiring 103a including the gate electrode 103b.

A transparent pixel electrode 115a in the form of a plate is disposed on the same layer as the gate electrode 103b in the pixel region adjacent to the thin film transistor T by a predetermined distance and a gate insulating film 107 is formed on the pixel electrode 115a, And a plurality of rod-like transparent common electrodes 129a overlapping each other with a protective film 119 interposed therebetween. At this time, the plurality of transparent common electrodes 129a in the form of a bar are spaced apart from each other by a predetermined distance, and are formed in a horizontal or vertical direction. The shape shown in Fig. 4B is a horizontal direction, and slits slanted at an acute angle in the horizontal direction are provided between the bar-shaped common electrodes 123a in the horizontal direction.

The pixel electrode 115a is laterally contacted with the drain electrode 123c of the thin film transistor T through the protective film 119 and the pixel electrode contact hole 121a-see Fig. 6k formed in the gate insulating film 107 And is electrically connected to the pixel electrode connection pattern 129e. The pixel electrode connection pattern 115b is provided below the pixel electrode contact hole 121a and the triple connection of the drain electrode 123c, the pixel electrode connection pattern 129e and the pixel electrode connection pattern 115b. And a signal can be applied to the pixel electrode 115a of the adjacent second region P2 in which the pixel electrode connection pattern 115b extends integrally (see FIG. 4B). The pixel electrode contact hole may be provided so as to expose the upper portion of the drain electrode 123c in addition to the configuration that is laterally connected to the drain electrode 123c so that the pixel electrode contact pattern can be connected to the pixel electrode connection pattern 129e.

Between the first and second regions P1 and P2 between the left and right regions P1 and P2 is formed a common wiring connection pattern 129c integrated with the common electrode 129a formed on the protection film 119 and a data metal, A common wiring 129b is formed which is in contact with the common wiring connection pattern 129c through contact holes (Figs. A gate insulating film 107, an active pattern 109b, and an ohmic contact pattern 111b are sequentially stacked below the common wiring 129b.

In addition, both ends of the plurality of rod-shaped common electrodes 129a are electrically connected to the common electrode connection pattern 129c arranged in parallel with the data lines. The common electrode connection pattern 129c is electrically connected to the common wiring 129b which is arranged in the vertical direction and is applied with a common voltage signal through the contact hole 121b and is electrically connected to the common electrodes 129a, And supplies the reference voltage for liquid crystal driving, that is, the common voltage Vcom, to the common electrode 129a of each pixel.

The pixel electrode 115a overlaps the plurality of common electrodes 129a with a protective film 119 interposed therebetween to form a fringe field in each pixel region. At this time, a storage capacitance Cst is formed at the overlapping portion of the large-area pixel electrode 115a and the plurality of common electrodes 129a.

When the data signal is supplied to the pixel electrode 115a through the thin film transistor T, the common electrodes 129a to which the common voltage is supplied form a fringe field, Liquid crystal molecules arranged in the horizontal direction are rotated by dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

Hereinafter, a method of manufacturing an array substrate for an AH-IPS mode liquid crystal display with a DRD structure according to an embodiment of the present invention will be described with reference to the drawings.

6A to 6M are cross-sectional views illustrating manufacturing steps of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an embodiment of the present invention.

First, as shown in FIG. 6A, a plurality of pixel regions including a switching region are defined on a transparent substrate 101, a transparent conductive material layer 105 and a first conductive metal layer 103 are formed by a conventional sputtering method Lt; / RTI > At this time, the transparent conductive layer 105 may be formed of any one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), and carbon nanotubes (CNT). As the metal used for the first conductive metal layer 103, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten , Moly titanium (MoTi), and copper / moly titanium (Cu / MoTi).

Next, a first photoresist is coated on the first conductive metal layer 103, and then the first photoresist is exposed and developed through a photolithography process using a first exposure mask, Resist patterns 106a and 106b are formed.

At this time, the first photoresist pattern is formed using a diffraction mask including a light shielding portion, a transflective portion, and a transmissive portion. The light shielding portion is disposed so as to correspond to the gate electrode formation region, And then the exposure and development steps are performed to form the shape as shown in FIG. 6B. Therefore, a halftone mask or the like may be used as the first exposure mask.

6C, the first photoresist pattern is selectively removed through a developing process to form a photoresist pattern of the gate formation region 106a and a photoresist pattern of the pixel electrode and the pixel electrode connection pattern formation region 106. [ Thereby forming a metal layer on the surface 103e.

6D, using the remaining photoresist pattern and the metal layer on the pixel electrode and the pixel electrode connection pattern formation region 103e as masks, a gate electrode (not shown) The transparent pixel electrode 115a and the pixel electrode connection pattern 115b under the gate electrode 103b and the gate electrode 103b are formed at the same time.

Thus, the gate wiring and the gate electrode 103b and the lower transparent conductive layer pattern 105a are formed simultaneously with the large-area pixel electrode 115a. At this time, the pixel electrode 105b is arranged on the unit pixel region. Here, the unit pixel region is divided into a first region and a second region.

6E, a gate insulating film 107 made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate including the pixel electrode 115a and the pixel electrode connecting pattern 115b , An amorphous silicon layer (n + or p +) 111 and a second conductive metal layer 113 containing an impurity are sequentially stacked on the gate insulating film 107 .

At this time, the amorphous silicon layer (a + Si or H +) 111 containing impurities is deposited by chemical vapor deposition (CVD) (113) is deposited by a sputtering method. At this time, as the second conductive metal layer 113, a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoTi) and copper / moly titanium (Cu / MoTi).

Next, as shown in FIG. 6F, a second photoresist film 115 is formed by applying a high-transmittance photoresist over the second conductive metal layer 113.

The third photoresist film 115 is then subjected to an exposure process by using a third exposure mask 117 composed of a light shielding portion 117a, a transflective portion 117b and a transmissive portion 117c. At this time, the light shielding portion 117a of the diffraction mask 117 is located above the third photoresist film 115 corresponding to the source and drain electrode formation regions, and the transflective portion 117b of the diffraction mask 117 is located on the thin film And is located above the third photoresist film 115 corresponding to the channel forming region of the transistor.

Here, the illustrated second exposure mask 117 may be a diffraction mask using a diffraction effect of the above-described light, for example, a halftone mask or another mask.

 Next, as shown in FIG. 6G, the third photoresist film 115 is etched to form the source and drain electrode formation regions 125a and the channel formation regions 125b by progressing the exposure process and the development process. At this time, since the source and drain electrode formation regions 125a are in a state in which light is not transmitted, the thickness of the third photoresist film 115 is maintained as it is. However, a part of the light is transmitted through the channel formation region 125b, . That is, the channel forming region 125b has a thickness thinner than the source and drain electrode forming regions 125a.

Next, using the photoresist film on the source and drain electrode formation regions 125a and the channel formation regions 125b as masks, the second conductive metal layer 113, the amorphous silicon layer 111 containing impurities and the amorphous silicon layer 109 are sequentially patterned to form an active layer 109a and an ohmic contact layer 111a on the gate insulating film 107 corresponding to the gate electrode 103b.

At this time, the active pattern 109b and the ohmic contact pattern 111b are also formed in the region where the common wiring is formed.

Then, as shown in 6h, the channel forming region 125b is completely removed together with a part of the thickness of the source and drain electrode forming regions 125a through an ashing process. At this time, the upper surface of the second conductive metal layer 113 overlapping the channel region is exposed to the outside.

Next, as shown in FIG. 6I, the exposed portions of the second conductive metal layer 113 are etched using the source and drain electrode formation regions 125a of the third photoresist film having a part of the thickness removed as a mask, A source electrode 123b and a drain electrode 123c spaced apart from each other are formed with data lines (not shown) perpendicularly intersecting the wiring (see 103a in FIG. 4B). At the same time, a common wiring 129b is also formed.

Then, the ohmic contact layer 111a exposed between the source electrode 123b and the drain electrode 123c is also etched away from each other. At this time, a channel region is formed in the active layer 109a under the etched ohmic contact layer 111a.

Next, as shown in FIG. 6J, after the source and drain electrode formation regions 125a of the third photoresist film are completely removed, an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate to form a protective film 119 A photo-resist having a high transmittance is applied on the protective film 119 to form a fourth photoresist film (not shown).

Then, although not shown in the drawing, the fourth photoresist film 119 is removed by performing the exposure and development processes by the photolithography process technique using the third exposure mask to form the fourth photoresist film pattern.

Next, as shown in FIG. 6K, using the fourth photoresist film pattern (not shown) as a mask, the protective film 119 and the gate insulating film 107 thereunder are selectively etched to expose the pixel electrode 115a A pixel electrode contact hole 121a exposing the pixel electrode connection pattern 115b and a common wiring contact hole 121b exposing the upper portion of the common wiring 129b are formed at the same time. At this time, when forming the pixel electrode contact hole 121a, the side of the drain electrode 123b is also exposed.

Subsequently, the fourth photoresist film pattern is removed and an ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or the like is formed on the protective film 119 including the pixel electrode contact hole 121a and the common wiring contact hole 121b. The second transparent conductive layer 123 is deposited by sputtering using any one selected from the group consisting of carbon nanotubes (CNTs).

Next, although not shown in the drawing, a photo-resist having a high transmittance is coated on the second transparent conductive material layer 123 to form a fifth photoresist film (not shown).

Subsequently, although not shown in the drawing, the fifth photoresist film (not shown) is removed by performing the exposure and development processes by a photolithography process technique using a fourth exposure mask (not shown) (Not shown).

6M, the second transparent conductive layer 123 is etched using the fifth photoresist film pattern (not shown) as a mask to form a plurality of common electrodes 129a, Connected to the pixel electrode 115a of the adjacent region through the contact hole 121a (when the pixel electrode contact hole 121a is in the first region, the electrical connection is with the pixel electrode of the adjacent second region) A pixel electrode connection pattern 129e electrically connected to the electrode connection pattern 115b is formed. A common wiring connection pattern 129c electrically connected to the common wiring 129b is formed on the common wiring 129b through the common wiring contact hole 121b at the same time.

Next, although not shown in the drawing, the fifth photoresist film pattern (not shown) is removed to complete the manufacturing process of the array substrate for the AH-IPS mode liquid crystal display of the DRD structure according to the present invention.

Although not shown in the drawing, a process of filling the liquid crystal layer between the array substrate and the color filter substrate together with the color filter substrate manufacturing process is performed to complete the DRD structure AH-IPS mode liquid crystal display device according to the present invention.

Therefore, according to the present invention, in the array substrate for the AH-IPS mode liquid crystal display of the DRD structure, the connection patterns of the pixel electrodes are connected to the thin film transistors adjacent to the adjacent pixels so that the common wiring is formed in the vertical direction Thus, it is possible to increase the aperture ratio of the liquid crystal display device by removing the common wiring in the space between the upper and lower pixels.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the claims and the appended claims.

103a: gate wiring 103b: gate electrode
115a: pixel electrode 115b: pixel electrode connection pattern
121a: pixel electrode contact hole 121b: common wiring contact hole
123a: Data Wiring
123b: source electrode 123c: drain electrode
129a: common electrode
129b: common wiring 129c: common wiring connection pattern
T: thin film transistor

Claims (12)

Board;
A plurality of pairs of gate wirings having adjacent pairs on the substrate, the pair of wirings being spaced apart from each other by a predetermined distance and arranged in one direction;
A plurality of data lines crossing the plurality of pairs of gate wirings and defining pixel regions;
First and second regions dividedly provided in the pixel region;
A pixel electrode and a thin film transistor provided in the first and second regions, respectively;
A protection layer formed on the entire surface of the substrate including the pixel region;
A common electrode formed on the protective film and facing the pixel electrode; And
And a common wiring connection pattern formed integrally with the common electrode and passing between the first and second regions,
Wherein the thin film transistor of the first region is electrically connected to the pixel electrode of the second region by a first pixel electrode connection pattern crossing the common wiring connection pattern. The method according to claim 1,
The gate electrode
And a transparent conductive film provided on the lower portion of the substrate. 3. The method of claim 2,
Wherein the first pixel electrode connection pattern is formed on the same layer as the transparent conductive film. The method according to claim 1,
And a common wiring is formed on the same layer as the data wiring, overlapping the common wiring connection pattern. 5. The method of claim 4,
Wherein the common wiring connection pattern is electrically connected to the common wiring by a first contact hole between the first region and the second region.
delete 6. The method of claim 5,
Wherein the first pixel electrode connection pattern electrically connects a drain electrode of the thin film transistor of the first region and a pixel electrode of the second region by a second contact hole formed simultaneously with the first contact hole And a plurality of pixel electrodes formed on the substrate. A pixel electrode and a thin film transistor each having a first region and a second region formed in the pixel regions defined by intersecting the plurality of pairs of gate wirings and a plurality of data wirings and respectively formed in the first and second regions, A manufacturing method of an array substrate for a display device,
Forming the gate wiring, the pixel electrode and the first pixel electrode connection pattern having at least a double structure of a metal film and a transparent conductive film in one direction on a substrate;
Depositing and patterning an insulating film, an amorphous silicon film, an amorphous silicon film doped with impurities, and a metal film over the entire surface of the substrate to form the thin film transistor, the data wiring, and the common wiring;
Forming a protective film on the entire surface of the substrate on which the thin film transistor, the data wiring, and the common wiring are formed;
Forming a first contact hole exposing the common wiring; And
Forming a common electrode overlapping the pixel electrode by depositing and patterning a transparent conductive film on the entire surface of the substrate including the first contact hole and simultaneously forming the common electrode between the first and second regions And forming a common wiring connection pattern that overlaps the wiring and is electrically connected to the common wiring through the first contact hole. 9. The method of claim 8,
Wherein the forming of the gate wiring, the pixel electrode, and the pixel electrode connection pattern comprises:
Forming a transparent conductive film, a metal film, and a photoresist film on a substrate;
The photoresist film is selectively removed through a diffraction mask to form a photoresist pattern on the gate wiring, a region where a gate electrode extending from the gate wiring is to be formed, and a metal film pattern on a region where the pixel electrode and the pixel electrode connection pattern are to be formed ;
Forming the pixel electrode and the pixel electrode connection pattern using the photoresist pattern and the metal film pattern as a mask; And
And removing the photoresist pattern to form the gate wiring and the gate electrode. 9. The method of claim 8,
The step of forming the thin film transistor, the data wiring, and the common wiring may include:
Depositing an insulating film, an amorphous silicon film, an amorphous silicon film doped with an impurity, and a metal film over the entire surface of the substrate on which the gate wiring, the pixel electrode, and the pixel electrode connection pattern are formed;
Forming a photoresist pattern on a region where the thin film transistor is to be formed and on a region where the data wiring and the common wiring are to be formed using a diffraction mask; And
And forming the thin film transistor, the data wiring, and the common wiring using the photoresist pattern as a mask. The method according to claim 1,
Wherein the thin film transistor of the second region is integrated with the pixel electrode of the first region and extends therefrom to cross the common wiring to be in contact with the second thin film transistor in the second region, And is electrically connected to the pixel electrode of the first region. 9. The method of claim 8,
The second contact hole exposing the first pixel electrode connection pattern may be formed at the same time as forming the first contact hole,
And simultaneously forming the common wiring and the common wiring connection pattern,
And a pixel electrode connection pattern to be connected to the first pixel electrode connection pattern is further formed.

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