KR101781215B1 - Method for fabricating array substrate for liquid crystal display device of ffs mode - Google Patents

Abstract

The present invention relates to a method of manufacturing an array substrate for an FFE-type liquid crystal display, comprising a plurality of gate wirings extending in one direction on a substrate and spaced parallel to each other, Forming a plurality of spaced apart common electrodes; Forming an active layer and a source electrode and a drain electrode spaced apart from each other on the active layer together with a data line defining a pixel region in an area intersecting the gate line; Forming a photoresist film on a protective film formed on the entire surface of the substrate and selectively patterning the photoresist film to form a first pattern having a first thickness on the data line and a protective film over the source and drain electrodes, Forming a second pattern having a second thickness thinner than the first pattern on the passivation layer located in the region, and exposing the passivation layer over the drain electrode; Forming a drain electrode contact hole by removing the exposed protective layer with the first pattern and the second pattern as a blocking layer; Removing the second pattern and etching a side surface of the protective film and a lower surface of the first pattern; Forming a transparent conductive material layer on the first pattern and the protective film so as to be separated from each other on the first pattern and the protective film; And removing the transparent conductive material layer formed on the first pattern together with the first pattern to form a plurality of pixel electrodes.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of fabricating an array substrate for a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for an FFS (Fringe Field Switching mode) liquid crystal display device.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field which is applied between the common electrode and the pixel electrode, and the characteristics such as the transmittance and the aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

In such a transverse electric field type liquid crystal display device, the color filter substrate and the array substrate are opposed to each other, and a liquid crystal layer is interposed between the color filter substrate and the array substrate.

The array substrate includes a thin film transistor, a common electrode, and a pixel electrode for each of a plurality of pixels defined in a transparent insulating substrate.

In addition, the common electrode and the pixel electrode are formed on the same substrate in parallel to each other.

In the color filter substrate, a black matrix is formed on a portion of the transparent insulating substrate corresponding to the gate wiring, the data wiring, and the thin film transistor, and a color filter is formed corresponding to the pixel.

The liquid crystal layer is driven by a horizontal electric field between the common electrode and the pixel electrode.

In the transverse electric field type liquid crystal display device having the above structure, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure the luminance, but by design, the distance between the common electrode and the pixel electrode, Only a part of both ends of the electrode contributes to the improvement of brightness, and most of the area is a result of blocking light.

Therefore, the FFS (Fringe Field Switching) technique is proposed to maximize the luminance improvement effect. The FFS technique is characterized in that there is no color shift and a high contrast ratio can be obtained by precisely controlling the liquid crystal, so that it is possible to realize a high screen quality compared with a general transverse electric field technique.

An array substrate structure for a liquid crystal display device of the FFS type according to the related art having such advantages is described with reference to FIG.

1 is a plan view of an array substrate for a liquid crystal display of the FFS type according to the prior art.

As shown in FIG. 1, the FFS type liquid crystal display device according to the related art includes a plurality of gate wirings 13 extending in one direction and spaced apart from each other in parallel on a lower substrate 11, A pad 13b and a common wiring 13c; A plurality of data wirings 21 and data pads 21c intersecting with the gate wirings 13 and defining pixel regions in the crossing region; A plate-shaped pixel electrode 19 disposed on the entire surface of the pixel region formed by intersecting the gate line 13 and the data line 21; A gate electrode 13a, an active layer 17, a source electrode 21a and a drain electrode 21b, which are provided at intersections of the gate line 13 and the data line 21 and are electrically connected to the pixel electrode 19, (T); A protective film 23 formed on the entire surface of the substrate including the thin film transistor T and exposing the gate pad 13b, the data pad 21c and the common wiring 13c; A plurality of common electrodes 27a formed on the protective film 23 and spaced apart from each other by overlapping with the plate-shaped pixel electrodes 19; gate pad connection wirings 27b and data pad connection wirings 27c; .

Here, the gate wiring 13 supplies a scan signal from a gate driver (not shown) through a gate pad 13b, and the data wiring 21 supplies a video signal from a data driver (not shown). The gate wiring 13 and the data wiring 21 intersect each other with the gate insulating film 15 therebetween to define respective pixel regions.

The thin film transistor T causes the pixel electrode 19 to be charged with a pixel signal supplied to the data line 21 in response to a scan signal supplied to the gate line 13. The thin film transistor T includes a gate electrode 13a included in the gate line 13, a source electrode 21a connected to the data line 21, A drain electrode 21b connected to the gate electrode 19 and an active layer 17 overlapping the gate electrode 13a with the gate insulating film 15 interposed therebetween and forming a channel between the source electrode 21a and the drain electrode 21b, And an ohmic contact layer (not shown) formed on the active layer 17 except for the channel for ohmic contact with the source electrode 21a and the drain electrode 21b.

The data line 21 is supplied with a pixel signal from a data driver (not shown) through a data pad 21c.

A transparent plate-shaped pixel electrode 19 is disposed on the front surface of the pixel region and spaced apart from the gate line 13 and the data line 21. The pixel electrode 19 and the data line 21, a protective film 23 is formed.

A plurality of common electrodes 27a spaced apart from each other and connected to the gate pad connecting line 27b and the data pad 21c connected to the gate pad 13b are formed on the protective film 23 located in the pixel region. The data pad connecting wiring 27c is formed.

The pixel electrode 19 overlaps the plurality of common electrodes 27a with a protective film 23 in each pixel region to form a fringe field.

When a video signal is supplied to the pixel electrode 19 through the thin film transistor T, the common electrodes 27a to which the common voltage is supplied form a fringe field so that the thin film transistor substrate and the color filter substrate (not shown) The liquid crystal molecules arranged in the horizontal direction are rotated by the dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

A method of fabricating an array substrate for a liquid crystal display of the FFS type according to the related art will be described with reference to FIGS. 2A to 2F.

2 is a cross-sectional view taken along lines IIa-IIa and IIb-IIb in FIG. 1, and is a cross-sectional view of a manufacturing process of an array substrate for a liquid crystal display of the FFS system according to the prior art.

As shown in FIG. 2A, a plurality of pixel regions including a switching region are defined on a transparent substrate 11, a first conductive metal layer (not shown) is deposited on the transparent substrate 11, The gate wiring 13 and the gate electrode 13a extending from the gate wiring 13 and the gate pad 13b and the gate wiring 13b which are spaced apart in parallel to the gate wiring 13 Wiring 13c are simultaneously formed.

Then, as shown in FIG. 2B, an amorphous silicon layer (not shown) is deposited on the gate insulating layer 15 after depositing a gate insulating layer 15 on the entire surface of the substrate.

Then, the amorphous silicon layer (not shown) is selectively patterned through the second mask process to form the active layer 17 on the gate electrode 13a and the data pad formation region.

Next, as shown in FIG. 2C, a transparent conductive material layer (not shown) is deposited on the entire surface of the substrate including the active layer 17, and then selectively patterned through a third mask process, A pixel electrode 19 in the form of a plate is formed on the gate insulating film 15 located on the gate insulating film 15.

2D, a second conductive metal layer (not shown) is deposited on the entire surface of the substrate including the pixel electrode 19 and the active layer 17, and then selectively patterned through a fourth mask process A source electrode 21a and a drain electrode 21b spaced apart from each other by a channel region are formed on the active layer 17 together with the data line 21 and the data pad 21c perpendicularly intersecting the gate line 13 . At this time, the pixel electrode 19 is directly connected to the drain electrode 21b.

2E, a protective film 23 is deposited on the entire surface of the substrate including the source electrode 21a and the drain electrode 21b. Thereafter, the protective film 23 and the protective film 23 are removed through a fifth mask process. A gate pad contact hole 25a selectively exposing the gate pad 13b by selectively patterning a lower gate insulating film 15 and a data pad contact hole 25b exposing the data pad 21c, And a common wiring contact hole 25c exposing the wiring 13c are simultaneously formed.

2F, a second transparent conductive material layer (not shown) is formed on the protective film 23 including the gate pad contact hole 25a, the data pad contact hole 25b and the common wiring contact hole 25c, The second transparent conductive material layer (not shown) is selectively patterned through a sixth mask process to form gate pad connection wirings 27b with a plurality of common electrodes 27a spaced apart from each other And the data pad connecting wiring 27c are simultaneously formed. At this time, the plurality of common electrodes 27a are electrically connected to the common wiring 13c through the common wiring contact hole 25c, and the gate pad connecting wiring 27b and the data pad connecting wiring 27c Are connected to the gate pad 13b and the data pad 21c through the gate pad contact hole 25a and the data pad contact hole 25b, respectively.

In this manner, the manufacturing process of the array substrate for the liquid crystal display of the FEF system according to the conventional art is completed by the 6-mask process.

However, according to the conventional method of fabricating an array substrate for an FFE-type liquid crystal display device, since a protective film having a thickness of about 6000 A is applied, parasitic capacitor Cst is large and panel resistance is increased by capacitance, It is difficult to apply it because it leads to an increase in power consumption in terms of enlargement of the panel, and it is difficult to apply it in a high resolution model because it is difficult to expand the aperture ratio in preparation for the TN (Twisted nematic) mode.

In addition, since the pixel electrode and the common electrode of the opening are driven by a vertical electric field, it is necessary to use a process having a larger number of masks than an IPS (In Plane Switching) mode which is a transverse electric field mode. That is, in the FEF mode, since the pixel electrode is formed on the entire surface of the opening, the thickness of the protective film must be formed to be about 6000 ANGSTROM thick in order to form the electric field of the common electrode on the upper side. Therefore, the process time required for the protective film deposition process and the patterning process is increased do.

Therefore, according to the conventional method of fabricating an array substrate for a liquid crystal display device of the FEF system, since the pixel electrode and the common electrode are spaced apart from each other through the insulating film due to the structure characteristic of the FEF system driven by the vertical electric field, . Particularly, the gate and the pixel electrode must be separated from each other or separated from each other in the same layer.

When the gate and the pixel electrode are on different layers, the mask process number increases. When the gate and the pixel electrode are on the same layer, the photolithography process using the halftone mask etches the different metal layer The number of masks can be reduced, but there is a disadvantage in that a short defect between the gate and the pixel electrode increases.

Therefore, due to the structure characteristic of the FEF system driven by a vertical electric field, an optimal vertical electric field between the pixel electrode and the common electrode is formed through the protective film, and a common electrode is formed on the data wiring. Therefore, the panel capacitance load The thickness of the protective film should be increased by more than 6000 Å.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide an FFS (FFS) type liquid crystal display device capable of increasing the transmittance by reducing mask blank constants in manufacturing an array substrate for an FFS ) Type liquid crystal display device.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate of an FPC-type liquid crystal display device, the method comprising: forming a plurality of gate wirings extending in one direction and spaced apart from each other in parallel, Forming a plurality of common electrodes spaced apart from each other; Forming an active layer and a source electrode and a drain electrode spaced apart from each other on the active layer together with a data line defining a pixel region in an area intersecting with the gate wiring; Forming a protective film over the entire surface of the substrate including the data line, the source electrode, and the drain electrode; Forming a first pattern having a first thickness on the protective layer over the data line, the source electrode, and the drain electrode, forming a first pattern having a first thickness on the data line, Forming a second pattern having a second thickness thinner than the first pattern on the protective film, and exposing a protective film over the drain electrode; Forming a drain electrode contact hole by removing the exposed protective layer with the first pattern and the second pattern as a blocking layer; Removing the second pattern and etching a side surface of the protective film and a lower surface of the first pattern; Forming a transparent conductive material layer on the first pattern and the protective film so as to be separated from each other on the first pattern and the protective film; And removing the transparent conductive material layer formed on the first pattern and the first pattern to form a plurality of pixel electrodes on the passivation layer.

According to the method for fabricating an array substrate of an FFE type liquid crystal display device according to the present invention, the source electrode and the drain electrode are spaced apart from each other by the pixel electrode and the protective film, and the source electrode and the drain electrode, It is possible to improve a short defect between the generated data line and the pixel electrode.

In addition, according to the method of manufacturing an array substrate of an FFE type liquid crystal display device according to the present invention, since a plurality of common electrodes have a bar-shaped pattern structure, the transmittance is improved as compared with a conventional structure using a plate- do.

According to the method of manufacturing an array substrate of an FFE type liquid crystal display device according to the present invention, since the panel resistance is reduced by decreasing the capacitance Cdc, it can be applied to the high-resolution and large-scale models of the FFE method.

Further, according to the method of manufacturing an array substrate of an FFE type liquid crystal display device according to the present invention, an array substrate of an FFE type liquid crystal display device is manufactured through a three-mask process instead of the existing five mask process or six mask process, The number of processes and the number of processes can be reduced, thereby reducing the process cost.

1 is a plan view of an array substrate for a liquid crystal display of the FFS type according to the prior art.
2 is a cross-sectional view taken along lines IIa-IIa and IIb-IIb in FIG. 1, and is a sectional view of a manufacturing process of an array substrate for a liquid crystal display of the FFS system according to the prior art.
3 is a plan view of an array substrate for a liquid crystal display of the FFS type according to the present invention.
4 is a cross-sectional view of the array substrate for a liquid crystal display according to the FFS method according to the present invention, taken along line IVa-IVa, line IVb-IVb and line IVc-IVc in FIG.
5A to 5P are cross-sectional views illustrating manufacturing steps of an array substrate for an F-FFS type liquid crystal display according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an array substrate for a liquid crystal display (FPS) system according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of an array substrate for a liquid crystal display of the FFS type according to the present invention.

4 is a cross-sectional view of the array substrate for a liquid crystal display according to the FFS method according to the present invention, taken along line IVa-IVa, line IVb-IVb and line IVc-IVc in FIG.

As shown in Figs. 3 and 4, the FFS type liquid crystal display array substrate according to the present invention includes a plurality of gate wirings (not shown) extending in one direction on a substrate 101 and spaced apart from each other in parallel 106, a gate pad 106c, and a plurality of common electrodes 103b; A plurality of data lines 117a and data dots 117d intersecting with the gate lines 106 and defining pixel regions in the crossing region; A thin film transistor T formed at the intersection of the gate wiring 106 and the data line 117a and composed of the gate electrode 106a, the active layer 113a, the source electrode 117b and the drain electrode 117c, ; A protective layer 123 formed on the entire surface of the substrate including the thin film transistor T and exposing the gate pad 106c, the data pad 117d and the drain electrode 117c; And a plurality of pixel electrodes 131a disposed on the protective layer 123 and spaced apart from the plurality of common electrodes 103b and electrically connected to the drain electrodes.

Here, the gate wiring 106 receives a scan signal from a gate driver (not shown) through a gate pad 106c, and the data wiring 117a receives a scan signal from a data driver (not shown) via a data pad 117d. And supplies a video signal. The gate wiring 106 and the data wiring 117a intersect each other with the gate insulating film 111 interposed therebetween to define respective pixel regions.

The gate wiring 106 is formed in at least a double-layer structure or a single-layer structure including a transparent conductive layer on the lower substrate 101. For example, a multilayer structure in which a first conductive layer using a transparent conductive layer and a second conductive layer using an opaque metal are stacked, or a laminate structure of the moving structure or an opaque metal.

The first conductive layer may be formed of ITO, IZO, ITZO, Moti, or Mo, and the second conductive layer may be formed of Cu, Mo, Al, Cu alloy, Mo alloy, Al alloy, or the like.

The thin film transistor T causes the pixel electrode 131a to be charged with the pixel signal supplied to the data line 117a in the scan signal supplied to the gate line 106. [

The thin film transistor T includes a gate electrode 106a included in the gate wiring 106, a source electrode 117b connected to the data line 117a, and a source electrode 117b, A drain electrode 117c connected to the gate electrode 131a and an active layer 113a overlapping the gate electrode 106 with the gate insulating film 111 sandwiched therebetween and forming a channel between the source electrode 117b and the drain electrode 117c, And an ohmic contact layer 115a formed on the active layer 113a except the channel for ohmic contact with the source electrode 117b and the drain electrode 117c.

The data line 117a receives a pixel signal from a data driver (not shown) through a data pad 117d.

In addition, transparent common electrodes 103b spaced apart from the gate lines 106 and the data lines 117a and spaced apart from each other in parallel with the data lines 117a are formed on the front surface of the pixel region.

A plurality of transparent pixel electrodes 131a are arranged alternately with the lower common electrodes 103b on the protective film 123. The pixel electrodes 131a are electrically connected to the drain electrodes 117c have.

In addition, a plurality of pixel electrodes 123a spaced apart from each other and connected to the gate pad connecting wiring 123b and the data pad 119d connected to the gate pad 106b are formed on the protective film 123 located in the pixel region The data pad connecting wiring 123c is formed.

In this way, the plurality of common electrodes 103b supplies a reference voltage for driving the liquid crystal, that is, a common voltage to each pixel.

The plurality of pixel electrodes 131a form a fringe field with the lower common electrode 103b through the protective film 123 in each pixel region.

In this way, when a video signal is supplied to the pixel electrode 131a through the thin film transistor T, the common electrodes 103b to which the common voltage is supplied form a fringe field, which is in between the thin film transistor substrate and the color filter substrate The liquid crystal molecules arranged in the horizontal direction are rotated by the dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

A method of manufacturing an array substrate for an FPC-type liquid crystal display according to the present invention will be described with reference to FIGS. 5A to 5P.

5A to 5P are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display (FPS) system according to the present invention.

Pixel region is defined along with a plurality of pixel regions including a switching region on a transparent substrate 101 and a first transparent conductive material layer 103 is formed on the transparent substrate 101, And the first conductive metal layer 105 are sequentially deposited by a sputtering method. At this time, as the first transparent conductive material layer 103, any one selected from a transparent conductive material group including ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), MoTi and Mo is used.

The first conductive metal layer 105 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum alloy, (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo alloy / Al alloy, Mo / Al alloy, Cu / Mo alloy, Cu / Mo (Ti)

Next, as shown in FIG. 5B, a photo-resist having a high transmittance is coated on the first conductive metal layer 105 to form a first photoresist layer 107.

Subsequently, the first photoresist layer 107 is exposed using the first diffraction mask 109 including the light intercepting portion 109a, the transflective portion 109b and the transmissive portion 109c. At this time, the light blocking portion 109a of the first diffraction mask 109 is located on the first photoresist layer 107 corresponding to the gate wiring formation region including the gate electrode and the gate pad formation region, The transflective portion 109b of the mask 109 is located above the first photoresist 107 corresponding to the common electrode formation area. Further, in addition to the first diffraction mask 109, a mask using a diffraction or transmission effect of light, for example, a half-tone mask or another mask may be used.

 Next, as shown in FIG. 5C, the first photoresist layer 107 is patterned through the exposure process and then a developing process to form a first pattern 107a of a gate wiring and a gate pad formation region, The second pattern 107b of the region is formed. At this time, since the first pattern 107a of the gate wiring formation region and the gate pad formation region does not transmit light, the thickness of the first photoresist film 107 is maintained as it is, A part of the light is transmitted and removed by a predetermined thickness. That is, the second pattern 107b of the common electrode formation region has a thickness thinner than the first pattern 107a of the gate wiring formation region and the gate pad formation region.

5D, using the first pattern 107a of the gate wiring formation region and the auxiliary common wiring formation region of the first photosensitive film and the second pattern 107b of the common wiring formation region as masks, 1) conductive metal layer 105 and the first transparent conductive material layer 103 are patterned to form a gate wiring (not shown in FIG. 4, 106), a gate electrode 106a protruding from the gate wiring 106, 106c and the common electrode 103b. The gate electrode 106a and the gate electrode 106a are formed of a first conductive metal layer pattern 105a and a first transparent conductive material layer pattern 103a, 106c are formed of a first conductive metal layer pattern 105v and a first transparent conductive material layer pattern 103c. The common electrodes 103b are spaced apart from each other and are formed in a direction perpendicular to the gate wiring (not shown in FIG. 4).

5E, all of the second pattern 107b on the second conductive metal layer pattern 105b on the common electrodes 103b is etched through an ashing process to form the common electrode 103b, The second conductive metal layer pattern 105b on the first conductive metal layer 103b is exposed to the outside. At this time, a part of the thickness of the first pattern 107a on the gate wiring (not shown), the gate electrode 106a, and the gate pad 106c is also etched through the ashing process.

Then, as shown in FIG. 5F, the exposed second conductive metal layer pattern 105b is removed with the first pattern 107a, which is partially etched by the ashing process, The gate wiring 106a, the gate electrode 106a and the gate pad 106c are exposed by removing the remaining first pattern 107a. The gate line 106a, the gate electrode 106a, and the gate pad 106c may be formed of a layer of a transparent conductive material layer and a layer of a non-transparent conductive metal material layer .

Next, as shown in FIG. 5G, a gate insulating film 111 made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate.

Subsequently, an amorphous silicon layer (a-Si: H) 113 and an amorphous silicon layer (n + or p +) 115 containing impurities and a second conductive metal layer 117 are sequentially formed on the gate insulating film 111 Laminated. At this time, the amorphous silicon layer (n + or p +) 115 containing the amorphous silicon layer (a-Si: H) 113 and the impurities is deposited by a chemical vapor deposition (CVD) method, 2 conductive metal layer 117 is deposited by a sputtering method. Herein, only the chemical vapor deposition method and the sputtering method are described as the above vapor deposition method, but other vapor deposition methods may be used in some cases. At this time, the second conductive metal layer 117 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum alloy, (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo alloy / Al alloy, Mo / Al alloy, Cu / Mo alloy, Cu / Mo (Ti)

Next, a second photoresist layer 119 having excellent transparency is applied on the second conductive metal layer 117.

Subsequently, the second photoresist layer 119 is subjected to an exposure process using a second diffraction mask 121 composed of a light intercepting portion 121a, a transflective portion 121b and a transmissive portion 121c. At this time, the light blocking portion 121a of the second diffraction mask 121 is positioned above the second photoresist layer 119 corresponding to the data pad formation region and the source and drain electrode formation regions , The transflective portion 121b of the second diffraction mask 121 is located in the channel region of the thin film transistor T, that is, above the second photoresist film 119 corresponding to the gate electrode 106a. In addition to the second diffraction mask 121, a mask using a diffraction or transmission effect of light, for example, a half-tone mask or another mask may be used.

5H, a developing process is performed after the exposure process, and then the second photoresist layer 119 is selectively patterned to form a data pad formation region and a data pad formation region together with the source and drain electrode formation regions, as shown in FIG. 5H And a second pattern 119b is formed in a channel region of the TFT (T). At this time, since the first pattern 119a of the data wiring formation region, the source electrode, the drain electrode, and the data pad formation region does not transmit light, the second photoresist film thickness remains the same, A part of the light is transmitted through the second pattern 119b of the channel region of the first photoresist layer 119a and removed by a predetermined thickness. That is, the second pattern 119b of the channel region of the thin film transistor T is thinner than the first pattern 119a of the data line formation region and the source and drain electrode formation regions.

5I, a first pattern 119a of the data line formation region, a source electrode, a drain electrode, and a data pad formation region and a second pattern 119b of a channel region of the thin film transistor T, The amorphous silicon layer 115 containing the impurity and the amorphous silicon layer 113 are selectively patterned to form the active layer 115 together with the data line 117a and the data pad 117d, A source electrode forming region, a drain electrode forming region and an ohmic contact layer forming region are respectively defined.

5J, the second pattern 119b of the channel region of the thin film transistor T is completely removed through an ashing process to completely remove the second pattern 119b of the channel region of the thin film transistor T. Thus, The portion of the second conductive metal layer 117 under the pattern 119b is exposed. At this time, a part of the thickness of the first pattern 119a in the data and data pad regions and the source and drain electrode forming regions is also removed through the ashing process.

Then, the exposed portion of the second conductive metal layer 117 is etched by using the first pattern 119a of the data wiring and data pad regions and the source and drain electrode forming regions where a part of the thickness is etched by the ashing process, Thereby forming the source electrode 117b and the drain electrode 117c spaced apart from the source electrode 117b.

Next, although not shown in the drawing, the amorphous silicon layer 115 containing impurities in the channel region is removed through an etching process to form an ohmic contact layer 115a exposing a channel region of the active layer 113a .

Next, as shown in FIG. 5K, the remaining first pattern 119a is removed, and a protective film 123 made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate.

Then, a photo-resist having a high transmittance is applied on the protective film 123 to form a third photoresist film 125.

Subsequently, the third photoresist layer 125 is subjected to an exposure process using a third diffraction mask 127 composed of a light intercepting portion 127a, a transflective portion 127b and a transmissive portion 127c.

At this time, the light blocking portion 127a of the third diffraction mask 127 is electrically connected to the gate electrode 106c, the data pad 117c, the pixel electrode formation region, and the drain electrode contact hole formation region, And is located on the upper side of the photosensitive film 125.

In addition, the transflective portion 127b of the third diffraction mask 127 is located above the third photoresist 125 corresponding to the pixel electrode formation region.

The transmissive portion 127c of the third diffraction mask 127 is located above the second photoresist 125 corresponding to the gate pad contact hole, the data pad contact hole, and the drain electrode contact hole formation region. At this time, in addition to the third diffraction mask 127, a mask using a light diffraction or transmission effect, for example, a multi-tone mask or another mask may be used.

Then, as shown in FIG. 5L, the development process is performed after the exposure process, and then the second photoresist layer 125 is selectively patterned to form the gate pad 106c, the data pad 117c, the pixel electrode formation region, A first pattern 125a is formed in an area other than an electrode contact hole forming area and a second pattern 125b is formed in the pixel electrode forming area. At this time, the portion of the second photoresist 125 corresponding to the gate pad contact hole, the data pad contact hole, and the drain electrode contact hole formation region is completely removed. At this time, since the first pattern 125a formed in the regions other than the gate pad 106c, the data pad 117c, and the drain electrode contact hole forming region is in a state where no light is transmitted, the thickness of the third photosensitive film is maintained , The second pattern 125b formed in the pixel electrode formation region is partially removed by the third photoresist layer and is removed by a predetermined thickness. That is, the second pattern 125b of the pixel electrode formation region has a thickness smaller than that of the first pattern 125a.

Next, as shown in FIG. 5m, the exposed protective film 123 and the underlying gate insulating film 111 are selectively etched using the first pattern 125a and the second pattern 125b of the third photosensitive film as masks, To form a drain electrode contact hole 129a, a gate pad contact hole 129b and a data pad contact hole 129c at the same time.

5N, an ashing process using the SF ₆ and O ₂ is performed to completely remove the second pattern 125b in the pixel electrode formation region, and the first pattern 125a is removed, Remove only some thickness.

The second pattern 125b and the first pattern 125a are formed by etching the first and second patterns 125a and 125b, respectively, when the first etching process is performed by adjusting the ratio of SF ₆ to O ₂ to 1: 3 or more. The second pattern 125b is completely removed first, and only the first pattern 125a is partially removed. Next, when the second pattern 125b is completely removed, the ratio of the SF ₆ and O ₂ is adjusted to about 3 to about 1, contrary to the first etching, The protective film 123 and the first pattern 125a are etched faster than the first pattern 125a and the undercut phenomenon occurs under the protective film 123 and the first pattern 125a, Is etched to the inside of the side surface.

Next, as shown in FIG. 5O, a second transparent conductive material layer 131 is deposited on the first pattern 125a and the protective layer 123 by a sputtering method. At this time, as the second transparent conductive material layer 131, any one selected from transparent conductive material group including ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), MoTi and Mo is used. The second transparent conductive material layer 131 is formed on the first pattern 125a and the protective film 123 by the lower region of the first pattern 125a etched to the side by the undercut phenomenon, Are separated from each other.

5P, a second transparent conductive material layer 131 separated from the first pattern 125a and the protective film 123 and a first pattern 125a are baked, The first pattern 125a is removed through a subsequent lift-off process and the second transparent conductive layer 131 on the first pattern 125a is removed as well, A plurality of pixel electrodes 131a are formed. At this time, the plurality of pixel electrodes 131a are electrically connected to the drain electrode 117c through the drain electrode contact hole 129a and alternately arranged with the lower common electrode 103b. A gate pad connection wiring 131b electrically connected to the gate pad 106c through the gate pad contact hole 129b is formed on the protection layer 123. The gate pad connection wiring 131b is electrically connected to the gate pad 106c through the data pad contact hole 129c, A data pad connection wiring 131c electrically connected to the data pad 117d is formed simultaneously with the pixel electrode 131a.

In this way, the manufacturing process of the array substrate for the liquid crystal display of the FEF system according to the present invention is completed by the three-mask process.

As described above, according to the array substrate of the FEF LCD device and the method of manufacturing the same, the source electrode and the drain electrode are separated from each other by the pixel electrode and the protective film, It is possible to improve a short defect between the data line and the pixel electrode generated by the foreign material during the photo process.

In addition, according to the array substrate of the FEF LCD type liquid crystal display device and the method of manufacturing the same, a plurality of common electrodes have a bar-shaped pattern structure, and the transmittance .

According to the array substrate of the FFC type liquid crystal display device and the method of manufacturing the same according to the present invention, since the panel resistance is reduced by decreasing the capacitance Cdc, it can be applied to the FPC-type high resolution model and the large-sized model Do.

Furthermore, according to the array substrate of the FFE type liquid crystal display device and the method of manufacturing the same according to the present invention, an array substrate of an FFE type liquid crystal display device is manufactured through a 3-mask process instead of the existing 5-mask process or 6-mask process The number of masks and the number of processes can be reduced, thereby reducing the process cost.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

101: Substrate 103: First transparent conductive material layer
103b: common electrode 105: first conductive metal layer
106: gate wiring 106a: gate electrode 106c: gate pad 107: first photoresist film
109: first diffraction mask 111: gate insulating film 113a: active layer 115a: ohmic contact layer
117: second conductive metal layer 117a: data wiring
117b: source electrode 117c: drain electrode
117d: Data pad 119: Second photosensitive film
121: second diffraction mask 123: protective film
125: third photoresist 127: third diffraction mask
129a: drain electrode contact hole 129b: gate pad contact hole 129c: data pad contact hole 131: second transparent conductive material layer
131a: pixel electrode 131b: gate pad connection wiring
131c: Data Pad Connection Wiring

Claims (7)

Forming a plurality of common electrodes arranged perpendicularly to the gate wiring and spaced apart from each other with a plurality of gate wirings extending in one direction on the substrate and spaced parallel to each other;
Forming an active layer and a source electrode and a drain electrode spaced apart from each other on the active layer together with a data line defining a pixel region in an area intersecting the gate line;
Forming a protective film on the entire surface of the substrate including the data line, the source electrode, and the drain electrode;
Forming a photoresist film on the protective film and selectively patterning the photoresist film to form a first pattern having a first thickness on the protective film over the data line and the source and drain electrodes; Forming a second pattern having a second thickness thinner than the first pattern on the passivation layer and exposing the passivation layer over the drain electrode;
Forming a drain electrode contact hole by removing the exposed protective layer with the first pattern and the second pattern as a blocking layer;
Removing the second pattern and etching a side surface of the protective film and a lower surface of the first pattern;
Forming a transparent conductive material layer on the first pattern and the protective film so as to be separated from each other on the first pattern and the protective film; And
And removing the transparent conductive material layer formed on the first pattern together with the first pattern to form a plurality of pixel electrodes on the protective film. ≪ Desc / Clms Page number 19 > 2. The method according to claim 1, wherein the step of forming a plurality of common electrodes arranged vertically with the gate wiring and spaced apart from each other by the gate wiring is performed by a mask process using a diffraction mask, A method of manufacturing an array substrate of a device. The method as claimed in claim 1, wherein the step of forming the active layer and the source electrode and the drain electrode spaced apart from each other on the active layer together with the data line are performed by a mask process using a diffraction mask, ≪ / RTI > The method of claim 1, further comprising: forming a first pattern having a first thickness on the data line, a protective film over the source electrode and the drain electrode, forming a first pattern on the protective film, Wherein the step of forming the second pattern having the second thickness and exposing the protective film on the drain electrode is performed by a mask process using a diffraction mask. The method as claimed in claim 1, wherein the etching of the lower surface of the first pattern and the side surface of the passivation layer is performed by an ashing process. Way. 6. The method according to claim 5,
The etching rate of the second pattern and the first pattern is higher than that of the protective film by controlling the ratio of SF ₆ and O ₂ to 1 to 3 or more so that the second pattern is completely removed first, Pattern 125a is partially removed;
And etching the second pattern by adjusting the ratio of SF ₆ and O ₂ to 3 or more to 1 at the time when the second pattern is completely removed, contrary to the case of the first etching. Type liquid crystal display device. The FPC type liquid crystal display device according to claim 1, wherein the step of removing the transparent conductive material layer formed on the first pattern together with the first pattern is performed by a lift-off process Lt; / RTI >

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