KR101897747B1 - Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate for an FFE-type liquid crystal display device and a method of manufacturing the same. A gate insulating film and an active layer formed on the entire surface of the substrate including the gate wiring; a source electrode and a drain electrode formed on the active layer and spaced apart from each other; a barrier pattern spaced from the drain electrode; A data line formed on the gate insulating film and perpendicularly intersecting the gate line; A pixel electrode formed on the substrate corresponding to a pixel region formed by intersecting the gate wiring and the data wiring; A pixel electrode contact pattern formed on the pixel electrode and overlapped with the barrier pattern; A passivation film formed on the entire surface of the substrate including the pixel electrode, the data line, and the barrier pattern; A pixel electrode contact hole formed in the passivation film and a gate insulating film below the passivation film to expose the pixel electrode and the drain electrode; And a pixel electrode connection pattern formed on the passivation film and electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to an array substrate for an FFE-type liquid crystal display device and a method of manufacturing the array substrate.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an FFS (Fringe Field Switching) type liquid crystal display device and a method of manufacturing the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

Although not shown in the drawings, such a transverse electric field type liquid crystal display device has a color filter substrate and a thin film transistor substrate facing each other, and a liquid crystal layer interposed between the color filter substrate and the thin film transistor substrate.

A thin film transistor, a common electrode, and a pixel electrode are formed for each of a plurality of pixels defined in the thin film transistor substrate. At this time, the common electrode and the pixel electrode are formed on the same substrate in parallel to each other.

In the color filter substrate, a black matrix is formed at a portion corresponding to a gate wiring formed on the thin film transistor substrate, a data wiring and a thin film transistor formed at a crossing point of the wiring, and a color filter is provided corresponding to the pixel .

Therefore, the liquid crystal layer is driven by the horizontal electric field between the common electrode and the pixel electrode.

In the transverse electric field type liquid crystal display device having the above structure, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure the luminance, but by design, the distance between the common electrode and the pixel electrode, Only a part of both ends of the electrode contributes to the improvement of brightness, and most of the area is a result of blocking light.

Therefore, a technique proposed to maximize the luminance improvement effect is Fringe Field Switching (hereinafter referred to as FFS) technology. The FFS technique is characterized in that there is no color shift and a high contrast ratio can be obtained by precisely controlling the liquid crystal, so that it is possible to realize a high screen quality compared with a general transverse electric field technique.

A conventional FFS type liquid crystal display device having such a high image quality as described above will be described with reference to FIGS. 1 to 3. FIG.

1 is a plan view of a thin film transistor substrate for an FFS type liquid crystal display according to the prior art.

FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, and is a schematic cross-sectional view of a thin film transistor substrate for an FFS type liquid crystal display according to the prior art.

FIG. 3 is an enlarged plan view of the "A" portion of FIG. 1, showing a distance between a common electrode and a pixel electrode connection pattern in an enlarged view of a thin film transistor substrate for a FFS FIG.

1 to 2, a conventional FFS type liquid crystal display device according to the related art includes a plurality of gate wirings 15 extending in one direction and spaced apart from each other in parallel on a transparent insulating substrate 11, A gate electrode 15a extending from the gate wiring 15; A gate insulating layer 17 formed on the entire surface of the substrate including the gate electrode 13a; A plurality of data lines 23 formed on the gate insulating layer 17 and defining pixel regions in an area intersecting the gate lines 13; The active layer 19 and the ohmic contact layer 21 are provided at the intersections of the gate line 15 and the data line 23 and formed on the gate electrode 15a and the gate insulating film 17, And a thin film transistor T composed of a source electrode 23a and a drain electrode 23b.

A large-area pixel electrode 13 is disposed on the substrate 11 in the pixel region formed by intersecting the gate line 15 and the data line 23. A gate insulating film And a plurality of rod-shaped transparent common electrodes 29a spaced apart from each other with a passivation film 25 therebetween are arranged.

The pixel electrode 13 is overlapped with the plurality of common electrodes 29a and is electrically connected to the pixel electrode contact hole 29a formed in the gate insulating film 17 and the passivation film 25 by the pixel electrode connecting pattern 29b. And is electrically connected to the drain electrode 23b under the gate electrode 27.

3, a first gap distance d1 is provided between one end of the common electrode 29a and the pixel electrode connection pattern 29b, and the pixel electrode connection pattern 29b and the pixel electrode connection pattern 29b are spaced apart from each other by a first distance d1. A second gap d2 is maintained between the electrode contact holes 27. [

According to the above configuration, when a data signal is supplied to the pixel electrode 13 through the thin film transistor T, the common electrodes 29a to which the common voltage is supplied form a fringe field, ) And the color filter substrate (not shown), liquid crystal molecules arranged in the horizontal direction are rotated by dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

A method of manufacturing a fringe field (FFS) type liquid crystal display device having the above-described structure according to the related art will be briefly described with reference to FIGS. 1 to 3. FIG.

First, a transparent insulating substrate 11 defining a plurality of pixel regions including a switching region is prepared.

Next, as shown in FIGS. 1 and 2, an ITO layer (Indium Tin Oxide) (not shown) as a first transparent conductive material is deposited on the entire surface of the insulating substrate 11, The pixel electrode 13 having a large area is formed in the pixel region of the insulating substrate 11. [

A first conductive metal layer (not shown) is deposited on the entire surface of the insulating substrate 11 including the pixel electrode 13 by a sputtering method. Then, a second mask process using a photolithography technique is performed to deposit the first conductive metal layer A conductive metal layer (not shown) is selectively patterned to form a gate wiring 15, a gate electrode 15a protruding from the gate wiring 15, and a gate pad (not shown) electrically connected to the external driving circuit.

Then, a gate insulating film 17 is deposited on the entire surface of the substrate including the gate wiring 15 and then an amorphous silicon layer (a-Si: H) (not shown) and an amorphous silicon layer (N + or p +) (not shown) containing the impurities and the amorphous silicon layer (a +) (not shown) are sequentially deposited through a third mask process using a photolithography technique, The active layer 19 and the ohmic contact layer 21 are formed on the gate insulating film 17 above the gate electrode 15a by selectively etching the gate electrode 15a.

Next, a second conductive metal layer (not shown) is deposited on the gate insulating film 17 including the ohmic contact layer 21 and the active layer 19.

Then, the second conductive metal layer (not shown), the ohmic contact layer 21 and the active layer 19 are selectively removed through a fourth mask process using a photolithography technique to form the gate wiring 15 A data line 23 crossing vertically, and a source electrode 23a and a drain electrode 23b extending from the data line 23 are formed. At this time, a data pad (not shown) extending from the data line 23 and electrically connected to an external driving circuit (not shown) is formed at the time of forming the data line 23.

Then, a passivation film 25 is deposited on the entire surface of the substrate including the pixel electrode 23.

The passivation film 25 and the gate insulating film 17 are selectively etched through a fifth mask process using a photolithography technique to expose the drain electrode 23b and the pixel electrode 13, Thereby forming a contact hole 27a.

Next, a second transparent conductive material layer (not shown) is deposited on the passivation film 25 including the pixel electrode contact hole 27a. Then, a second transparent conductive material layer (not shown) is deposited on the passivation film 25 through the sixth mask process using a photolithography technique. The drain electrode 23b and the pixel electrode 13 are electrically connected through the pixel electrode contact hole 27a together with a plurality of common electrodes 29a spaced apart from each other by selectively etching a transparent conductive material layer A pixel electrode connection pattern 29b is formed. 3, a first gap distance d1 is provided between one end of the common electrode 29a and the pixel electrode connection pattern 29b, and the pixel electrode connection pattern 29b and the pixel electrode connection pattern 29b are spaced apart from each other by a first distance d1. And a second spacing distance d2 is formed between the electrode contact holes 27. [

Thus, the manufacturing process of the thin film transistor array substrate for the FFE type liquid crystal display according to the related art is completed.

Thereafter, although not shown in the drawing, an FFE-type liquid crystal display device is manufactured by performing a process of filling the liquid crystal layer between the array substrate and the color filter substrate together with the color filter substrate manufacturing process.

As described above, according to the array substrate of the FEF type liquid crystal display device according to the related art, since the mask process is performed six times during the fabrication of the array substrate for the FFS type liquid crystal display device, And the cost required for the mask process is increased. Particularly, in a conventional FFS (Fringe Field Switching) type liquid crystal display device, a separate mask must be used to form the active layer and the pixel electrode, so that the number of mask processes increases accordingly.

Further, according to the related art, separate pixel electrode contact holes and pixel electrode connection patterns are required for the contact between the drain electrode of the thin film transistor and the pixel electrode formed thereunder.

Therefore, in the case of the pixel electrode connection pattern, the ITO layer is patterned in a lump when the ITO layer, which is the transparent conductive material layer for common electrode formation, is patterned without a separate exposure process. At this time, since the first distance d1 is required for securing a short margin between the common electrode and the pixel electrode connection pattern, for example, as shown in FIG. 3, the opening area and the transmittance .

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to reduce the number of mask processes in manufacturing an array substrate for an FFS type liquid crystal display, (FFS) type liquid crystal display device capable of improving the aperture ratio by reducing the size of the array substrate and the manufacturing method thereof.

According to an aspect of the present invention, there is provided an array substrate for an FFE-type liquid crystal display, including: a gate wiring formed on one surface of a substrate in one direction; A gate insulating film and an active layer formed on the entire surface of the substrate including the gate wiring; a source electrode and a drain electrode formed on the active layer and spaced apart from each other; a barrier pattern spaced from the drain electrode; A data line formed on the gate insulating film and perpendicularly intersecting the gate line; A pixel electrode formed on the substrate corresponding to a pixel region formed by intersecting the gate wiring and the data wiring; A pixel electrode contact pattern formed on the pixel electrode and overlapped with the barrier pattern; A passivation film formed on the entire surface of the substrate including the pixel electrode, the data line, and the barrier pattern; A pixel electrode contact hole formed in the passivation film and a gate insulating film below the passivation film to expose the pixel electrode and the drain electrode; And a pixel electrode connection pattern formed on the passivation film and electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for an FPC-type liquid crystal display, including: forming a pixel electrode having a gate line and a pixel electrode contact pattern in one direction; Forming a gate insulating film on the entire surface of the substrate including the gate wiring; Forming an active layer above the gate insulating film and source and drain electrodes formed on the active layer and spaced apart from each other; and forming a data line perpendicularly intersecting the gate line with a barrier pattern spaced from the drain electrode ; Forming a passivation film on the entire surface of the substrate including the pixel electrode, the data line, and the barrier pattern; Forming a pixel electrode contact hole exposing the pixel electrode and the drain electrode in the passivation film and a gate insulating film below the passivation film; And forming a pixel electrode connection pattern electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode on the passivation film.

The gate wiring and the pixel electrode can be formed using a single mask and the active layer, the source electrode, and the drain electrode can be formed by using one mask at the time of manufacturing the array substrate for the FEF LCD type liquid crystal display device according to the present invention In addition, it is possible to manufacture an FFE-type liquid crystal display device by a four-step mask process instead of the conventional five-time mask process, thereby reducing the mask cost, thereby shortening the manufacturing process time and reducing the manufacturing cost.

Further, according to the array substrate for an FPC-type liquid crystal display and the method of manufacturing the same according to the present invention, the pixel electrode contact pattern composed of the metal conductive layer at the time of forming the gate wiring and the pixel electrode is formed, A short between the pixel electrode and the common electrode can be formed during the etching process.

According to the array substrate for an FFC-type liquid-crystal display device and the method for fabricating the same, a barrier pattern capable of breaking in a region where a short margin is generated is formed, and when the ITO for common electrode formation is deposited By forming a short between the pixel electrode and the common electrode, the region required for disconnection is extended to the area of the opening area, thereby increasing the aperture ratio and the transmittance.

Further, according to the array substrate for an FFC-type liquid-crystal display device and the method of manufacturing the same, in a region where a short margin between the pixel electrode and the common electrode is required after the pixel electrode contact hole is formed A barrier pattern is formed and an undercut phenomenon occurs in a portion of the gate insulating film under the barrier pattern so that the drain electrode and the pixel electrode are electrically connected through the pixel electrode contact hole at the time of ITO deposition for common electrode formation It is possible to maintain a short between the pixel electrode and the common electrode.

1 is a plan view of a thin film transistor substrate for an FFS type liquid crystal display according to the prior art.
FIG. 2 is a cross-sectional view taken along a line II-II in FIG. 1, and is a schematic cross-sectional view of a thin film transistor array substrate for an FFS type liquid crystal display according to the prior art.
Fig. 3 is an enlarged plan view of the "A" portion of Fig. 1, showing a distance between a common electrode and a pixel electrode connection pattern in an enlarged view Fig.
4 is a plan view of a thin film transistor array substrate for an FFS type liquid crystal display according to the present invention.
5 is a cross-sectional view taken along the line V-V in FIG. 4, and is a schematic cross-sectional view of a thin film transistor array substrate for an F-FFS type liquid crystal display according to the present invention.
FIG. 6 is an enlarged plan view of the "B" portion of FIG. 4, showing a barrier pattern disposed between the common electrode and the pixel electrode connection pattern in the thin film transistor array substrate for an FFS A pixel electrode contact pattern, and a pixel electrode connection pattern.
FIG. 7 is an enlarged plan view of the "B" portion of FIG. 4, and is an enlarged cross-sectional view showing a connection state of a barrier pattern disposed between a common electrode and a pixel electrode connection pattern, a pixel electrode contact pattern, and a pixel electrode connection pattern.
8A to 8T are cross-sectional views illustrating a manufacturing process of an FFS type liquid crystal display device according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an array substrate for an F-FFS type liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a thin film transistor array substrate for an FFS type liquid crystal display according to the present invention.

5 is a cross-sectional view taken along the line V-V in FIG. 4, and is a schematic cross-sectional view of a thin film transistor array substrate for an F-FFS type liquid crystal display according to the present invention.

FIG. 6 is an enlarged plan view of the "B" portion of FIG. 4, showing a barrier pattern disposed between the common electrode and the pixel electrode connection pattern in the thin film transistor array substrate for an FFS A pixel electrode contact pattern, and a pixel electrode connection pattern.

FIG. 7 is an enlarged plan view of the "B" portion of FIG. 4, and is an enlarged cross-sectional view showing a connection state of a barrier pattern disposed between a common electrode and a pixel electrode connection pattern, a pixel electrode contact pattern, and a pixel electrode connection pattern.

As shown in FIGS. 4 to 7, the array substrate for FFS type liquid crystal display according to the present invention includes a gate wiring 106 formed on one surface of a transparent insulating substrate 101 in one direction; A source electrode 117b and a drain electrode 117c formed on the active layer 113a and the gate insulating film 1111 formed on the entire surface of the substrate including the gate wiring 106 and spaced apart from each other, A barrier pattern 117d spaced from the drain electrode 117c; A data line 117a formed on the gate insulating layer 111 and perpendicularly intersecting the gate line 106; A pixel electrode 103b formed on the substrate corresponding to a pixel region formed by intersecting the gate wiring 106 and the data wiring 117a; A pixel electrode contact pattern 106b formed on the pixel electrode 103b and overlapped with the barrier pattern 117d; A passivation film 123 formed on the entire surface of the substrate including the pixel electrode 103b, the data line 117a, and the barrier pattern 117d; A pixel electrode contact hole 127 formed in the passivation film 123 and the gate insulating film 111 under the passivation film 123 to expose the pixel electrode 103b and the drain electrode 117c; And a pixel electrode connection pattern 130 which is formed on the passivation film 123 and electrically connects the pixel electrode 103b and the drain electrode 117c together with a plurality of common electrodes 129a overlapping the pixel electrode 125. [ (129b).

Here, the gate wiring 106 has a laminated structure of a transparent conductive layer pattern 103a and a metal conductive layer pattern 105a.

The pixel electrode 103b is formed on the entire surface of the pixel region of the insulating substrate 101 corresponding to the space separated from the gate wiring 106a and the data wiring 117a.

An island-shaped pixel electrode contact pattern 106b is formed on a portion of the drain electrode 117c and on the upper surface of the pixel electrode 103b overlapping with the barrier pattern 117d. At this time, the pixel electrode contact pattern 106b is made of a metal conductive material.

In addition, a plurality of transparent common electrodes 129a are disposed on the pixel electrode 103b with a certain distance therebetween, with the passivation film 123 and the gate insulating film 111 interposed therebetween. At this time, the common electrode 129a overlaps with the large-area pixel electrode 103b disposed in the pixel region. 5 and 6, since the opening region C having the first distance d1 is secured between the pixel electrode contact pattern 106b and the common electrode 129a, the aperture ratio and transmittance can be improved do.

Therefore, a reference voltage for driving the liquid crystal, that is, a common voltage is supplied to each of the plurality of common electrodes 129a. The common electrode 129a overlaps the pixel electrode 103b of the large area with the passivation film 123 and the gate insulating film 111 in each pixel region to form a fringe field.

The pixel electrode connection pattern 129b is connected to the pixel electrode 103b and the drain electrode 117c through the pixel electrode contact hole 127. [ At this time, the pixel electrode contact hole 127 is formed in the passivation film 123 and the gate insulating film 111 under the pixel electrode contact hole 127, and the side wall of the pixel electrode contact hole 127 formed in the gate insulating film 111 is formed with an undercut A portion 127a is formed. A layered structure of the barrier pattern 117d, the ohmic contact layer 115a, and the active layer 113a is disposed at an upper portion overlapping the undercut portion 127a. The pixel electrode connection pattern 129b contacts not only the drain electrode 117c and the pixel electrode 103b but also the sidewalls of the ohmic contact layer 115a and the active layer 113a.

5 to 7, the thin film transistor T includes a gate electrode 106a extending in the vertical direction from the gate wiring 106 formed on the insulating substrate 101 and a gate electrode 106b extending in the vertical direction And a source electrode 117b and a drain electrode 117c spaced apart from each other by the channel region of the active layer 113a together with the gate insulating film 111 formed on the active layer 113a and the ohmic contact layer 115a.

A gate pad (not shown) extending from the gate wiring 106 and connected to an external driving circuit (not shown) is formed at one end of the gate wiring 106.

A data pad (not shown) extending from the data line 117a and connected to the external driving circuit is formed at one end of the data line 117a.

Although not shown in the drawing, a lower alignment film (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 129a.

On the other hand, a black matrix (BM) is formed on the color filter substrate (not shown) which is separated from the TFT substrate, that is, the insulating substrate 101, (Not shown) is formed.

In addition, color filter layers (not shown) of red, green, and blue colors are formed in the pixel region of the color filter substrate (not shown). At this time, the black matrix is formed on the color filter substrate between the color filter layers of red, green, and blue colors.

Although not shown in the figure, when the color filter substrate (not shown) and an insulating substrate (not shown) as a thin film transistor substrate are attached together, the black matrix (not shown) For example, the upper portion of the thin film transistor T, the gate wiring 106, and the data wiring 117a. At this time, the line width of the black matrix (not shown) overlapping the data line 117a may be the same or narrower than the data line 117a. In particular, since the common electrode 129a is covered on the data line 117a to shield the light to some extent, the black matrix (not shown) is not completely overlapped on the data line (not shown) .

Although not shown in the figure, an upper alignment film (not shown) is formed on the color filter layer (not shown) to align the liquid crystal in a predetermined direction.

When a data signal is supplied to the pixel electrode 103b through the thin film transistor T, a fringe field is formed between the common electrode 129a and the pixel electrode 103b to which a common voltage is supplied , The liquid crystal molecules arranged in the horizontal direction between the insulating substrate 101 and the color filter substrate (not shown) are rotated by dielectric anisotropy, so that the light transmittance of the liquid crystal molecules transmitted through the pixel region varies depending on the degree of rotation Thereby realizing the gradation.

Therefore, according to the array substrate for an FFC-type liquid crystal display and the method of manufacturing the same according to the present invention, by forming the gate electrode and the pixel electrode contact pattern composed of the metal conductive layer at the time of forming the pixel electrode, A short between the pixel electrode and the common electrode can be formed during the etching process.

According to the array substrate for an FFC-type liquid-crystal display device and the method for fabricating the same, a barrier pattern capable of breaking in a region where a short margin is generated is formed, and when the ITO for common electrode formation is deposited By forming a short between the pixel electrode and the common electrode, the region required for disconnection is extended to the area of the opening area, thereby increasing the aperture ratio and the transmittance.

Further, according to the array substrate for an FFC-type liquid-crystal display device and the method of manufacturing the same, in a region where a short margin between the pixel electrode and the common electrode is required after the pixel electrode contact hole is formed A barrier pattern is formed and an undercut phenomenon occurs in a portion of the gate insulating film under the barrier pattern so that the drain electrode and the pixel electrode are electrically connected through the pixel electrode contact hole at the time of ITO deposition for common electrode formation It is possible to maintain a short between the pixel electrode and the common electrode.

A method of fabricating an array substrate for an FFS type liquid crystal display according to the present invention will be described with reference to FIGS. 8A to 8T.

8A to 8T are cross-sectional views illustrating manufacturing steps of an array substrate for an F-FFS type liquid crystal display according to the present invention.

As shown in FIG. 8A, a plurality of pixel regions including a switching region are defined on a transparent insulating substrate 101, and a first transparent conductive material layer 103 and a first conductive material The metal layers 105 are sequentially deposited by a sputtering method. Here, the first transparent conductive material layer 103 may be formed of any one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). The first conductive metal layer 205 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten At least one selected from the group of conductive metals including titanium (MoTi), copper / moly titanium (Cu / MoTi) is used.

Then, a photo-resist having a high transmittance is applied on the first conductive metal layer 105 to form a first photoresist 107.

8B, the first photoresist layer 107 is subjected to an exposure process using a first diffraction mask 109 composed of a light intercepting portion 109a, a transflective portion 109b and a transmissive portion 109c Go ahead. At this time, the first diffraction mask 109 is a mask capable of adjusting the transmittance using the diffraction phenomenon of light, and includes a slit mask and a half-tone mask. Here, a case where a slit mask is used as a diffraction mask will be described as an example.

The light shielding portion 109a of the first diffraction mask 109 is located above the first photoresist 107 corresponding to the gate wiring, the gate electrode, the gate pad formation region, and the pixel electrode contact pattern formation region, The transflective portion 109b of the one-way diffraction mask 109 is located above the first photoresist 107 corresponding to the pixel electrode formation region.

Next, as shown in FIG. 8C, the first photoresist layer 107 is selectively removed through the exposure process and then the development process to form a gate electrode including a gate electrode and a gate electrode corresponding to a pixel electrode contact pattern formation region The first pattern portion 107a and the second pattern portion 107b corresponding to the pixel electrode formation region are formed.

At this time, since the first pattern portion 107a does not transmit light, the thickness of the first photoresist layer 107 is maintained as it is. However, the second pattern portion 107b is partially removed, do. That is, the first pattern portion 107b has a thickness smaller than that of the second pattern portion 107a.

8D, the first patterned portion 107a and the second patterned portion 107b of the first photoresist layer are patterned using the etching mask to form the first conductive metal layer 105 and the first transparent conductive material layer 103) are selectively etched to form a gate wiring (not shown in FIG. 4, 106), a gate electrode (not shown, see 106a in FIG. 8E) and a pixel electrode 103b protruding from the gate wiring 106 . At this time, a conductive metal layer pattern 105b is also formed on the pixel electrode 103b when the first conductive metal layer 105 and the first transparent conductive material layer 103 are patterned. The pixel electrode 103b is arranged in a pixel region formed by intersecting the gate wiring 106 and the data wiring (not shown), as shown in Fig.

Then, as shown in FIG. 8E, an ashing process is performed to form a portion of the gate line 106 and the gate electrode 106a and a part of the first pattern portion 107a on the pixel electrode contact pattern forming region The second pattern portion 107b on the conductive metal layer pattern 105b is entirely removed to expose the conductive metal layer pattern 105b. At this time, the first pattern portion 107a is also formed on the upper surface of the conductive metal layer pattern 105 overlapping with the pixel electrode contact pattern forming region.

Then, as shown in FIG. 8F, the exposed patterned conductive metal layer pattern 105b is removed using the first patterned portion 107a, which is partially etched by the ashing process, as a blocking film to form the pixel electrode contact pattern 106b, .

Then, the gate wiring 106 and the first pattern portion 107a on the gate electrode 106a and the pixel electrode contact pattern 106b are removed.

Then, after removing the first pattern portion (107a) on the left, to form a gate insulating film 111 made of silicon nitride (SiNx) or silicon oxide (SiO ₂₎ on the substrate surface including the pixel electrode (103b), An amorphous silicon layer (n + or p +) 115 and a second conductive metal layer 117 containing an amorphous silicon layer (a-Si: H) 113 and impurities are sequentially stacked on the gate insulating film 111.

At this time, the amorphous silicon layer (n + or p +) 115 containing the amorphous silicon layer (a-Si: H) 113 and the impurities is deposited by a chemical vapor deposition (CVD) method, 2 conductive metal layer 117 is deposited by a sputtering method.

Although only the chemical vapor deposition method and the sputtering method are described above as the deposition method, other deposition methods may be used if necessary. The second conductive metal layer 117 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten At least one selected from the group of conductive metals including titanium (MoTi), copper / moly titanium (Cu / MoTi) is used.

Next, as shown in FIG. 8G, a photo-resist having a high transmittance is coated on the second conductive metal layer 117 to form a second photoresist layer 119.

Subsequently, the second photoresist layer 119 is exposed using a second diffraction mask 121 composed of a light shielding portion 121a, a transflective portion 121b and a transmissive portion 121c. In this case, the second diffraction mask 121 is a mask capable of adjusting transmittance using diffraction of light, and includes a slit mask and a half-tone mask. Here, a case where a slit mask is used as a diffraction mask will be described as an example.

At this time, the light blocking portion 121a of the second diffraction mask 121 is located above the second photoresist layer 119 corresponding to the barrier pattern formation region together with the data wiring, the source electrode, and the drain electrode formation region, The transflective portion 121b of the second diffraction mask 121 is located above the second photoresist film 119 corresponding to the channel forming region of the thin film transistor and the spacing between the drain electrode forming region and the barrier pattern forming region .

Next, as shown in FIG. 8H, the second photoresist layer 119 is etched through the exposure process and then the development process to form a first pattern portion 119a corresponding to the data line, the source electrode, and the drain electrode formation region And a second pattern portion 119b corresponding to the channel forming region and the spacing portion.

At this time, since the first pattern portion 119a does not transmit light, the thickness of the second photoresist layer 119 is maintained. However, since the second pattern portion 119b transmits a part of the light, do. That is, the second pattern portion 119b is thinner than the first pattern portion 119a.

Next, as shown in FIG. 8I, the first pattern portion 119a and the second pattern portion 119b of the second photosensitive film are patterned using the second conductive metal layer 117, the amorphous silicon A layer 115 and an amorphous silicon layer 113 are successively patterned to form a data line 117a perpendicularly intersecting the gate line 106 and an upper portion of the gate line 106a corresponding to the gate electrode 106a The active layer 113a and the ohmic contact layer 115a are formed.

Then, as shown in 8j, the source electrode and the drain electrode forming region, the first pattern portion 119a corresponding to the data line 117a and a part of the thickness of the first pattern portion 119a are subjected to an ashing process, The second pattern portion 119b corresponding to the spacing portion is completely removed. At this time, the upper surface of the second conductive metal layer 117 overlapping the channel region and the upper portion of the spacing portion is exposed to the outside.

Next, as shown in FIG. 8K, the exposed portion of the second conductive metal layer 117 is etched using the first pattern portion 119a having a part of the thickness removed, as an etching mask, so that the source electrode 117b A drain electrode 117c and a barrier pattern 117d spaced apart from the drain electrode 117c are formed. At this time, a portion of the ohmic contact layer 115a on the channel region and the spacing portion is exposed to the outside.

Subsequently, the ohmic contact layer 115a exposed between the source electrode 117b and the drain electrode 117c is etched to be spaced apart from each other. At this time, a channel region is formed in the active layer 113a under the etched ohmic contact layer 115a.

Then, as shown in Figure 8l, the second photosensitive film of the first removal of the pattern portion (119a), and then, a silicon nitride (SiNx) or silicon oxide (SiO ₂₎ an inorganic insulating material or an insulating organic consisting of the substrate surface A passivation layer 123 is formed by depositing a material on the passivation layer 123 and then a photo-resist having high transmittance is applied on the passivation layer 123 to form a third photoresist layer 125. Here, An example in which an inorganic insulating material made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is used as the passivation film 123 will be described.

Next, as shown in FIG. 8M, a third photoresist pattern 125a is formed by removing the third photoresist 125 by performing a photolithography process technique using an exposure mask (not shown) do.

Next, as shown in FIG. 8N, the passivation film 123 is selectively and primarily dry-etched using the third photoresist pattern 125a as an etch mask so that the drain electrode 117c, the barrier pattern 117d, The pixel electrode contact hole 127 exposing the layer 113a is formed. At this time, the first dry etching process is performed in a state where oxygen gas is increased with an etching gas, for example, (SF ₆ : O ₂ = 1: 3.5), thereby forming the passivation film 123 in a tapered form .

Next, as shown in FIG. 8O, the active layer 113a inside the pixel electrode contact hole 127 is secondarily dry-etched. In this case, the second dry process is performed using an etching gas having an etching selectivity ratio of the gate insulating film 111 and the active layer 113a of about 1: 1.5. Further, in the secondary etching process, the active layer region under the barrier pattern 117d is covered by the barrier pattern 117d, thereby preventing etching.

Next, as shown in FIG. 8P, during the secondary etching process, the exposed gate insulating film 111 is subjected to a third dry etching to expose the upper surface of the pixel electrode contact pattern 106b on the pixel electrode 103b . At this time, the third etching process proceeds using an etching gas having a etching selectivity ratio of the gate insulating film 111 and the active layer 113a of about 1: 1.5. In the third etching process, an undercut phenomenon occurs in the sidewall of the gate insulating film 111 in the pixel electrode contact hole 127 to form an undercut 127a.

8 (q), the third photoresist pattern 125a is removed and a second transparent conductive material layer 129 is formed on the passivation film 123 including the pixel electrode contact hole 127, And is deposited by magnetron sputtering. At this time, as the second transparent conductive material layer 129, any one selected from a transparent material group including indium tin oxide (ITO) and indium zinc oxide (IZO) is used. At this time, the second transparent conductive material layer 129 is electrically connected to the drain electrode 117c exposed in the pixel electrode contact hole 127, the side surface of the active layer 113a, and the pixel electrode contact pattern 106b, Is formed on the passivation film 123 including the exposed upper surface of the pattern 117d.

However, the second transparent conductive material layer 129 is not formed on the side surfaces of the barrier pattern 117d and on the side surfaces of the active layer 113a and the gate insulating film 111 under the barrier pattern 117d. This is because the active layer 113a under the barrier pattern 117d in the pixel electrode contact hole 127 and the side surface portions of the gate insulating film 111 are etched to the side by the undercut phenomenon in the third etching process. Accordingly, the second transparent conductive material layer 129 is formed separately from the pixel electrode contact hole 127.

8R, a photo-resist having high transmittance is applied to the entire surface of the substrate including the second transparent conductive material layer 129 to form a fourth photoresist layer 131. Next, as shown in FIG.

Next, as shown in FIG. 8S, a fourth photoresist pattern 131a is formed by removing the fourth photoresist layer 131 by performing an exposure and a development process by a photolithography process technique using an exposure mask (not shown) do.

8T, the second transparent conductive material layer 129 is etched using the fourth photoresist pattern 131a as a mask to expose the pixel electrode contact holes 121a and 123b together with the plurality of common electrodes 129a, And a pixel electrode connection pattern 129b for electrically connecting the pixel electrode 103b and the drain electrode 117c through the through hole 127.

Although not shown in the figure, the fourth photoresist pattern 131a is removed and a lower orientation film (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 129a, FFS) type liquid crystal display device.

Then, although not shown in the drawing, light is blocked from being transmitted to a region except for the pixel region on a color filter substrate (not shown) bonded to the thin film transistor substrate, that is, the insulating substrate (not shown) A black matrix (BM) (not shown) is formed.

Next, a color filter layer (not shown) of red, green, and blue colors is formed in the pixel region of the color filter substrate (not shown). At this time, the black matrix is located on the color filter substrate between the red, green, and blue color filter layers (not shown).

When the color filter substrate and the insulating substrate, which are the thin film transistor substrates, are attached to each other, the black matrix may include regions except the pixel region of the insulating substrate 101, for example, the thin film transistor T, the gate wiring 106a, And the upper portion of the data line 117a.

Then, although not shown in the drawings, an upper alignment layer (not shown) is formed on the color filter layer to arrange the liquid crystal in a predetermined direction, thereby completing the process of manufacturing the color filter array substrate.

Although not shown in the drawing, a liquid crystal display (FFS) type liquid crystal display device according to the present invention is manufactured by forming a liquid crystal layer (not shown) between the insulating substrate 101 and a color filter substrate .

As described above, at the time of manufacturing the array substrate for an FILM type liquid crystal display device according to the present invention, the gate wiring and the pixel electrode are formed using one mask, and the active layer, the source electrode, And it is possible to manufacture an FFE-type liquid crystal display device by a four-step mask process instead of the conventional five-step mask process, thereby reducing the mask cost, thereby shortening the manufacturing process time and reducing the manufacturing cost .

Further, according to the array substrate for an FPC-type liquid crystal display and the method of manufacturing the same according to the present invention, the pixel electrode contact pattern composed of the metal conductive layer at the time of forming the gate wiring and the pixel electrode is formed, A short between the pixel electrode and the common electrode can be formed during the etching process.

According to the array substrate for an FFC-type liquid-crystal display device and the method for fabricating the same, a barrier pattern capable of breaking in a region where a short margin is generated is formed, and when the ITO for common electrode formation is deposited By forming a short between the pixel electrode and the common electrode, the region required for disconnection is extended to the area of the opening area, thereby increasing the aperture ratio and the transmittance.

Further, according to the array substrate for an FFC-type liquid-crystal display device and the method of manufacturing the same, in a region where a short margin between the pixel electrode and the common electrode is required after the pixel electrode contact hole is formed A barrier pattern is formed and an undercut phenomenon occurs in a portion of the gate insulating film under the barrier pattern so that the drain electrode and the pixel electrode are electrically connected through the pixel electrode contact hole at the time of ITO deposition for common electrode formation It is possible to maintain a short between the pixel electrode and the common electrode.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

101: insulating substrate 103b: pixel electrode
106: gate wiring 106a: gate electrode
106b: Pixel electrode contact pattern 111: Gate electrode
113a: active layer 115a: ohmic contact layer
117a: data line 117b: source electrode
117c: drain electrode 117d: barrier pattern
123: passivation film 127: pixel electrode contact hole 127a: undercut portion 129a: common electrode
129b: pixel electrode connection pattern

Claims (13)

A gate wiring formed on one surface of the substrate in one direction;
A gate insulating film and an active layer formed on the entire surface of the substrate including the gate wiring; a source electrode and a drain electrode formed on the active layer and spaced apart from each other; a barrier pattern spaced apart from the drain electrode;
A data line formed on the gate insulating film and perpendicularly intersecting the gate line;
A pixel electrode formed on the substrate corresponding to a pixel region formed by intersecting the gate wiring and the data wiring;
An island-shaped pixel electrode contact pattern formed on the pixel electrode and overlapping a part of the drain electrode and the barrier pattern;
A passivation film formed on the entire surface of the substrate including the pixel electrode, the data line, and the barrier pattern;
A pixel electrode contact hole formed in the passivation film and a gate insulating film below the passivation film and exposing the pixel electrode, the drain electrode, and the barrier pattern; And
And a pixel electrode connection pattern formed on the passivation film and electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode through the pixel electrode contact hole, And a plurality of pixel electrodes.
The array substrate according to claim 1, wherein the gate wiring is formed of a laminated structure of a transparent conductive material layer pattern and a conductive metal layer pattern, and the pixel electrode is formed of a transparent conductive material layer pattern. The array substrate for a liquid crystal display according to claim 2, wherein the pixel electrode contact pattern is made of the same material as the conductive metal layer pattern constituting the gate wiring. The array substrate for a liquid crystal display according to claim 1, wherein an undercut portion is formed on a sidewall of the gate insulating film under the barrier pattern in the pixel electrode contact hole. The liquid crystal display device according to claim 1, wherein the pixel electrode connection pattern is formed on an upper portion of a passivation film including a drain electrode, an active layer, a gate insulating film inside the pixel electrode contact hole, / RTI > Forming a pixel electrode having a gate wiring, a pixel electrode and a pixel electrode contact pattern in one direction on one surface of a substrate;
Forming a gate insulating film on the entire surface of the substrate including the gate wiring;
A source electrode and a drain electrode formed on the active layer above the gate insulating film and spaced apart from each other and formed above the active layer; and forming a data line perpendicularly intersecting the gate line with a barrier pattern spaced apart from the drain electrode ;
Forming a passivation film on the entire surface of the substrate including the pixel electrode, the data line, and the barrier pattern;
Forming a pixel electrode contact hole exposing the pixel electrode and the drain electrode in the passivation film and a gate insulating film below the passivation film; And
Forming a pixel electrode connection pattern electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode on the passivation film;
Wherein the pixel electrode contact pattern is formed in an island shape overlapping a part of the drain electrode and the barrier pattern.
The display device of claim 6, wherein the gate wiring is formed of a laminated structure of a transparent conductive material layer pattern and a conductive metal layer pattern, the pixel electrode is formed of a transparent conductive material layer pattern, and the pixel electrode contact pattern is formed of a conductive metal layer pattern Wherein the first substrate and the second substrate are bonded to each other. The method of manufacturing an array substrate for a liquid crystal display according to claim 6, wherein an undercut portion is formed on a sidewall of the gate insulating film under the barrier pattern in the pixel electrode contact hole. The liquid crystal display device according to claim 6, wherein the pixel electrode connection pattern is formed on an upper portion of a passivation film including a drain electrode, an active layer, a gate insulating film inside the pixel electrode contact hole, Gt; 7. The method of claim 6, wherein forming the pixel electrode contact hole comprises:
Forming a pixel electrode contact hole exposing the drain electrode, the barrier pattern and the active layer by selectively dry etching the passivation film;
Second dry etching the active layer in the pixel electrode contact hole;
And exposing the upper surface of the pixel electrode contact pattern on the pixel electrode by third dry etching the gate insulating film exposed during the second dry etching process. The method according to claim 10, wherein the passivation film is formed in a tapered shape by performing oxygen gas in an increased amount by an etching gas (SF ₆ : O ₂ = 1: 3.5) during the first dry etching process,
In the second dry etching process, etching is performed using an etching selectivity ratio of the gate insulating film and the active layer of 1: 1.5,
In the third dry etching process, the gate insulating layer exposed during the second dry etching process is etched by a third dry etching using an etch gas having an etch selectivity ratio of the gate insulating layer and the active layer of 1: 1.5, Wherein the step of forming the contact hole exposes the upper surface of the pixel electrode contact pattern on the pixel electrode by causing an undercut phenomenon on the side wall of the gate insulating film of the pixel electrode.

The method according to claim 1,
Wherein the barrier pattern has a first width, an ohmic contact layer having a second width below the barrier pattern, and an active layer having a third width below the ohmic contact layer.
13. The method of claim 12,
And the third width is smaller than the first width and the second width.

Images