KR20130044097A - Array substrate for lcd and fabricating method of the same - Google Patents

Abstract

PURPOSE: An LCD array substrate and a method for fabricating the same are provided to increase an aperture ratio by removing a common line formed between an upper and a lower pixel. CONSTITUTION: A common electrode(129a) is arranged in the upper part of a pixel electrode(105a). A common line(129b) is electrically contacted with the common electrode. The common line passes between the first and the second area of a pixel region. A pixel electrode connection pattern(105c) electrically connects the drain electrode(123d) of a thin film transistor in the first area with the pixel electrode in a second area.

Description

ARRAY SUBSTRATE FOR LCD AND FABRICATING METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a DRD structure AH-IPS mode liquid crystal display device having an improved aperture ratio by changing a pixel structure and a method of manufacturing the same.

Recently, various portable devices such as mobile phones and laptop computers, and information electronic devices that implement high resolution and high quality images such as HDTVs have been developed. The demand for display devices is gradually increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix liquid crystal display device using a thin film transistor (TFT) as a switching element is suitable for displaying a dynamic image.

FIG. 1 schematically illustrates a structure of a conventional active matrix type liquid crystal display device, wherein an active matrix type liquid crystal display device includes a plurality of switches provided at intersections of a plurality of gate lines GL and data lines DL. And a liquid crystal panel 1 formed of an element T. The liquid crystal panel 1 converts a digital video signal into an analog signal based on a gamma voltage, supplies the data signal to the data wiring DL, and simultaneously gates the gate signal. By supplying to GL, the liquid crystal cell C is filled with a data signal.

Specifically, the gate electrode of the switching device T is connected to the gate wiring GL, the source electrode is connected to the data wiring DL, and the drain electrode of the switching device T is connected to the liquid crystal cell C. It is connected to one electrode of the pixel electrode. The common voltage Vcom is supplied to the common electrode of the liquid crystal cell C through the common wiring CL. When the gate signal is applied to the gate line GL, the switching element is turned on to form a channel between the source electrode and the drain electrode to supply a voltage on the data line DL to the pixel electrode of the liquid crystal cell C. In this case, the liquid crystal molecules of the liquid crystal cell C display an image according to incident light while the arrangement is changed by an electric field between the pixel electrode and the common electrode.

Here, the TN mode or IPS mode, which is a driving mode of the liquid crystal display device, is determined according to the positions of the common electrode and the pixel electrode of the liquid crystal panel 1. The IPS mode for forming an electric field has an advantage that the viewing angle is wider than that of the TN mode in which the common electrode and the pixel electrode are disposed to face different substrates to form a vertical electric field.

Recently, AH-IPS (Advanced High-IPS) mode has been proposed in which the above-described IPS mode is improved to maximize luminance characteristics. In the above-described AH-IPS mode, a fringe field is formed by staggering the common electrode and the pixel electrode on different layers on one substrate, thereby achieving higher image quality improvement characteristics than the IPS.

In the AH-IPS mode liquid crystal display, the gate line GL, the common line CL, and the pixel electrode of the liquid crystal panel 1 are formed on the same layer in one mask process using a halftone mask.

On the other hand, the liquid crystal panel 1 of the liquid crystal display device is connected to the gate driver 2 for driving the plurality of gate lines GL, and the data driver 3 for driving the plurality of data lines DL, As liquid crystal display devices become larger and higher in resolution, the number of ICs forming a required driving unit is increasing.

However, since the IC of the data driver 3 is relatively expensive compared to other devices, a technique for reducing the number of ICs has recently been researched and developed in order to lower the production cost of the liquid crystal display device. Instead of doubling the number of lines (GL), the double rate driving (DRD) structure, which reduces the number of data lines (DL) by half and reduces the number of ICs required by half, and realizes the same resolution as before. Proposed.

2 is a diagram illustrating a pixel structure of a DRD structure liquid crystal display device.

As shown in the drawing, in the DRD structure liquid crystal display, a plurality of pixels P1 and P2 arranged on one horizontal line are connected to two gate lines GL1 and GL2 and one data line DL2. A plurality of pixels P3 and P4 arranged on the horizontal line are connected to the two gate lines GL3 and GL4 and the data line DL2.

According to this structure, the DRD structure liquid crystal display minimizes flicker and reduces power consumption. In the case of applying a data signal of the same polarity to one data line during one frame, the column Z-inversion (column) Z-inversion) is implemented.

However, when the AH-IPS mode is applied to the DRD structure liquid crystal display device having such a structure, the gate line GL and the common line CL are formed on the same layer. As shown in FIG. It is arranged between the wiring GL2 and the other gate wiring GL3.

3 is a plan view showing a part of an array substrate for a conventional DRD structure AH-IPS mode liquid crystal display device.

As shown in the drawing, an array substrate of a conventional DRD structure AH-IPS mode liquid crystal display device includes a plurality of gate wirings 13a and 13a 'formed in parallel with each other and extending in one direction on the substrate 11, and the gate wirings. A plurality of data wires 23a are formed so as to intersect with (13a, 13a ') and define a pixel area. In the pixel region, a thin film transistor T including a gate electrode 13b, an active layer (not shown), a source electrode 23c and a drain electrode 23d connected to the extension wiring 23b of the data wiring 23a is formed. It is provided.

In addition, a transparent pixel electrode 15 is disposed on the front surface of the pixel region with a space separated from the gate wiring 13a and the data wiring 23a, and an insulating film (not shown) is disposed on the pixel electrode 15. In addition, a plurality of rod-shaped transparent common electrodes 29a are disposed.

The pixel electrode 15 is electrically connected to the pixel electrode connection pattern 29b connected to the drain electrode 23d.

Further, both ends of the plurality of rod-shaped common electrodes 29a are electrically connected to the common electrode connection pattern 29b disposed in parallel with the gate wiring 13a, and the common electrode connection pattern 29b is a contact hole. It is connected to the common wiring 13c via 29c.

Here, the common wiring 13c is formed in the horizontal direction between the gate wirings 13a and 13a 'and the data wiring extension wirings 23b and 23b'. This is because two pixels are connected to one data line in one horizontal line according to the DRD structure, and in order to implement the AH-IPS structure through a 4 mask process, the gate lines 13a and 13a 'and the common wiring ( This is because the common wiring 13c cannot be formed in the vertical direction because 13c is formed on the same layer.

According to this structure, the conventional DRD structure AH-IPS mode liquid crystal display device has a problem that the common wiring 13c is disposed between the upper and lower pixels, and the aperture ratio of the liquid crystal panel is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. In the liquid crystal display device having a structure in which one data line is shared on the same horizontal line, the AH- improved the problem of a decrease in the aperture ratio due to the common wiring formed in the horizontal direction of the array substrate. It is an object of the present invention to provide an array substrate for an IPS mode liquid crystal display device.

In order to achieve the above object, an array substrate for a DRD structure AH-IPS mode liquid crystal display device according to a preferred embodiment of the present invention, the substrate; A plurality of gate wirings formed in one direction on the substrate; A plurality of data lines crossing the gate lines; A pixel region defined as first and second regions at intersections of the gate and data lines; A thin film transistor electrically connected to the pixel electrode and the adjacent data line and the source electrode respectively formed in the first and second regions; A protective film formed on the entire surface of the substrate including the pixel area; A common electrode formed on the passivation layer and facing the pixel electrode; A common wiring in electrical contact with the common electrode and formed to pass between the first and second regions; And a pixel electrode connection pattern electrically connecting the drain electrode of the thin film transistor of the first region and the pixel electrode of the second region.

The gate electrode has at least a double structure having a transparent conductive film thereunder.

The pixel connection pattern is formed on the same layer as the transparent conductive film.

The common wiring is formed on the same layer as the data line.

The common wiring may be electrically connected to the common electrode by a first contact hole formed between the spaces between pixels.

The pixel electrode connection pattern may electrically connect the thin film transistor and the pixel electrode to be orthogonal to the common wiring.

The pixel electrode connection pattern may be electrically connected to the common electrode by a second contact hole formed at the same time as the first contact hole.

In order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device according to a preferred embodiment of the present invention includes a pixel region defined as first and second regions at intersections of gates and data lines, A pixel electrode formed in each of the first and second regions, a thin film transistor electrically connected to a neighboring data line and a source electrode, and a pixel electrode electrically connecting the thin film transistor of the first region and the pixel electrode of the second region. A method of manufacturing an array substrate for a DRD structure AH-IPS mode liquid crystal display device having a connection pattern, comprising: a gate wiring, a pixel electrode, and the pixel electrode connection pattern having at least a double structure of a metal film and a transparent conductive film in one direction on a substrate; Forming a; Depositing and patterning an insulating film, an amorphous silicon film, an amorphous silicon film containing an impurity, and a metal film on the entire surface of the substrate to form a thin film transistor, data wiring, and common wiring; Forming a passivation layer on an entire surface of the substrate on which the thin film transistor, data wiring and common wiring are formed; Forming a contact hole exposing the pixel electrode connection pattern and the common wiring; And forming a common electrode by depositing and patterning a transparent conductive film on the entire surface of the substrate including the contact hole, and at the same time, electrically contacting the thin film transistor and the pixel electrode connection pattern, and the common wiring and the common electrode.

The forming of the gate wiring, the pixel electrode, and the pixel electrode connection pattern may include forming a transparent conductive film, a metal film, and a photoresist film on a substrate; Selectively removing the photoresist film through a diffraction mask to form the photoresist pattern on the region where the gate wiring and the gate electrode extending from the gate wiring are to be formed, and the metal film pattern on the region where the pixel electrode and the pixel electrode connection pattern are to be formed. Forming a; Forming the pixel electrode and the pixel electrode connection pattern using the photoresist pattern and the metal film pattern as masks; Removing the photoresist pattern to form the gate wiring and the gate electrode.

The forming of the thin film transistor, the data line, and the common line may include depositing an insulating film, an amorphous silicon film, an amorphous silicon film, and a metal film containing impurities on the entire surface of the substrate on which the gate wiring, the pixel electrode, and the pixel electrode connection pattern are formed. step; Forming a photoresist pattern on a region where the thin film transistor is to be formed and a region where the data wiring and the common wiring are to be formed using a diffraction mask; And forming the thin film transistor, the data wiring, and the common wiring using the photoresist pattern as a mask.

According to a preferred embodiment of the present invention, by forming a connection pattern of pixel electrodes of each pixel and electrically connecting the thin film transistors of neighboring pixels, a common wiring provided in another layer can be formed in the vertical direction between each pixel. . As a result, the aperture ratio of the DRD structure AH-IPS mode liquid crystal display device can be improved.

1 is a view schematically showing a structure of a conventional active matrix liquid crystal display device.
2 is a diagram illustrating a pixel structure of a DRD structure liquid crystal display device.
3 is a plan view showing a part of an array substrate for a conventional DRD structure AH-IPS mode liquid crystal display device.
4A is a plan view of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4B is an enlarged view of a portion of FIG. 4A.
FIG. 5 is a cross-sectional view of the VV ′ and VI-VI ′ portions of the array substrate illustrated in FIG. 4B.
6A through 6M are cross-sectional views illustrating a manufacturing process of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, a structure of an array substrate for a DRD structure AH-IPS mode liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

4A is a plan view of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4B is an enlarged view of a portion of FIG. 4A.

As shown, the array substrate for the DRD structure AH-IPS mode liquid crystal display device of the present invention is formed so as to intersect the gate wiring 103a and the gate wiring 103a formed in parallel in one direction on the substrate 111. A plurality of data lines 123a are formed to define the pixel region. The pixel region includes a thin film transistor T including a gate electrode 103b, an active layer (not shown), a source electrode 123c connected to the data extension wiring 123b, and a drain electrode 123d. In addition, a transparent pixel electrode 105a is disposed on a front surface of the pixel region with a space separated from the gate wiring 103a and the data wiring 123a, and an insulating film (not shown) is interposed between the pixel electrode 105a and the pixel electrode 105a. The plurality of rod-shaped transparent common electrodes 129a are disposed.

In addition, the pixel electrode 105a is electrically connected by the pixel electrode connection pattern 105c connected to the drain electrode 123d described above. Particularly, the pixel electrode connection pattern 105c of the predetermined pixel P2 corresponds to the corresponding pixel electrode connection pattern 105c. It extends to the transistor T formed adjacent to the neighboring pixel P1 and is electrically connected to the transistor T.

That is, the pixel electrode of each pixel is electrically connected to the thin film transistors of neighboring pixels through the pixel electrode connection pattern instead of the nearest thin film transistor.

In addition, the plurality of bar-shaped common electrodes 129a are formed by connecting the pixels P1 and P2 to each other. In the drawing, the long axis of the bar shape is formed in a horizontal direction, that is, in a direction parallel to the gate wiring 103a. However, the common electrode 129a and the data wiring 123a may be formed in the vertical direction so as to be parallel to each other.

Here, the common line 129b disposed perpendicular to the gate line 103a passes through the upper portion of the gate line 103a at the center of the common electrode 129a and is disposed through the contact hole 129c disposed between the upper and lower pixels. The common electrode 129a is in electrical contact with each other. According to this structure, the common wiring 129b is formed on the same layer as the data wiring 123a between two neighboring pixels P1 and P2 sharing the common electrode 129a. This arrangement allows the common wiring 129b to be formed in the vertical direction, and the aperture ratio is improved by eliminating the common space between the two spaces adjacent to each other in the vertical direction.

In addition, when a data signal of the same polarity is applied to one data line during one frame, the device is driven at a low power by operating as a column Z-inversion. Hereinafter, a structure of an array substrate for a DRD structure AH-IPS mode liquid crystal display device according to an embodiment of the present invention will be described with reference to the cross section of the array substrate illustrated in FIGS. 4A and 4B.

FIG. 5 is a cross-sectional view of the V-V ′ and VI-VI ′ portions of the array substrate illustrated in FIG. 4B.

As shown in the drawing, an array substrate for a DRD structure AH-IPS mode liquid crystal display device includes a gate electrode 103b connected to a gate wiring, an active layer 109a, a source electrode 123b, and a drain electrode 123c sequentially. It includes a thin film transistor (T) of the stacked form.

Here, a transparent conductive layer pattern 105a made of a transparent conductive material, for example, ITO, is formed under the gate wiring and the gate electrode 103 extending from the gate wiring to form a double stacked structure. In this case, the transparent conductive layer pattern 105a may be formed on the whole or part of the lower portion of the gate wiring including the gate electrode 103b.

In the pixel region adjacent to the thin film transistor T, the pixel electrode 105b having a large area is disposed on the same layer as the gate electrode 103b, and the gate insulating film 107 is disposed above the pixel electrode 105b. A plurality of rod-shaped transparent common electrodes 123a are disposed with the passivation layer 119 therebetween. In this case, the plurality of transparent common electrodes 123a having a rod shape are formed to be spaced apart from each other by a predetermined interval, and are formed in a horizontal or vertical direction.

The pixel electrode 105b described above is connected to the pixel electrode connection pattern 123e that is in contact with the drain electrode 123c of the thin film transistor T through the pixel electrode contact hole formed in the passivation layer 119 and the gate insulating layer 107. It is electrically connected to the drain electrode 123c.

In addition, the common wiring 129b is formed of a data metal in contact with the common electrode connection pattern 129c through a contact hole on the passivation layer 119. The gate insulating layer 107, the active pattern 109b, and the ohmic contact pattern 111b are sequentially stacked below the common wiring 129b.

Furthermore, both ends of the plurality of rod-shaped common electrodes 123a are electrically connected to the common electrode connection pattern 129c disposed in parallel with the data lines. In the common electrode connection pattern 129c, the plurality of common electrodes 123a supply a reference voltage for driving the liquid crystal, that is, a common voltage Vcom, to each pixel.

The pixel electrode 105b overlaps the plurality of common electrodes 123a in the pixel area with the passivation layer 119 therebetween to form a fringe field. In this case, a storage capacitance Cst is formed between the lower large area pixel electrode 105b and the plurality of common electrodes 123a.

In this way, when the data signal is supplied to the pixel electrode 105b through the thin film transistor T, the common electrodes 123a supplied with the common voltage form a fringe field, thereby forming an array substrate and a color filter substrate ( Liquid crystal molecules arranged in the horizontal direction between the (not shown) is rotated by the dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

Hereinafter, a manufacturing method of an array substrate for a DRD structure AH-IPS mode liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

6A through 6M are cross-sectional views illustrating a manufacturing process of an array substrate for a DRD structure AH-IPS mode liquid crystal display according to an exemplary embodiment of the present invention.

First, as illustrated in FIG. 6A, a plurality of pixel regions including a switching region are defined on the transparent substrate 101, and the transparent conductive material layer 105 and the first conductive metal layer 103 are conventionally sputtered. By deposition. In this case, the material constituting the transparent conductive layer 105 may be any one selected from the group including indium tin oxide (ITO), indium zinc oxide (IZO), and carbon nanotube (CNT). In addition, the metal used for the first conductive metal layer 103 may include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and molybdenum tungsten (MoW). At least one selected from the group of conductive metals including molybdenum (MoTi) and copper / mortium (Cu / MoTi) is applied.

Next, after the first photoresist is applied on the first conductive metal layer 103, the first photoresist is exposed and developed through a photolithography process technique using a first exposure mask to expose the first photoresist. Resist patterns 106a and 106b are formed.

In this case, the first photoresist pattern is formed using a diffraction mask including a light blocking portion, a transflective portion, and a transmissive portion. Arranged correspondingly, the exposure and development processes are performed to form a shape as shown in FIG. 6B. Therefore, a half-tone mask or the like may be used as the first exposure mask.

Subsequently, as illustrated in FIG. 6C, an exposure process is performed, and then a first photoresist pattern is selectively removed through a developing process, thereby forming a photoresist pattern of the gate forming region 106a and a pixel electrode and pixel electrode connection pattern forming region. The metal layer on 103e is formed.

Next, as shown in FIG. 6D, the remaining photoresist pattern and the metal layer on the pixel electrode and the pixel electrode connection pattern formation region 103e are used as masks to protrude from the gate wiring simultaneously with the gate wiring (not shown). The gate electrode 103b, the transparent and large area of the pixel electrode 105b under the gate electrode 103b, and the pixel electrode connection pattern 105c are simultaneously formed.

As a result, the gate wiring, the gate electrode 103b and the lower transparent conductive layer pattern 105a are simultaneously formed together with the pixel electrode 105b of the large area. In this case, the pixel electrode 105b is disposed on the unit pixel area. In this case, the unit pixel area includes first and second areas.

Subsequently, as shown in FIG. 6E, a gate insulating film 107 made of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate including the pixel electrode 105b and the pixel electrode connection pattern 105c. An amorphous silicon layer (a-Si: H) 109, an amorphous silicon layer (n + or p +) 111 containing impurities, and a second conductive metal layer 113 are sequentially stacked on the gate insulating layer 107. .

In this case, the amorphous silicon layer (a-Si: H) 109 and the amorphous silicon layer (n + or p +) 111 containing impurities are deposited by Chemical Vapor Deposition (CVD), and the second conductive metal layer is deposited. 113 is deposited by a sputtering method. At this time, as the second conductive metal layer 113, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), molybdenum At least one selected from the group of conductive metals including (MoTi) and copper / mortitanium (Cu / MoTi) is used.

Next, as shown in FIG. 6F, a photoresist having high transmittance is coated on the second conductive metal layer 113 to form a second photoresist film 115.

Next, an exposure process is performed on the third photoresist film 115 using the third exposure mask 117 including the light blocking portion 117a, the transflective portion 117b, and the transmissive portion 117c. In this case, the light blocking portion 117a of the diffraction mask 117 is positioned above the third photoresist film 115 corresponding to the source and drain electrode formation regions, and the transflective portion 117b of the diffraction mask 117 is a thin film. It is located above the third photoresist film 115 corresponding to the channel formation region of the transistor.

Here, the illustrated second exposure mask 117 may use a diffraction mask using a diffraction effect of the above-described light, for example, a half-ton mask or other mask.

 Subsequently, as shown in FIG. 6G, the exposure process and the development process are performed to etch the third photoresist film 115 to form the source and drain electrode forming regions 115a and the channel forming regions 115b. At this time, since the source and drain electrode forming regions 115a are not transmitted through the light, the thickness of the third photoresist film 115 is maintained as it is, but the channel forming regions 115b have a predetermined thickness through which some of the light is transmitted. Is removed. That is, the channel forming region 115b has a thickness thinner than that of the source and drain electrode forming region 115a.

Next, using the photoresist film on the source and drain electrode forming region 115a and the channel forming region 115b as a mask, the second conductive metal layer 113, the amorphous silicon layer 111 containing impurities and the amorphous silicon layer ( 109 is sequentially patterned to form an active layer 109a and an ohmic contact layer 111a on the gate insulating film 107 corresponding to the gate electrode 103b.

At this time, the active pattern 109b and the ohmic contact pattern 111b are formed in the region where the common wiring is formed.

Subsequently, as shown in 6h, the channel forming region 115b is completely removed along with a part of the thickness of the source and drain electrode forming region 115a through an ashing process. In this case, an upper surface of the second conductive metal layer 113 overlapping the channel region is exposed to the outside.

Next, as shown in FIG. 6I, the exposed portion of the second conductive metal layer 113 is etched by using the source and drain electrode forming regions 115a of the third photoresist film, which is partially removed, as a mask. A source electrode 123a and a drain electrode 123b spaced apart from each other are formed together with a data line (not shown) that vertically intersects the wiring (not shown). At the same time, the common wiring 129b is also formed.

Subsequently, the ohmic contact layer 111a exposed between the source electrode 123a and the drain electrode 123b is also etched and spaced apart from each other. In this case, a channel region is formed in the active layer 109a under the etched ohmic contact layer 111a.

Next, as shown in FIG. 6J, after the source and drain electrode forming regions 115a of the third photoresist film are completely removed, an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate to form a protective film 119. Subsequently, a fourth photoresist layer (not shown) is formed by applying a photoresist having high transmittance on the passivation layer 119.

Subsequently, although not shown in the figure, an exposure and development process are performed by a photolithography process technique using a third exposure mask to remove the fourth photoresist film 119 to form a fourth photoresist film pattern.

Next, as shown in FIG. 6K, the passivation layer 119 and the gate insulating layer 107 below are selectively etched using the fourth photoresist layer pattern (not shown) as a mask to extend from the pixel electrode 105b. The first contact hole 121a exposing the pixel electrode connection pattern 105c and the second contact hole 121b exposing the upper portion of the common wiring 129b are simultaneously formed. At this time, when the first contact hole 121a is formed, the drain electrode 123b is also exposed.

Subsequently, the fourth photoresist film pattern is removed, and indium tin oxide (ITO), indium zinc oxide (IZO), and carbon carbon (CNT) are disposed on the passivation layer 119 including the first and second contact holes 121a and 121b. The second transparent conductive layer 123 is deposited by sputtering using any one selected from the group including Nano Tube.

Next, although not shown, a fifth photoresist film (not shown) is formed by applying a high transmittance photo-resist on the second transparent conductive material layer 123.

Subsequently, although not shown in the drawing, the fifth photoresist film pattern is removed by performing the exposure and development processes by a photolithography process technique using a fourth exposure mask (not shown) to remove the fifth photoresist film (not shown). (Not shown) is formed.

Next, as illustrated in FIG. 6M, the second transparent conductive layer 123 is etched using the fifth photoresist layer pattern (not shown) as a mask to form the pixel electrode together with the plurality of common electrodes 123a. The pixel electrode connection pattern 123b electrically connected to the pixel electrode 105b through the contact hole 121a and the transparent conductive layer pattern 105a on the gate wiring 103a through the gate wiring contact hole 121b. And gate connection pattern 123c electrically connected to each other.

Subsequently, although not shown, the fifth photoresist film pattern (not shown) is removed to complete the manufacturing process of the array substrate for the DRD structure AH-IPS mode liquid crystal display device according to the present invention.

Subsequently, although not shown in the drawing, the DRD structure AH-IPS mode liquid crystal display device according to the present invention is completed by performing a process of filling the liquid crystal layer between the array substrate and the color filter substrate together with the color filter substrate manufacturing process.

Therefore, according to the present invention, a common wiring is formed in the vertical direction across the center of two pixels by connecting the connection pattern of pixel electrodes with a thin film transistor adjacent to a neighboring pixel in a DRD structure AH-IPS mode liquid crystal display array substrate. By removing the common wiring in the space between the upper and lower pixels, the aperture ratio of the liquid crystal display can be increased.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the claims and the appended claims.

103a: gate wiring 103b: gate electrode
105a: pixel electrode 105c: pixel electrode connection pattern
123a: Data Wiring 123b: Data Extension Wiring
123c: source electrode 123d: drain electrode
123e: first contact hole 129a: common electrode
129b: common wiring 129c: second contact hole
T: thin film transistor

Claims (10)

Board;
A plurality of gate wirings formed in one direction on the substrate;
A plurality of data lines crossing the gate lines;
A pixel region defined as first and second regions at intersections of the gate and data lines;
A thin film transistor electrically connected to the pixel electrode and the adjacent data line and the source electrode respectively formed in the first and second regions;
A protective film formed on the entire surface of the substrate including the pixel area;
A common electrode formed on the passivation layer and facing the pixel electrode;
A common wiring in electrical contact with the common electrode and formed to pass between the first and second regions; And
And a pixel electrode connection pattern electrically connecting the drain electrode of the thin film transistor of the first region and the pixel electrode of the second region. The method of claim 1,
The gate electrode
An array substrate for a liquid crystal display device, characterized in that it has a dual structure having a transparent conductive film at the bottom. 3. The method of claim 2,
And the pixel connection pattern is formed on the same layer as the transparent conductive film. The method of claim 1,
And the common wiring is formed on the same layer as the data line. The method of claim 1,
And the common wiring is electrically connected to the common electrode by a first contact hole formed between the spaces between pixels. The method of claim 5, wherein
And the pixel electrode connection pattern electrically connects the thin film transistor and the pixel electrode to be orthogonal to the common wiring. The method according to claim 6,
And the pixel electrode connection pattern is electrically connected to the common electrode by a second contact hole formed simultaneously with the first contact hole. A pixel region defined as a first and a second region at an intersection point of a gate and a data line, a pixel electrode formed at each of the first and second regions, and a thin film transistor electrically connected to a neighboring data line and a source electrode; And a pixel electrode connection pattern for electrically connecting the thin film transistor in the first region and the pixel electrode in the second region.
Forming a gate wiring, a pixel electrode, and the pixel electrode connection pattern having at least a double structure of a metal film and a transparent conductive film on a substrate in one direction;
Depositing and patterning an insulating film, an amorphous silicon film, an amorphous silicon film containing an impurity, and a metal film on the entire surface of the substrate to form a thin film transistor, data wiring, and common wiring;
Forming a passivation layer on an entire surface of the substrate on which the thin film transistor, data wiring and common wiring are formed;
Forming a contact hole exposing the pixel electrode connection pattern and the common wiring; And
Forming a common electrode by depositing and patterning a transparent conductive film on the entire surface of the substrate including the contact hole, and at the same time, electrically contacting the thin film transistor and the pixel electrode connection pattern, and the common wiring and the common electrode.
Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 8,
The forming of the gate wiring, the pixel electrode, and the pixel electrode connection pattern may include:
Forming a transparent conductive film, a metal film and a photoresist film on the substrate;
Selectively removing the photoresist film through a diffraction mask to form the photoresist pattern on the region where the gate wiring and the gate electrode extending from the gate wiring are to be formed, and the metal film pattern on the region where the pixel electrode and the pixel electrode connection pattern are to be formed. Forming a;
Forming the pixel electrode and the pixel electrode connection pattern using the photoresist pattern and the metal film pattern as masks; And
Removing the photoresist pattern to form the gate wiring and the gate electrode
Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 8,
Forming the thin film transistor, data wiring and common wiring,
Depositing an insulating film, an amorphous silicon film, an amorphous silicon film containing an impurity, and a metal film on an entire surface of the substrate on which the gate wiring, the pixel electrode, and the pixel electrode connection pattern are formed;
Forming a photoresist pattern on a region where the thin film transistor is to be formed and a region where the data wiring and the common wiring are to be formed using a diffraction mask; And
Forming the thin film transistor, data wiring, and common wiring using the photoresist pattern as a mask;
Method of manufacturing an array substrate for a liquid crystal display device comprising a.

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