KR102262775B1 - Display device - Google Patents

Abstract

A display device according to an embodiment of the present invention is disclosed. Disclosed is a display device capable of improving an aperture ratio of a pixel by disposing storage capacitors adjacent to each other and sharing a common line. In the display device of the present invention, the first storage capacitor and the second storage capacitor are disposed between the first pixel electrode and the second pixel electrode, and the first storage capacitor is positioned opposite the first pixel electrode with respect to the vertical common line. , the second storage capacitor is positioned opposite to the second pixel electrode with respect to the vertical common line. Also, a first bridge pixel electrode connecting the first pixel electrode from the first storage capacitor and a second bridge pixel electrode connecting the second pixel electrode from the second storage capacitor are disposed.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device capable of improving an aperture ratio.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are being developed. A liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is formed for each pixel. Pixels of the liquid crystal display may be divided into R sub-pixels, G sub-pixels, B sub-pixels, and W sub-pixels to realize color and increase luminance. Hereinafter, a display device in which pixels are divided into RGBW sub-pixels is referred to as an “RGBW type display device”.

A liquid crystal display device includes a liquid crystal display panel, a backlight unit irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying data voltages to data lines of the liquid crystal display panel, and a gate line of the liquid crystal display panel. and a gate drive IC for supplying a gate pulse (or scan pulse) to the cells (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of a backlight unit, and the like.

The liquid crystal display uses an inversion method that reverses the polarities of data voltages charged in neighboring sub-pixels and periodically inverts the polarities of the data voltages to reduce direct current afterimage and prevent liquid crystal deterioration. is being driven In most liquid crystal displays, a horizontal and vertical 1-dot inversion method or a horizontal 1-dot and vertical 2-dot inversion method is applied. One dot means one sub-pixel.

A storage capacitor is provided in each of the sub-pixels to maintain driving of the liquid crystal. In the case of a structure in which storage capacitors provided in vertical and adjacent sub-pixels face each other, it is necessary to secure a storage capacitor area. In this case, there is a problem in that the area between the sub-pixels adjacent vertically is widened, and thus the aperture ratio is lowered. In addition, as the demand of users for a high-quality liquid crystal display increases, it is necessary to achieve a high aperture ratio by changing the design of the sub-pixel.

Accordingly, the present invention provides a display device capable of improving an aperture ratio by disposing storage capacitors adjacent to each other. In addition, the present invention provides a display device capable of improving an aperture ratio by sharing a common line.

In order to achieve the above object, a display device according to an exemplary embodiment includes a first pixel and a second pixel. The first pixel includes a first pixel electrode, a first common electrode forming an electric field with the first pixel electrode, and a first storage capacitor, and the second pixel includes a second pixel electrode and an electric field with the second pixel electrode a second common electrode forming the second common electrode; and a second storage capacitor. and a first pixel electrode and the second pixel electrode are disposed between adjacent first and second data lines, and a vertical common line parallel to the data lines is disposed between the first pixel electrode and the second pixel electrode, First and second gate lines crossing the data lines are disposed between the first pixel electrode and the second pixel electrode. The first storage capacitor and the second storage capacitor are disposed between the first pixel electrode and the second pixel electrode, the first storage capacitor is positioned opposite the first pixel electrode with respect to the vertical common line, and the second storage capacitor includes: It is positioned opposite to the second pixel electrode with respect to the vertical common line. A first bridge pixel electrode connecting the first pixel electrode from the first storage capacitor and a second bridge pixel electrode connecting the second pixel electrode from the second storage capacitor are disposed, the first bridge pixel electrode and the second The bridge pixel electrode intersects the vertical common line.

For example, the first pixel includes a first TFT positioned at the intersection of the first data line and the first gate line, and the second pixel includes a second TFT positioned at the intersection of the second data line and the second gate line. including TFT.

For example, a first common line parallel to the first gate line is disposed opposite the first gate line with the first pixel electrode interposed therebetween, and the second common line is disposed opposite the second gate line with the second pixel electrode interposed therebetween. A second common line parallel to the second gate line is disposed. The first common line is connected to the first common electrode, and the second common line is connected to the second common electrode.

For example, the first bridge pixel electrode and the first pixel electrode are integrally formed, and the second bridge pixel electrode and the second pixel electrode are integrally formed.

For example, the first gate line and the second gate line are positioned between the first storage capacitor and the second storage capacitor.

Also, in order to achieve the above object, a display device according to an exemplary embodiment includes a first pixel and a second pixel electrode. The first pixel includes a first pixel electrode, a first common electrode forming an electric field with the first pixel electrode, and a first storage capacitor. The second pixel includes a second pixel electrode, a second common electrode forming an electric field with the second pixel electrode, and a second storage capacitor. A data line is disposed between the first pixel electrode and the second pixel electrode, first and second gate lines crossing the data line are disposed between the first pixel electrode and the second pixel electrode, and the first pixel electrode and the second pixel electrode First and second common lines crossing the data line are disposed between the two pixel electrodes. The first storage capacitor is disposed between the first gate line and the first pixel electrode, the second storage capacitor is disposed between the second gate line and the second pixel electrode, and the first storage capacitor and the second storage capacitor are the data line. are located on opposite sides of each other.

For example, the first pixel includes a first TFT positioned at the intersection of the data line and the first gate line, and the second pixel includes the second TFT positioned at the intersection of the data line and the second gate line. , the first TFT and the second TFT share a data line.

For example, a first gate line and a second gate line are positioned between the first common line and the second common line.

In addition, in order to achieve the above object, a display device according to an embodiment of the present invention includes a first pixel and a second pixel. The first pixel includes a first pixel electrode, a first common electrode forming an electric field with the first pixel electrode, and a first storage capacitor. The second pixel includes a second pixel electrode, a second common electrode forming an electric field with the second pixel electrode, and a second storage capacitor. A data line is disposed between the first pixel electrode and the second pixel electrode, and first and second gate lines crossing the data line are disposed between the first pixel electrode and the second pixel electrode. A common line is disposed between the first gate line and the second gate line, and the common line is included in the first storage capacitor and the second storage capacitor. The first storage capacitor is disposed between the first gate line and the first pixel electrode, the second storage capacitor is disposed between the second gate line and the second pixel electrode, and the first storage capacitor and the second storage capacitor are the data line. are located on opposite sides of each other.

For example, the first pixel includes a first TFT positioned at the intersection of the data line and the first gate line, and the second pixel includes the second TFT positioned at the intersection of the data line and the second gate line. , the first TFT and the second TFT share a data line.

For example, the first storage capacitor includes a drain electrode of the first TFT and a common line, and the second storage capacitor includes a drain electrode of the second TFT and a common line.

For example, the auxiliary common line is parallel to the data line and adjacent to the data line with the first pixel and the second pixel therebetween, and the auxiliary common line is connected to the common line through a contact hole.

For example, a vertical common line surrounding the first pixel electrode and the second pixel electrode is included, and the vertical common line includes an extension overlapping the second gate line.

In a display device according to an embodiment of the present invention, the TFT and the storage capacitor are disposed adjacent to each other based on a vertical common line, and the TFT and the storage capacitor are disposed adjacent to each other based on the vertical common line using a bridge pixel electrode. connected to the pixel electrode of the pixel. Accordingly, there is an advantage that the aperture ratio can be improved by reducing the distance between the pixels.

In addition, in the display device according to an exemplary embodiment of the present invention, one common line is disposed between the gate lines so that two pixels share a common line in order to reduce the distance between the pixels having a vertical relationship. Accordingly, there is an advantage that an aperture ratio of the pixels can be improved by reducing the distance between the pixels.

1 is a view showing a display device according to an embodiment of the present invention;
2 is a circuit diagram showing a portion of a pixel array according to an embodiment of the present invention;
3 is a plan view illustrating a structure of a pixel array of a display device according to a first embodiment of the present invention;
Fig. 4 is a cross-sectional view taken along line II' of Fig. 3;
5 is a cross-sectional view taken along II-II' of FIG. 3;
6 is a plan view illustrating a structure of a pixel array of a display device according to a second embodiment of the present invention;
7 is a cross-sectional view taken along III-III' of FIG.
8 is a plan view illustrating a structure of a pixel array of a display device according to a third exemplary embodiment of the present invention;
9 is a cross-sectional view taken along line IV-IV' of FIG. 8;
10 is a plan view illustrating a pixel array structure of a display device according to a fourth embodiment of the present invention;
11 is a cross-sectional view taken along line V-V' of FIG. 10;
12 is a view comparing the pixel array of the conventional display device and the pixel array of the display device according to the first embodiment of the present invention.
13 is a view showing aperture ratios of pixels of a display device according to second to fourth embodiments of the present invention;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The display device of the present invention may be implemented as a flat panel display device capable of realizing color, such as a liquid crystal display device (LCD), an organic light emitting diode display device (OLED Display), and a plasma display panel (PDP). Hereinafter, embodiments of the present invention will be described focusing on the liquid crystal display, but it should be noted that the present invention is not limited to the liquid crystal display. For example, the arrangement of RGBW sub-pixels of the present invention is applicable to an organic light emitting diode display.

1 is a view showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , a display device according to the present invention includes a display panel 10 having a pixel array formed thereon, and a display panel driving circuit for writing input image data to the display panel 10 . A backlight unit for uniformly irradiating light to the display panel 10 may be disposed under the display panel 10 .

The display panel 10 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. The pixel array of the display panel 10 includes pixels arranged in a matrix form by a cross structure of data lines D1 to Dm and gate lines G1 to Gn.

Data lines D1 to Dm+1, gate lines G1 to G2n, TFTs, the pixel electrode 1 connected to the TFT, and the pixel electrode 1 are connected to the lower substrate of the display panel 10 . and a storage capacitor (Cst). Each of the pixels adjusts the amount of light transmission by using liquid crystal molecules driven by the voltage difference between the pixel electrode 1 that charges the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied. Displays images of video data. Each of the pixels is divided into RGBW sub-pixels. The RGBW sub-pixels may be arranged in the form shown in FIG. 2 .

A color filter array including a black matrix and a color filter is formed on the upper substrate of the display panel 10 . The common electrode 2 is formed on the upper substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as mode, it is formed on the lower substrate together with the pixel electrode. A polarizing plate is attached to each of the upper and lower substrates of the display panel 10 , and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display panel driving circuit writes data to the pixels. The display panel driving circuit includes a data driver 12 , a gate driver 14 , and a timing controller 20 .

The data driver 12 includes a plurality of source drive ICs. Data output channels of the source drive ICs are connected to data lines D1 to Dm of the pixel array. The total number of data output channels of the source drive ICs is reduced to half of the total number of data lines due to the pixel array structure shown in FIG. 2 . Accordingly, the present invention can lower the cost of the display device.

The data driver 12 receives input image data from the timing controller 20 . The digital video data transmitted to the data driver 12 includes R data, G data, B data, and W data. The data driver 12 converts RGBW digital video data of an input image into positive/negative gamma compensation voltages under the control of the timing controller 20 to output positive/negative data voltages. The output voltage of the data driver 12 is supplied to the data lines D1 to Dm.

The gate driver 14 sequentially supplies gate pulses to the gate lines G1 to Gn under the control of the timing controller 20 . The gate pulse output from the gate driver 14 is synchronized with the positive/negative video data voltage to be charged in the pixels.

The timing controller 20 converts RGB data of an input image received from the host system 30 into RGBW data and transmits the converted RGB data to the data driver 12 . As an interface for data transmission between the timing controller 20 and the source drive ICs of the data driver 12 , a mini low-voltage differential signaling (LVDS) interface or an embedded panel interface (EPI) interface may be applied. The EPI interface is a Korean patent application 10-2008-0127458 (2008-12-15), US application 12/543,996 (2009-08-19) filed by the applicant of the present application, and a Korean patent application 10-2008-0127456 (2008-12) -15), US application 12/461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), US application 12/537,341 (2009-08-07), etc. can be applied as

The timing controller 20 receives timing signals synchronized with input image data from the host system 30 . The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK. The timing controller 20 controls operation timings of the data driver 12 and the gate driver 14 based on the timing signals Vsync, Hsync, DE, and DCLK received together with the pixel data of the input image. The timing controller 20 may transmit polarity information of data for controlling the polarity of the pixel array to each of the source drive ICs of the data driver 12 . The Mini LVDS interface transmits the polarity control signal through a separate control wire. The EPI interface is an interface technology that encodes polarity control information in a control data packet transmitted between a clock training pattern for CDR (Clok and Data Recovery) and an RGBW data packet and transmits it to each of the source drive ICs.

The timing controller 20 may convert RGB data of an input image into RGBW data using a white gain calculation algorithm. The white gain calculation algorithm can be any known. For example, Korean Patent Application No. 10-2005-0039728 (May 12, 2005), Korean Patent Application No. 10-2005-0052906 (June 20, 2005) previously filed by the applicant of the present application, Korean Patent Application No. 10-2005 The white gain calculation algorithms proposed in -0066429 (2007. 07. 21) and Korean Patent Application No. 10-2006-0011292 (2006. 02. 06) are applicable.

The host system 30 may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

In the present invention, in order to reduce the number of source drive ICs, the structure of the pixel array is implemented as double rate driving (DRD) type pixels in which two adjacent sub-pixels share one data line as shown in FIG. 2 . The source drive IC driving the DRD type pixel array doubles the frequency of the data voltage. The DRD type pixel array can reduce the number of source drive ICs by half.

The present invention proposes the arrangement of a pixel array as shown in FIG. 2 in order to prevent a decrease in the aperture ratio because the storage capacitors are adjacent to each other. Hereinafter, the first color, the second color, the third color, and the fourth color are exemplified as R, G, B, and W, respectively, but the present invention is not limited thereto.

The present invention controls the polarity pattern of a pixel array in the form of a dot inversion that inverts polarities between adjacent sub-pixels along vertical and horizontal directions. The polarity pattern of the pixel array is determined according to the polarity of the data voltage output from each of the source drive ICs of the data driver 12 and the structure of the pixel array.

The horizontal polarity pattern of the pixel array is determined according to the polarities of data voltages simultaneously output through output channels of the source drive IC. For example, when '+' is positive polarity and '-' is negative polarity, if the polarities of data voltages simultaneously output through the output channels of the source drive IC are + - + - or - + - + from left to right It is a horizontal 1 dot inversion (H1 dot inversion), and if + + - - or - - + + is a horizontal 2 dot inversion (H2 dot inversion).

The vertical polarity pattern of the pixel array is determined according to the temporally changing data voltage polarity when data voltages are output through output channels from the source drive IC. For example, if the temporal change in the polarity of the data voltage output through the output channels from the source drive IC is + - + - or - + - +, it is a vertical 1 dot inversion (V1 dot inversion), and + + - - or - - + + is a vertical 2 dot inversion (V2 dot inversion).

2 is a circuit diagram illustrating a part of a pixel array according to an embodiment of the present invention.

Referring to FIG. 2 , the pixel array includes data lines D1 to Dm+1, gate lines G1 to G2n crossing the data lines D1 to Dm+1, and gate lines G1 to G2n. common lines V1 to V2n in parallel with and for switching a current path between the pixel electrodes PX11 to PX14 and PX21 to PX24 of the pixels and the data lines D1 to Dm+1 in response to a gate pulse TFTs T11 to T12, T21 to T24, and T31 to T34 are provided. The polarities of the data voltages whose polarities are inverted in the column inversion method and the data voltages charged in the pixels due to the pixel array structure of FIG. 2 are inverted in horizontal 1 dot and vertical 1 dot inversion.

The source drive ICs 12 output data voltages whose polarities are inverted to the data lines D1 to Dm+1 in a column inversion form. The gate driving circuit 13 sequentially supplies gate pulses to the first to 2n gate lines G1 to G2n. After the first gate pulse is supplied to the first gate line G1, the second to 2n-th gate pulses G1 to G2n are sequentially supplied to the second to 2n-th gate lines G1 to G2n.

During the N-th frame period, the source drive ICs 12 supply only the positive data voltage to the odd data lines D1..Dm+1 and only the negative data voltage to the even data lines D2m. . During the N+1th frame period, the source drive ICs 12 supply only the negative data voltage to the odd data lines D1..Dm+1 and only the positive data voltage to the even data lines Dm. supply

In each of the odd horizontal display lines LINE#1... LINE#n, first and second pixels of the odd horizontal display line exist between the i-th data line and the i+1-th data line. The first pixel of the odd horizontal display line is charged with the negative polarity data voltage supplied from the i+1th data line during the Nth frame period, and then has the positive polarity supplied from the i+1th data line during the N+1th frame period. Charge the data voltage. The second pixel of the odd horizontal display line is charged with the positive data voltage supplied from the i-th data line during the N-th frame period, and then charged with the negative data voltage supplied from the i-th data line during the N+1-th frame period. do. In FIG. 2 , reference numeral 'PX11' denotes a first pixel electrode formed in a first pixel of an odd horizontal display line, and 'PX12' denotes a second pixel electrode formed in a second pixel of an odd horizontal display line.

In each of the odd horizontal display lines LINE#1.. LINE#n, third and fourth pixels of the odd horizontal display line are present between the i+1th data line and the i+2th data line. After the third pixel of the odd horizontal display line is charged with the negative data voltage supplied from the i+1th data line during the Nth frame period, the positive polarity supplied from the i+1th data line during the N+1th frame period is charged. Charge the data voltage. After the fourth pixel of the odd horizontal display line is charged with the positive data voltage supplied from the i+2th data line during the Nth frame period, the negative polarity supplied from the i+2th data line during the N+1th frame period is charged. Charge the data voltage. In FIG. 2 , reference numeral 'PX13' denotes a third pixel electrode formed in a third pixel of an odd horizontal display line, and 'PX14' denotes a fourth pixel electrode formed in a fourth pixel of an odd horizontal display line.

In the even horizontal display line LINE#n-1, first and second pixels of an even horizontal line exist between the i-th data line and the i+1-th data line. The first pixel of the even horizontal line is charged with the positive data voltage supplied from the i-th data line during the N-th frame period and then charged with the negative data voltage supplied from the i-th data line during the N+1-th frame period. . The second pixel of the even horizontal line is charged with the negative data voltage supplied from the i+1th data line during the Nth frame period, and then the positive data supplied from the i+1th data line during the N+1th frame period is charged. charge voltage. In FIG. 2 , reference numeral 'PX21' denotes a first pixel electrode formed in a first pixel of an even horizontal display line, and 'PX22' denotes a second pixel electrode formed in a second pixel of an even horizontal display line.

In the even horizontal display line LINE#n-1, the third and fourth pixels of the even horizontal line exist between the i+1th data line and the i+2th data line. The third pixel of the even horizontal line is charged with the positive data voltage supplied from the i+2th data line during the Nth frame period, and then the negative data supplied from the i+2th data line during the N+1th frame period is charged. charge voltage. The fourth pixel of the even horizontal line is charged with the negative data voltage supplied from the i+1th data line during the Nth frame period, and then positive data supplied from the i+1th data line during the N+1th frame period. charge voltage. In FIG. 2 , reference numeral 'PX23' denotes a third pixel electrode formed in a third pixel of an even horizontal display line, and 'PX24' denotes a fourth pixel electrode formed in a fourth pixel of an even horizontal display line.

As can be seen from FIG. 2 , the vertically neighboring pixels and the left and right neighboring pixels are charged with data voltages having opposite polarities. Accordingly, the pixels of the pixel array of FIG. 2 are charged with data voltages that are inverted in the form of one horizontal dot and one vertical dot inversion.

In the pixel array 10 shown in FIG. 2 , the connection relationship between the TFT, the pixel electrode, and the data line is shown in the first to fourth pixels of the first horizontal display line LINE#1 and the second horizontal display line LINE#. The first to fourth pixels of 2) will be described as examples.

The first pixel of the first horizontal display line LINE#1 is charged with the data voltage supplied from the second data line D2. Subsequently, the second pixel of the first horizontal display line LINE#1 is charged with the data voltage supplied from the first data line D1. The first TFT T11 of the first horizontal display line supplies the data voltage from the second data line D2 to the first pixel electrode PX11 in response to the first gate pulse from the first gate line G1 . do. A common voltage is charged to the first common line V1. The first pixel electrode PX11 is charged with the data voltage for about 1/2 horizontal period. The gate electrode of the first TFT T11 is connected to the first gate line G1. A source electrode of the first TFT T11 is connected to the second data line D2 , and a drain electrode thereof is connected to the first pixel electrode PX11 , and the first common line V1 and the first storage capacitor C11 are connected to each other. is formed

The second TFT T12 of the first horizontal display line supplies the data voltage from the first data line D1 to the second pixel electrode PX12 in response to the second gate pulse from the second gate line G2 . do. A common voltage is charged to the second common line V2. The second pixel electrode PX12 is charged with the data voltage for approximately 1/2 horizontal period. The gate electrode of the second TFT T12 is connected to the second gate line G2. A source electrode of the second TFT T12 is connected to the first data line D1 , a drain electrode thereof is connected to the second pixel electrode PX12 , and a second common line V2 and a second storage capacitor C12 are connected. is formed

Subsequently, the third pixel of the first horizontal display line LINE#1 is charged with the data voltage supplied from the third data line D3. The third TFT T13 of the first horizontal display line supplies the data voltage from the third data line D3 to the third pixel electrode PX13 in response to the second gate pulse from the second gate line G2 . do. A common voltage is charged to the second common line V2. The third pixel electrode PX13 is charged with the data voltage for approximately 1/2 horizontal period. The gate electrode of the TFT (T13) is connected to the second gate line (G2). A source electrode of the third TFT T13 is connected to the third data line D3 , a drain electrode thereof is connected to the third pixel electrode PIX13 , and the second common line V2 and the third storage capacitor C13 are connected to each other. ) is formed. The fourth TFT T14 of the first horizontal display line supplies the data voltage from the second data line D2 to the fourth pixel electrode PX14 in response to the first gate pulse from the first gate line G1 . do. A common voltage is charged to the first common line V1. The fourth pixel electrode PX14 is charged with the data voltage for approximately 1/2 horizontal period. The gate electrode of the fourth TFT T14 is connected to the first gate line G1. The source electrode of the fourth TFT T14 is connected to the second data line D2 , and its drain electrode is connected to the fourth pixel electrode PIX14 , and the first common line V1 and the fourth storage capacitor C14 are connected to each other. is formed

The first pixel of the second horizontal display line LINE#2 charges the data voltage supplied from the second data line D2. Subsequently, the second pixel of the second horizontal display line LINE#2 is charged with the data voltage supplied from the first data line D1 . The first TFT T21 of the second horizontal display line supplies the data voltage from the second data line D2 to the first pixel electrode PX21 in response to the third gate pulse from the third gate line G3 . do. A common voltage is charged to the third common line V3. The first pixel electrode PX21 is charged with the data voltage for approximately 1/2 horizontal period. The gate electrode of the first TFT T21 is connected to the third gate line G3. The source electrode of the first TFT T21 is connected to the second data line D2 , and the drain electrode thereof is connected to the first pixel electrode PX21 , and the third common line V3 and the first storage capacitor C21 are connected to each other. is formed The second TFT T22 of the second horizontal display line supplies the data voltage from the first data line D1 to the second pixel electrode PX22 in response to the fourth gate pulse from the fourth gate line G4. do. The common voltage is charged to the fourth common line V4. The second pixel electrode PX22 is charged with the data voltage for about 1/2 horizontal period. The gate electrode of the second TFT T22 is connected to the fourth gate line G4. A source electrode of the second TFT T22 is connected to the first data line D1 , a drain electrode thereof is connected to the second pixel electrode PIX22 , and a fourth common line V4 and a second storage capacitor C22 are connected. is formed

The third pixel of the second horizontal display line LINE#2 charges the data voltage supplied from the third data line D3. Subsequently, the fourth pixel of the second horizontal display line LINE#2 is charged with the data voltage supplied from the second data line D2 . The third TFT T23 of the second horizontal display line supplies the data voltage from the third data line D3 to the third pixel electrode PX23 in response to the fourth gate pulse from the fourth gate line G4 . do. The common voltage is charged to the fourth common line V4. The third pixel electrode PX23 is charged with the data voltage for about 1/2 horizontal period. The gate electrode of the third TFT T23 is connected to the fourth gate line G4. A source electrode of the third TFT T23 is connected to the third data line D3 , a drain electrode thereof is connected to the third pixel electrode PX23 , and the fourth common line V4 and the third storage capacitor C23 are connected to each other. is formed The fourth TFT T24 of the second horizontal display line supplies the data voltage from the second data line D2 to the fourth pixel electrode PX24 in response to the third gate pulse from the third gate line G3 . do. A common voltage is charged to the third common line V3. The fourth pixel electrode PX24 charges the data voltage for approximately 1/2 horizontal period. The gate electrode of the fourth TFT T24 is connected to the third gate line G3 . The source electrode of the fourth TFT T24 is connected to the second data line D2 , and the drain electrode thereof is connected to the fourth pixel electrode PX24 , and the third common line V3 and the fourth storage capacitor C24 are connected to each other. is formed

The foregoing descriptions of FIGS. 1 and 2 are for illustrating the schematic structure and operation of the column inversion method of the display device of the present invention. Hereinafter, various structures of the column inversion type display device will be described. In addition, in the following embodiments, the order numbers of 1st, 2nd, 3rd, 4th, etc. are arbitrarily assigned names for convenience of description, and therefore, they should be viewed flexibly because the order numbers may vary depending on the viewpoint.

<First embodiment>

3 is a plan view illustrating a structure of a pixel array of a display device according to a first exemplary embodiment of the present invention. Hereinafter, a pixel array structure of the first and second pixels of the first horizontal display line LINE#1 and the first and second pixels of the second horizontal display line LINE#2 will be described. . The first pixel and the second pixel of the second horizontal display line LINE#2 are described as the third pixel and the fourth pixel to prevent confusion with the pixels of the first horizontal display line.

Referring to FIG. 3 , in the horizontal electric field liquid crystal display according to the first embodiment of the present invention, gate lines G2 and G3 are horizontally disposed on a substrate, and data lines D1 and D2 formed to cross them. ), TFTs T11 and 21 formed at each intersection thereof, pixel electrodes PX12 and PX21 and common electrodes Vcom12 and Vcom21 formed to form a horizontal electric field in the pixel region provided in the intersection structure, and The common lines V1 , V2 , V3 , V4 connected to the common electrodes Vcom12 and Vcom21 and disposed in parallel with the gate lines G2 and G3 and the data lines D1 and D2 are disposed in parallel with each other. and includes a vertical common line VV connected to the common electrodes Vcom12 and Vcom21.

In more detail, the second pixel electrode PX12 and the third pixel electrode PX21 are disposed between the adjacent first and second data lines D1 and D2 . A vertical common line VV parallel to the data lines D1 and D2 is disposed between the second pixel electrode PX12 and the third pixel electrode PX21 , and the second pixel electrode PX12 and the third pixel electrode PX12 A second gate line G2 and a third gate line G3 crossing the data lines D1 and D2 are disposed between the PX21 . The second storage capacitor C12 and the third storage capacitor C21 are disposed between the second pixel electrode PX12 and the third pixel electrode PX21 , and the second storage capacitor C12 is connected to the vertical common line VV. The second pixel electrode PX12 and the third storage capacitor C21 are positioned opposite to each other with respect to , and the third storage capacitor C21 is positioned opposite to the third pixel electrode PX21 with respect to the vertical common line VV. The first bridge pixel electrode BPX1 connecting the second storage capacitor C12 to the second pixel electrode PX12 and the second connecting the third pixel electrode PX21 from the third storage capacitor C21 The bridge pixel electrode BPX2 is disposed, and the first bridge pixel electrode BPX1 and the second bridge pixel electrode BPX2 cross the vertical common line VV.

A second TFT T12 is included at the intersection of the first data line D1 adjacent to the second storage capacitor C12 and the second gate line G2 and adjacent to the third storage capacitor C21. A third TFT T21 is included at the intersection of the data line D2 and the third gate line G3 . A first common line V1 parallel to the second gate line G2 is disposed opposite to the second gate line G2 with the second pixel electrode PX12 interposed therebetween, and the third pixel electrode PX21 A fourth common line V4 parallel to the third gate line G3 is disposed opposite to the third gate line G3 with the third gate line G3 interposed therebetween. The first common line V1 is connected to the second common electrode Vcom12 , and the fourth common line V4 is connected to the third common electrode Vcom21 . The first bridge pixel electrode BPX1 and the second pixel electrode PX12 are integrally formed, and the second bridge pixel electrode BPX2 and the third pixel electrode PX21 are integrally formed. Also, the second gate line G2 and the third gate line G3 are positioned between the second storage capacitor C12 and the third storage capacitor C21 .

More specifically, the first pixel P1 and the second pixel P2 are disposed above the second gate line G2 and the third gate line G3 as a reference, and the third pixel P3 is disposed below the second gate line G2 and the third gate line G3. ) and a fourth pixel P4 are disposed. In addition, based on the vertical common line VV, the first pixel P1 and the third pixel P3 are disposed on the left, and the second pixel P2 and the fourth pixel P4 are disposed on the right side. The first data line D1 is disposed on the left side of the first pixel P1 and the third pixel P3 , and the second data line D2 is disposed on the right side of the second pixel P2 and the fourth pixel P4 . this is placed A second common line V2 is disposed adjacent to the second gate line G2 in parallel, and a third common line V2 is disposed adjacent to and parallel to the third gate line G3.

A second TFT T12 is disposed at the intersection of the second gate line G2 and the first data line D1 . The second TFT T12 includes a source electrode 150 branched from the first data line D1 and a drain electrode 155 extending from the second TFT T12 . The drain electrode 155 overlaps the second common line V2 to form a second storage capacitor C12 . The first bridge pixel electrode BPX1 is connected to the drain electrode 155 through the first contact hole CH1 in the region overlapping the second storage capacitor C12 . The first bridge pixel electrode BPX1 extends from the second TFT T12 positioned in the first pixel P1 to supply a data voltage to the second pixel electrode PX12 of the second pixel P2 . The first bridge pixel electrode BPX1 is integrally formed with the second pixel electrode PX12 and crosses the vertical common line VV positioned between the first pixel P1 and the second pixel P2 . The first common line V1 is connected to the second common electrode Vcom12 of the second pixel P2 to supply a common voltage. Accordingly, the second pixel P2 includes the second TFT T12 , the second pixel electrode PX12 extended by the first bridge pixel electrode BPX1 , and the second common electrode Vcom12 .

Meanwhile, a third TFT T21 is disposed at the intersection of the third gate line G3 and the second data line D2 . The third TFT T21 includes a source electrode 160 branched from the second data line D2 and a drain electrode 165 extending from the third TFT T21 . The drain electrode 165 overlaps the third common line V3 to form a third storage capacitor C21 . The second bridge pixel electrode BPX2 is connected to the drain electrode 165 through the third contact hole CH3 in the region overlapping the third storage capacitor C21 . The second bridge pixel electrode BPX2 extends from the third TFT T21 positioned in the fourth pixel P4 to supply a data voltage to the third pixel electrode PX21 of the third pixel P3 . The second bridge pixel electrode BPX2 is integrally formed with the third pixel electrode PX21 and crosses the vertical common line VV positioned between the third pixel P3 and the fourth pixel P4 . The fourth common line V4 is connected to the third common electrode Vcom21 of the third pixel P3 to supply a common voltage. Accordingly, the third pixel P3 includes the third TFT T21 , the third pixel electrode PX21 extended by the second bridge pixel electrode BPX2 , and the third common electrode Vcom21 .

Meanwhile, the second common line V2 is connected to the first common electrode Vcom11 of the first pixel P1 to supply a common voltage, and the vertical common line VV is also connected to the second common line VV through the second contact hole CH2. 1 It is connected to the common electrode Vcom11 to supply a common voltage. In addition, the third common line V3 is connected to the fourth common electrode Vcom22 of the fourth pixel P4 to supply a common voltage, and the vertical common line VV is also connected to the fourth common electrode Vcom22 through the fourth contact hole CH4. 4 It is connected to the common electrode (Vcom22) to supply a common voltage.

In the present invention, the TFT and the storage capacitor are arranged adjacent to each other based on a vertical common line in order to reduce the spacing between the pixels in the vertical relationship. As shown in FIG. 3 , the second storage capacitor C12 is disposed between the first pixel P1 and the third pixel P3 , and the third storage capacitor C21 is formed between the second pixel P2 and the second pixel P2 . It is disposed between the 4 pixels P4 . Accordingly, conventional storage capacitors are disposed to face each other to prevent a decrease in the aperture ratio due to a very wide spacing between pixels.

In addition, the present invention supplies data voltages to pixel electrodes of pixels disposed adjacent to each other based on a vertical common line from a TFT and a storage capacitor by using a bridge pixel electrode to reduce a gap between pixels in a vertical relationship. . As shown in FIG. 3 , the first bridge pixel electrode BPX1 is connected to the drain electrode 150 of the second TFT T12 to intersect the vertical common line VV to form a second pixel P2 adjacent thereto. It is integrally connected with the second pixel electrode PX12. In addition, the second bridge pixel electrode BPX2 is connected to the drain electrode 165 of the third TFT T21 to cross the vertical common line VV and the third pixel electrode PX21 of the neighboring third pixel P3 is connected. ) is integrally connected with Accordingly, the gap between pixels is very wide due to the structure in which the source electrode of the conventional TFT is extended, thereby preventing the aperture ratio from being lowered.

Hereinafter, a cross-sectional structure of the pixel array of the display device according to the first embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5 . 4 is a cross-sectional view taken along line II' of FIG. 3, and FIG. 5 is a cross-sectional view taken along line II-II' of FIG.

4 and 5 , the second gate line G2 and the second common line V2 are disposed in parallel on the substrate 110 . The second gate line G2 serves as a gate electrode. The gate insulating layer 140 is disposed over the entire surface of the substrate 110 on the second gate line G2 and the second common line V2 . The semiconductor layer 145 is positioned on the gate insulating layer 140 to overlap the second gate line G2 . In addition, on the gate insulating layer 140 , a source electrode 150 connected to one side of the semiconductor layer 145 , and a drain electrode 155 spaced apart from the source electrode 150 by a predetermined distance and connected to the other side of the semiconductor layer 145 . this is located Accordingly, the second TFT T12 including the second gate line G2 , the semiconductor layer 145 , the source electrode 150 , and the drain electrode 155 is configured.

In addition, the drain electrode 155 and the second common line V2 overlap to form the second storage capacitor C12 . A vertical common line VV is positioned to be spaced apart from the drain electrode 155 by a predetermined distance. A second data line D2 is positioned. A planarization layer 170 covering the second TFT T12 , the vertical common line VV, and the second data line D2 is disposed on the entire surface of the substrate 110 . The planarization layer 170 has a first contact hole CH1 exposing a portion of the drain electrode 155 and a second contact hole CH2 exposing a portion of the vertical common line VV and the second common line V2. ) is provided. A first bridge pixel electrode BPX1 , a second pixel electrode PX12 , a first common electrode Vcom11 , and a second common electrode Vcom12 are positioned on the planarization layer 170 . The first bridge pixel electrode BPX1 is connected to the drain electrode 155 through the first contact hole CH1 of the planarization layer 170 . The first common electrode Vcom11 is connected to the second common line V2 and the vertical common line VV through the second contact hole CH2 of the planarization layer 170 . The first bridge pixel electrode BPX1 crosses the vertical common line VV and extends to the second pixel electrode PX12 . Accordingly, the display device according to the first embodiment of the present invention is configured.

<Second embodiment>

6 is a plan view illustrating a structure of a pixel array of a display device according to a second exemplary embodiment of the present invention. Hereinafter, the same reference numerals are given to the same components as those of the first embodiment to facilitate understanding.

Referring to FIG. 6 , the horizontal electric field liquid crystal display according to the second embodiment of the present invention includes gate lines G2 and G3 horizontally disposed on a substrate, a data line D1 formed to cross them, TFTs T11 and 22 formed at each intersection, pixel electrodes PX11, PX12, PX21, and PX22 and common electrodes Vcom11, Vcom12, and Vcom21 formed to form a horizontal electric field in the pixel region provided in the intersection structure. Vcom22), the common lines V1, V2, V3 connected to the common electrodes Vcom11, Vcom12, Vcom21, and Vcom22 and disposed in parallel with the gate lines G2 and G3, and the data line D1; The vertical common line VV is disposed between the pixel electrodes PX11 , PX12 , PX21 , and PX22 in parallel or overlapping with each other and connected to the common electrodes Vcom11 , Vcom12 , Vcom21 and Vcom22 .

The second embodiment of the present invention discloses a DRD structure in which two pixels share one data line in the same manner as in the above-described first embodiment, but discloses a structure that is partially different, such as the position of the pixel electrode.

In more detail, the first pixel electrode PX11 and the second pixel electrode PX12 are disposed adjacent to each other with the data line D1 interposed therebetween, and the third pixel electrode PX21 and the fourth pixel electrode PX22 are adjacent to each other. is laid out A second gate line G2 and a third gate line G3 crossing the data line D1 are disposed between the first pixel electrode PX11 and the third pixel electrode PX21 . Accordingly, the first pixel electrode PX11 is disposed to face the third pixel electrode PX21 with the second and third gate lines G2 and G3 interposed therebetween, and the second pixel electrode PX12 is the second and the fourth pixel electrode PX22 with the third gate lines G2 and G3 interposed therebetween.

A vertical common line VV parallel to the data line D1 is disposed between the first pixel electrode PX11 and the second pixel electrode PX12 and between the third pixel electrode PX21 and the fourth pixel electrode PX22 do. Also, the vertical common line VV is disposed adjacent to the data line D1 with the first pixel electrode PX11 and the third pixel electrode PX21 interposed therebetween, and the second pixel electrode PX12 and the fourth pixel electrode PX12 are disposed adjacent to each other. It is disposed adjacent to the data line D1 with the pixel electrode 22 interposed therebetween. The vertical common line VV is integrated with the first to fourth common electrodes Vcom11 , Vcom12 , Vcom21 , and Vcom22 to have a mesh shape.

The first storage capacitor C11 is disposed between the first pixel electrode PX11 and the third pixel electrode PX21 , and is disposed between the first pixel electrode PX11 and the second gate line G2 . The fourth storage capacitor C22 is disposed between the second pixel electrode PX12 and the fourth pixel electrode PX22 and is disposed between the fourth pixel electrode PX22 and the third gate line G3 . The data line D1 includes a first TFT T11 at the intersection of the data line D1 adjacent to the first storage capacitor C11 and the second gate line G2 and adjacent to the second storage capacitor C22. A fourth TFT T22 is included at the intersection of the and the third gate line G3. That is, the first TFT T11 and the fourth TFT T22 share the data line D1 .

The second common line V2 is disposed adjacent to the second gate line G2 , and the first common line V1 has a second common line with the first pixel electrode PX11 and the second pixel electrode PX12 interposed therebetween. It is placed opposite the line V2. The third common line V3 is disposed adjacent to the third gate line G3 and the fourth common line V4 has a third common line with the third pixel electrode PX21 and the fourth pixel electrode PX22 interposed therebetween. It is placed opposite the line V3. Also, the second gate line G2 and the third gate line G3 are positioned between the first storage capacitor C11 and the fourth storage capacitor C22 .

More specifically, the first pixel P1 and the second pixel P2 are disposed above the second gate line G2 and the third gate line G3 as a reference, and the third pixel P3 is disposed below the second gate line G2 and the third gate line G3. ) and a fourth pixel P4 are disposed. In addition, the first pixel P1 and the third pixel P3 are disposed on the left side of the data line D1 , and the second pixel P2 and the fourth pixel P4 are disposed on the right side of the data line D1 . A second common line V2 is disposed adjacent to the second gate line G2 in parallel, and a third common line V2 is disposed adjacent to and parallel to the third gate line G3.

A first TFT T11 is disposed at the intersection of the second gate line G2 and the data line D1 . The first TFT T11 includes a source electrode 150 branched from the data line D1 and a drain electrode 155 extending from the first TFT T11 . The drain electrode 155 overlaps the second common line V2 to form a first storage capacitor C11 . A first pixel electrode PX11 extending from a region overlapping the drain electrode 155 and the first storage capacitor C11 is positioned. The first pixel electrode PX11 is located in the first pixel P1 . The first pixel electrode PX11 is connected to the drain electrode 155 through the first contact hole CH1 to receive the data voltage from the first TFT T11 . In addition, the first common electrode Vcom11 receives a common voltage from the vertical common line VV to form a horizontal electric field with the first pixel electrode PX11 . Accordingly, the first pixel P1 includes the first TFT T11 , the first pixel electrode PX11 , and the first common electrode Vcom11 .

Meanwhile, a fourth TFT T22 is disposed at the intersection of the third gate line G3 and the data line D1 . The fourth TFT T22 includes a source electrode 160 branched from the data line D1 and a drain electrode 165 extending from the fourth TFT T22. The drain electrode 165 overlaps the third common line V3 to form a fourth storage capacitor C22 . A fourth pixel electrode PX22 extending from a region where the drain electrode 165 and the fourth storage capacitor C22 overlap is positioned. The fourth pixel electrode PX22 is positioned in the fourth pixel P4 . The fourth pixel electrode PX22 is connected to the drain electrode 165 through the second contact hole CH2 to receive the data voltage from the fourth TFT T22 . In addition, the fourth common electrode Vcom22 receives a common voltage from the vertical common line VV to form a horizontal electric field with the fourth pixel electrode PX22 . Accordingly, the fourth pixel P4 includes the fourth TFT T22 , the fourth pixel electrode PX22 , and the fourth common electrode Vcom22 . The third common line V3 supplies a common voltage to the vertical common line VV in an area adjacent to the third pixel P3 through the third contact hole CH3. The remaining second pixel P2 and third pixel P3 are also configured in the same manner as the first pixel P1 and fourth pixel P4 .

According to the present invention, in order to reduce the distance between pixels in a vertical relationship, the TFT and the storage capacitor are disposed adjacent to each other based on the data line. As shown in FIG. 6 , the first storage capacitor C11 is disposed between the first pixel P1 and the third pixel P3 , and the fourth storage capacitor C22 is formed between the second pixel P2 and the second pixel P2 . It is disposed between the four pixels P4 . Accordingly, the conventional storage capacitors are disposed to face each other to prevent a decrease in the aperture ratio due to a very wide spacing between pixels.

Hereinafter, a cross-sectional structure of a pixel array of a display device according to a second embodiment of the present invention will be described in more detail with reference to FIG. 7 . 7 is a cross-sectional view taken along line III-III' of FIG. 6 .

Referring to FIG. 7 , a second gate line G2 , a third gate line G3 , a second common line V2 , and a third common line V3 are disposed on the substrate 110 . The second gate line G2 serves as a gate electrode. A gate insulating layer 140 is disposed over the entire surface of the substrate 110 on the second gate line G2 , the third gate line G3 , the second common line V2 , and the third common line V3 . The semiconductor layer 145 is positioned on the gate insulating layer 140 to overlap the second gate line G2 . In addition, on the gate insulating layer 140 , a source electrode 150 connected to one side of the semiconductor layer 145 , and a drain electrode 155 spaced apart from the source electrode 150 by a predetermined distance and connected to the other side of the semiconductor layer 145 . this is located Accordingly, the first TFT T11 including the second gate line G2 , the semiconductor layer 145 , the source electrode 150 , and the drain electrode 155 is configured.

In addition, the drain electrode 155 and the second common line V2 overlap to form the first storage capacitor C11 . A planarization layer 170 covering the first TFT T11 is disposed on the entire surface of the substrate 110 . A first contact hole CH1 exposing a portion of the drain electrode 155 and a third contact hole CH3 exposing a portion of the third common line V3 are provided in the planarization layer 170 . A first pixel electrode PX11 , a first common electrode Vcom11 , and a vertical common line VV are positioned on the planarization layer 170 . The vertical common line VV is connected to the third common line V3 through the third contact hole CH3 formed in the planarization layer 170 and the gate insulating layer 140 . Accordingly, the display device according to the second embodiment of the present invention is configured.

<Third embodiment>

8 is a plan view illustrating a structure of a pixel array of a display device according to a third exemplary embodiment of the present invention. Hereinafter, the same reference numerals are assigned to the same components as those of the second embodiment to facilitate understanding.

Referring to FIG. 8 , a horizontal electric field liquid crystal display according to a third embodiment of the present invention includes gate lines G2 and G3 horizontally disposed on a substrate, a data line D1 formed to cross them, TFTs T21 and 12 formed at each intersection, pixel electrodes PX11, PX12, PX21, PX22 and common electrodes Vcom11, Vcom12, Vcom21, formed to form a horizontal electric field in the pixel region provided in the intersection structure. Vcom22), the common line V1 connected to the common electrodes Vcom11, Vcom12, Vcom21, and Vcom22 and disposed in parallel with the gate lines G2 and G3, and the data line D1 parallel to or overlapping the pixel The vertical common line VV disposed between the electrodes PX11, PX12, PX21, and PX22 and connected to the common electrodes Vcom11, Vcom12, Vcom21, and Vcom22, and the data line D1 are disposed in parallel with but not overlapping and an auxiliary common line (SV).

In the third embodiment of the present invention, unlike the structure of the above-described second embodiment, one common line is disposed between two gate lines to disclose a structure in which two pixels share one common line.

In more detail, the first pixel electrode PX11 and the second pixel electrode PX12 are disposed adjacent to each other with the data line D1 interposed therebetween, and the third pixel electrode PX21 and the fourth pixel electrode PX22 are adjacent to each other. is laid out A second gate line G2 and a third gate line G3 crossing the data line D1 are disposed between the first pixel electrode PX11 and the third pixel electrode PX21 . Accordingly, the first pixel electrode PX11 is disposed to face the third pixel electrode PX21 with the second and third gate lines G2 and G3 interposed therebetween, and the second pixel electrode PX12 is the second and the fourth pixel electrode PX22 with the third gate lines G2 and G3 interposed therebetween.

A vertical common line VV parallel to the data line D1 is disposed between the first pixel electrode PX11 and the second pixel electrode PX12 and between the third pixel electrode PX21 and the fourth pixel electrode PX22 do. Also, the vertical common line VV is disposed adjacent to the data line D1 with the first pixel electrode PX11 and the third pixel electrode PX21 interposed therebetween, and the second pixel electrode PX12 and the fourth pixel electrode PX12 are disposed adjacent to each other. It is disposed adjacent to the data line D1 with the pixel electrode 22 interposed therebetween. The vertical common line VV is integrated with the first to fourth common electrodes Vcom11 , Vcom12 , Vcom21 , and Vcom22 to have a mesh shape.

The second storage capacitor C12 is disposed between the second pixel electrode PX12 and the fourth pixel electrode PX22 and is disposed between the second pixel electrode PX12 and the third gate line G3 . The third storage capacitor C21 is disposed between the first pixel electrode PX11 and the third pixel electrode PX21 , and is disposed between the third pixel electrode PX21 and the second gate line G2 . The second TFT T12 is included at the intersection of the data line D1 adjacent to the second storage capacitor C12 and the third gate line G3 and the data line D1 adjacent to the third storage capacitor C21 is A third TFT T21 is included at the intersection of the second gate line G2 and the second gate line G2 .

More specifically, the first pixel P1 and the second pixel P2 are disposed above the second gate line G2 and the third gate line G3 as a reference, and the third pixel P3 is disposed below the second gate line G2 and the third gate line G3. ) and a fourth pixel P4 are disposed. In addition, the first pixel P1 and the third pixel P3 are disposed on the left side of the data line D1 , and the second pixel P2 and the fourth pixel P4 are disposed on the right side of the data line D1 .

A third TFT T21 is disposed at the intersection of the second gate line G2 and the data line D1 . The third TFT T21 includes a source electrode 150 branched from the data line D1 and a drain electrode 155 extending from the third TFT T21 . The drain electrode 155 overlaps the common line V1 to form a third storage capacitor C21 . A third pixel electrode PX21 extending from a region overlapping the drain electrode 155 and the first storage capacitor C11 is positioned. The third pixel electrode PX21 is located in the third pixel P3 . The third pixel electrode PX21 is connected to the drain electrode 155 through the first contact hole CH1 to receive a data voltage from the third TFT T21 . In addition, the third common electrode Vcom21 receives a common voltage from the vertical common line VV to form a horizontal electric field with the third pixel electrode PX21 . Accordingly, the third pixel P3 includes the third TFT T21 , the third pixel electrode PX21 , and the third common electrode Vcom21 .

Meanwhile, the second TFT T12 is disposed at the intersection of the third gate line G3 and the data line D1 . The second TFT T12 includes a source electrode 160 branched from the data line D1 and a drain electrode 165 extending from the second TFT T12 . The drain electrode 165 overlaps the common line V1 to form a second storage capacitor C12 . A second pixel electrode PX12 extending from a region where the drain electrode 165 and the second storage capacitor C12 overlap is positioned. The second pixel electrode PX12 is located in the second pixel P2 . The second pixel electrode PX12 is connected to the drain electrode 165 through the second contact hole CH2 to receive the data voltage from the second TFT T12 . In addition, the second common electrode Vcom12 receives a common voltage from the vertical common line VV to form a horizontal electric field with the second pixel electrode PX12 . Accordingly, the second pixel P2 includes the second TFT T12 , the second pixel electrode PX12 , and the second common electrode Vcom12 . The common line V1 supplies a common voltage to the vertical common line VV in an area adjacent to the third pixel P3 through the third contact hole CH3. The remaining first pixel P1 and fourth pixel P4 are also configured in the same manner as the second pixel P2 and third pixel P3 .

The above-described second pixel P2 and third pixel P3 have a structure that shares one common line V1 . Specifically, the common line V1 is disposed in parallel with the second gate line G2 and the third gate line G3 and is disposed between the second gate line G2 and the third gate line G3. . Accordingly, the common line V1 forms the drain electrode 155 and the third capacitor C21 of the third pixel P3, and connects the drain electrode 165 and the second capacitor C12 of the second pixel P2. accomplish In addition, the common line extension part VVE partially extended from the vertical common line VV has a structure overlapping with the third gate line G3 . The common line extension VVE is positioned between the third gate line G3 and the third pixel electrode PX21 to prevent a parasitic capacitor between the third gate line G3 and the third pixel electrode PX21 . .

In the display device according to the third embodiment of the present invention, one common line is disposed between the gate lines so that the two pixels share a common line in order to reduce the distance between the pixels having a vertical relationship. As shown in FIG. 8 , the common line V1 is disposed between the second gate line G2 and the third gate line G3 and consists of one. Accordingly, the gap between the first pixel P1 and the third pixel P2 or between the second pixel P2 and the fourth pixel P4 is reduced, thereby improving the aperture ratio of the pixels.

Hereinafter, a cross-sectional structure of a pixel array of a display device according to a third exemplary embodiment of the present invention will be described in more detail with reference to FIG. 9 . 9 is a cross-sectional view taken along line IV-IV' of FIG. 8 .

Referring to FIG. 9 , the second gate line G2 , the third gate line G3 , and the common line V1 are disposed in parallel on the substrate 110 . The second gate line G2 serves as a gate electrode. The second gate line G2 , the third gate line G3 , and the common line V1 gate insulating layer 140 are disposed over the entire surface of the substrate 110 . The semiconductor layer 145 is positioned on the gate insulating layer 140 to overlap the second gate line G2 . In addition, on the gate insulating layer 140 , a source electrode 150 connected to one side of the semiconductor layer 145 , and a drain electrode 155 spaced apart from the source electrode 150 by a predetermined distance and connected to the other side of the semiconductor layer 145 . this is located Accordingly, the third TFT T21 including the second gate line G2 , the semiconductor layer 145 , the source electrode 150 , and the drain electrode 155 is configured.

In addition, the drain electrode 155 and the common line V1 overlap to form the third storage capacitor C21. At one side of the common line V1 , an auxiliary common line SV passes through the gate insulating layer 140 and is connected to the common line V1 . The auxiliary common line SV is formed simultaneously with the source electrode 150 or the drain electrode 155 . In addition, the extension VVE of the vertical common line VV is disposed to overlap the third gate line G3 to prevent a parasitic capacitor between the third gate line G3 and the third pixel electrode PX21 . .

A planarization layer 170 covering the third TFT T21 is disposed on the entire surface of the substrate 110 . A first contact hole CH1 exposing a portion of the drain electrode 155 and a third contact hole CH3 exposing a portion of the auxiliary common line SV are provided in the planarization layer 170 . A third pixel electrode PX21 , a third common electrode Vcom21 , and a vertical common line VV are positioned on the planarization layer 170 . The vertical common line VV is connected to the auxiliary common line SV through the third contact hole CH3 formed in the planarization layer 170 and the gate insulating layer 140 , and is also connected to the common line V1 . Accordingly, the display device according to the third embodiment of the present invention is configured.

<Fourth embodiment>

10 is a plan view illustrating a structure of a pixel array of a display device according to a fourth exemplary embodiment of the present invention. Hereinafter, the same reference numerals are assigned to the same components as those of the third embodiment to facilitate understanding.

Referring to FIG. 10 , a horizontal electric field liquid crystal display according to a fourth embodiment of the present invention includes gate lines G2 and G3 horizontally disposed on a substrate, a data line D1 formed to cross them, TFTs T21 and 12 formed at each intersection, pixel electrodes PX11, PX12, PX21, and PX22 and common electrodes Vcom11, Vcom12, Vcom21 formed to form a horizontal electric field in the pixel region provided in the intersection structure Vcom22), a common line V1 connected to the common electrodes Vcom11, Vcom12, Vcom21, and Vcom22 and disposed in parallel with the gate lines G2 and G3, and a pixel parallel to or overlapping with the data line D1 The vertical common line VV disposed between the electrodes PX11, PX12, PX21, and PX22 and connected to the common electrodes Vcom11, Vcom12, Vcom21, and Vcom22, and the data line D1 are disposed in parallel with but not overlapping Auxiliary common line (SV) is not included.

In the fourth embodiment of the present invention, unlike the structure of the aforementioned third embodiment, the extension of the vertical common line overlapped on the third gate line G3 is omitted. Accordingly, since the extension of the vertical common line is omitted, the opening ratio may be secured as much as the space occupied by the extension. The following description will be simplified because the third embodiment and the rest of the structure are the same.

In more detail, the first pixel electrode PX11 and the second pixel electrode PX12 are disposed adjacent to each other with the data line D1 interposed therebetween, and the third pixel electrode PX21 and the fourth pixel electrode PX22 are adjacent to each other. is laid out A second gate line G2 and a third gate line G3 crossing the data line D1 are disposed between the first pixel electrode PX11 and the third pixel electrode PX21 . Accordingly, the first pixel electrode PX11 is disposed to face the third pixel electrode PX21 with the second and third gate lines G2 and G3 interposed therebetween, and the second pixel electrode PX12 is the second and the fourth pixel electrode PX22 with the third gate lines G2 and G3 interposed therebetween.

A vertical common line VV parallel to the data line D1 is disposed between the first pixel electrode PX11 and the second pixel electrode PX12 and between the third pixel electrode PX21 and the fourth pixel electrode PX22 do. Also, the vertical common line VV is disposed adjacent to the data line D1 with the first pixel electrode PX11 and the third pixel electrode PX21 interposed therebetween, and the second pixel electrode PX12 and the fourth pixel electrode PX12 are disposed adjacent to each other. It is disposed adjacent to the data line D1 with the pixel electrode 22 interposed therebetween. The vertical common line VV is integrated with the first to fourth common electrodes Vcom11 , Vcom12 , Vcom21 , and Vcom22 to have a mesh shape.

The second storage capacitor C12 is disposed between the second pixel electrode PX12 and the fourth pixel electrode PX22 and is disposed between the second pixel electrode PX12 and the third gate line G3 . The third storage capacitor C21 is disposed between the first pixel electrode PX11 and the third pixel electrode PX21 , and is disposed between the third pixel electrode PX21 and the second gate line G2 . The second TFT T12 is included at the intersection of the data line D1 adjacent to the second storage capacitor C12 and the third gate line G3 and the data line D1 adjacent to the third storage capacitor C21 is A third TFT T21 is included at the intersection of the second gate line G2 and the second gate line G2 .

A third TFT T21 is disposed at the intersection of the second gate line G2 and the data line D1 . The third TFT T21 includes a source electrode 150 branched from the data line D1 and a drain electrode 155 extending from the third TFT T21 . The drain electrode 155 overlaps the common line V1 to form a third storage capacitor C21 . A third pixel electrode PX21 extending from a region overlapping the drain electrode 155 and the first storage capacitor C11 is positioned. The third pixel electrode PX21 is located in the third pixel P3 . The third pixel electrode PX21 is connected to the drain electrode 155 through the first contact hole CH1 to receive a data voltage from the third TFT T21 . In addition, the third common electrode Vcom21 receives a common voltage from the vertical common line VV to form a horizontal electric field with the third pixel electrode PX21 . Accordingly, the third pixel P3 includes the third TFT T21 , the third pixel electrode PX21 , and the third common electrode Vcom21 .

Meanwhile, the second TFT T12 is disposed at the intersection of the third gate line G3 and the data line D1 . The second TFT T12 includes a source electrode 160 branched from the data line D1 and a drain electrode 165 extending from the second TFT T12 . The drain electrode 165 overlaps the common line V1 to form a second storage capacitor C12 . A second pixel electrode PX12 extending from a region where the drain electrode 165 and the second storage capacitor C12 overlap is positioned. The second pixel electrode PX12 is located in the second pixel P2 . The second pixel electrode PX12 is connected to the drain electrode 165 through the second contact hole CH2 to receive a data voltage from the second TFT T12 . In addition, the second common electrode Vcom12 receives a common voltage from the vertical common line VV to form a horizontal electric field with the second pixel electrode PX12 . Accordingly, the second pixel P2 includes the second TFT T12 , the second pixel electrode PX12 , and the second common electrode Vcom12 . The remaining first pixel P1 and fourth pixel P4 are also configured in the same manner as the second pixel P2 and third pixel P3 . The common line V1 supplies a common voltage to the vertical common line VV in an area adjacent to the third pixel P3 through the third contact hole CH3.

The above-described second pixel P2 and third pixel P3 have a structure that shares one common line V1 . Specifically, the common line V1 is disposed in parallel with the second gate line G2 and the third gate line G3 and is disposed between the second gate line G2 and the third gate line G3. . Accordingly, the common line V1 forms the drain electrode 155 and the third capacitor C21 of the third pixel P3, and connects the drain electrode 165 and the second capacitor C12 of the second pixel P2. accomplish

In the display device according to the fourth embodiment of the present invention, one common line is disposed between the gate lines so that two pixels share a common line in order to reduce the distance between the pixels having a vertical relationship. As shown in FIG. 10 , the common line V1 is disposed between the second gate line G2 and the third gate line G3 and consists of one. Accordingly, the gap between the first pixel P1 and the third pixel P2 or between the second pixel P2 and the fourth pixel P4 is reduced, thereby improving the aperture ratio of the pixels.

Hereinafter, a cross-sectional structure of a pixel array of a display device according to a fourth embodiment of the present invention will be described in more detail with reference to FIG. 11 . 11 is a cross-sectional view taken along line V-V' of FIG. 10 .

Referring to FIG. 11 , the second gate line G2 , the third gate line G3 , and the common line V1 are disposed in parallel on the substrate 110 . The second gate line G2 serves as a gate electrode. The second gate line G2 , the third gate line G3 , and the common line V1 gate insulating layer 140 are disposed over the entire surface of the substrate 110 . The semiconductor layer 145 is positioned on the gate insulating layer 140 to overlap the second gate line G2 . In addition, on the gate insulating layer 140 , a source electrode 150 connected to one side of the semiconductor layer 145 , and a drain electrode 155 spaced apart from the source electrode 150 by a predetermined distance and connected to the other side of the semiconductor layer 145 . this is located Accordingly, the third TFT T21 including the second gate line G2 , the semiconductor layer 145 , the source electrode 150 , and the drain electrode 155 is configured.

In addition, the drain electrode 155 and the common line V1 overlap to form the third storage capacitor C21. At one side of the common line V1 , an auxiliary common line SV passes through the gate insulating layer 140 and is connected to the common line V1 . The auxiliary common line SV is formed simultaneously with the source electrode 150 or the drain electrode 155 . A planarization layer 170 covering the third TFT T21 is disposed on the entire surface of the substrate 110 . A first contact hole CH1 exposing a portion of the drain electrode 155 and a third contact hole CH3 exposing a portion of the auxiliary common line SV are provided in the planarization layer 170 . A third pixel electrode PX21 , a third common electrode Vcom21 , and a vertical common line VV are positioned on the planarization layer 170 . The vertical common line VV is connected to the auxiliary common line SV through the third contact hole CH3 formed in the planarization layer 170 and the gate insulating layer 140 , and is also connected to the common line V1 . Accordingly, the display device according to the fourth embodiment of the present invention is configured.

12 is a diagram comparing the pixel array of the conventional display device and the pixel array of the display device according to the first embodiment of the present invention.

Referring to FIG. 12 , in the pixel array of the conventional display device, the distance between pixels is about 125 μm. On the other hand, in the pixel array of the display device according to the first embodiment of the present invention, it can be seen that the distance between the pixels is reduced by about 30% to 90.5 μm.

In the display device according to the first embodiment of the present invention, the TFT and the storage capacitor are disposed adjacent to each other based on a vertical common line, and the TFT and the storage capacitor are disposed adjacent to each other based on the vertical common line using a bridge pixel electrode. It is connected to the pixel electrode of the pixel arranged in the same manner. Accordingly, due to the structure in which the conventional storage capacitor faces and the source electrode is extended, it is possible to reduce the gap between pixels, thereby improving the aperture ratio.

13 is a diagram illustrating an aperture ratio of a pixel of a display device according to a second embodiment to a fourth embodiment of the present invention.

Pixels of the display device according to the second, third, and fourth embodiments of the present invention were fabricated, and the aperture ratio of each pixel was measured. Here, each pixel was formed to have the same size as a pixel size based on 55 inches.

Referring to FIG. 13 , the display device according to the second embodiment of the present invention has a structure in which two gate lines and two common lines are provided while sharing one data line, and the pixel aperture ratio is 64.%. The display device according to the third exemplary embodiment of the present invention has a structure in which two gate lines are provided while sharing one data line and one common line, and the pixel aperture ratio is 67.1%. The display device according to the fourth embodiment of the present invention has the same structure as that of the third embodiment, except that the extension of the common line between the gate line and the pixel electrode is omitted, and the pixel aperture ratio is 70.2%.

In the display device according to the above-described second to fourth embodiments of the present invention, one common line is disposed between the gate lines so that two pixels share a common line, thereby reducing the vertical distance between the pixels to improve the aperture ratio of the pixel. There are advantages to doing it.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display device 110: substrate
140: gate insulating film 145: semiconductor layer
150: source electrode 155: drain electrode
170: planarization layer G1: first gate line
V1: first common line VV: vertical common line
D1: first data line D2: second data line
PX11: first pixel electrode Vcom11: first common electrode

Claims (13)

a first pixel including a first pixel electrode, a first common electrode forming an electric field with the first pixel electrode, and a first storage capacitor;
a second pixel including a second pixel electrode, a second common electrode forming an electric field with the second pixel electrode, and a second storage capacitor; and
The first pixel electrode and the second pixel electrode are disposed between adjacent first and second data lines, and a vertical common line parallel to the data lines is formed between the first pixel electrode and the second pixel electrode. first and second gate lines intersecting the data lines are disposed between the first pixel electrode and the second pixel electrode;
The first storage capacitor and the second storage capacitor are disposed between the first pixel electrode and the second pixel electrode, and the first storage capacitor is opposite to the first pixel electrode with respect to the vertical common line. and the second storage capacitor is positioned opposite to the second pixel electrode with respect to a vertical common line;
A first bridge pixel electrode connecting the first pixel electrode from the first storage capacitor and a second bridge pixel electrode connecting the second pixel electrode from the second storage capacitor are disposed; A pixel electrode and the second bridge pixel electrode intersect the vertical common line. According to claim 1,
The first pixel includes a first TFT positioned at the intersection of the first data line and the first gate line, and the second pixel is positioned at the intersection of the second data line and the second gate line. A display device including a second TFT. 3. The method of claim 2,
A first common line parallel to the first gate line is disposed opposite the first gate line with the first pixel electrode interposed therebetween, and opposite the second gate line with the second pixel electrode interposed therebetween a second common line parallel to the second gate line is disposed on the display device, the first common line is connected to the first common electrode, and the second common line is connected to the second common electrode. According to claim 1,
The first bridge pixel electrode and the first pixel electrode are integrally formed, and the second bridge pixel electrode and the second pixel electrode are integrally formed. According to claim 1,
The first gate line and the second gate line are positioned between the first storage capacitor and the second storage capacitor. a first pixel including a first pixel electrode, a first common electrode forming an electric field with the first pixel electrode, and a first storage capacitor;
a second pixel including a second pixel electrode, a second common electrode forming an electric field with the second pixel electrode, and a second storage capacitor; and
a data line is disposed between the first pixel electrode and the second pixel electrode, and first and second gate lines intersecting the data line are disposed between the first pixel electrode and the second pixel electrode; first and second common lines crossing the data line are disposed between the first pixel electrode and the second pixel electrode;
The first storage capacitor is disposed between the first gate line and the first pixel electrode, the second storage capacitor is disposed between the second gate line and the second pixel electrode, and the first storage capacitor and The second storage capacitor is positioned opposite to each other with respect to the data line. 7. The method of claim 6,
The first pixel includes a first TFT positioned at the intersection of the data line and the first gate line, and the second pixel includes a second TFT positioned at the intersection of the data line and the second gate line. wherein the first TFT and the second TFT share the data line. According to claim 1,
The first gate line and the second gate line are positioned between the first common line and the second common line. a first pixel including a first pixel electrode, a first common electrode forming an electric field with the first pixel electrode, and a first storage capacitor;
a second pixel including a second pixel electrode, a second common electrode forming an electric field with the second pixel electrode, and a second storage capacitor; and
a data line is disposed between the first pixel electrode and the second pixel electrode, and first and second gate lines crossing the data line are disposed between the first pixel electrode and the second pixel electrode;
a common line is disposed between the first gate line and the second gate line, the common line being included in the first storage capacitor and the second storage capacitor;
The first storage capacitor is disposed between the first gate line and the first pixel electrode, the second storage capacitor is disposed between the second gate line and the second pixel electrode, and the first storage capacitor and The second storage capacitor is positioned opposite to each other with respect to the data line. 10. The method of claim 9,
The first pixel includes a first TFT positioned at the intersection of the data line and the first gate line, and the second pixel includes a second TFT positioned at the intersection of the data line and the second gate line. wherein the first TFT and the second TFT share the data line. 11. The method of claim 10,
The first storage capacitor includes a drain electrode of the first TFT and the common line, and the second storage capacitor includes a drain electrode of the second TFT and the common line. 10. The method of claim 9,
a display that is parallel to the data line and includes an auxiliary common line adjacent to the data line with the first pixel and the second pixel interposed therebetween, wherein the auxiliary common line is connected to the common line through a contact hole Device. 10. The method of claim 9,
and a vertical common line surrounding the first pixel electrode and the second pixel electrode, wherein the vertical common line includes an extension overlapping the second gate line.

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