KR102009319B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a manufacturing method thereof. In an exemplary embodiment of the present invention, an LCD device includes data lines, gate lines intersecting the data lines, common voltage lines formed parallel to the data lines between the data lines, and the data lines. A liquid crystal display panel including pixel electrodes formed in a pixel region defined by intersections of the gate lines and the common voltage lines, and thin film transistors formed at intersections of the data lines and the gate lines; The gate electrode of the first thin film transistor formed at the intersection of the j th (j is at least two natural numbers) data lines and the k (k is at least two natural numbers) gate lines is connected to the k th gate line, and the source electrode is The drain electrode is connected to the j th data line and the drain electrode is disposed from the pixel electrode adjacent to the j-1 th data line or the j + 1 th data line. And a first protruding electrode extending through the first contact electrode.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes.

The liquid crystal display includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying data voltages to data lines of the liquid crystal display panel, and a gate line of the liquid crystal display panel. And a gate drive IC for supplying a gate pulse (or scan pulse) to the light sources (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, and the like.

Thanks to the rapid development of the process technology and the driving technology of the liquid crystal display device, the manufacturing cost of the liquid crystal display device is lowered and the image quality is greatly improved. In particular, a double rate driving (DRD) technique has been proposed in which two subpixels existing in one horizontal line are connected to one data line, and a data voltage having the same polarity is supplied to the two subpixels. The DRD technology can control two subpixels through one data line, thereby reducing manufacturing costs by reducing the number of source drive ICs. In the DRD technology, the source drive IC is driven in a column inversion manner to supply data voltages having different polarities to adjacent data lines, and the liquid crystal display panel is driven in horizontal two dot inversion.

Recently, as a variation of the DRD technology, the source drive IC is driven by column inversion, and the liquid crystal display panel is driven to satisfy both horizontal 2 dot inversion and vertical 1 dot inversion at the same time. Technology has been developed. However, the "E-inversion" technology has a disadvantage in that the design of the liquid crystal display panel is complicated. In addition, since the "E-inversion" technique connects a part of the pixels to a data line other than the adjacent data line, the common voltage line for supplying the common voltage to the common electrodes is formed on the same plane as the gate line. It is formed in a parallel direction. Since the common voltage line is formed of a gate metal layer that is an opaque metal layer, there is a problem that the aperture ratio is reduced.

The present invention provides a liquid crystal display device and a method for manufacturing the same, which can prevent the reduction of the aperture ratio while driving to satisfy horizontal two dot inversion and vertical one dot inversion at the same time.

In an exemplary embodiment of the present invention, an LCD device includes data lines, gate lines intersecting the data lines, common voltage lines formed parallel to the data lines between the data lines, and the data lines. A liquid crystal display panel including pixel electrodes formed in a pixel region defined by intersections of the gate lines and the common voltage lines, and thin film transistors formed at intersections of the data lines and the gate lines; The gate electrode of the first thin film transistor formed at the intersection of the j th (j is at least two natural numbers) data lines and the k (k is at least two natural numbers) gate lines is connected to the k th gate line, and the source electrode is The drain electrode is connected to the j th data line and the drain electrode is disposed from the pixel electrode adjacent to the j-1 th data line or the j + 1 th data line. And a first protruding electrode extending through the first contact electrode.

According to an exemplary embodiment of the present invention, a method of manufacturing a liquid crystal display device includes: a gate metal pattern including a gate line, an upper layer of a gate electrode of first and second thin film transistors, a pixel electrode, a first protruding electrode, A first step of forming a first transparent electrode pattern including a second protruding electrode and a lower layer of a gate electrode of the first and second thin film transistors; A gate insulating layer covering the gate metal pattern and the first transparent electrode pattern is formed, and a semiconductor pattern, a data line, a common voltage line, and source and drain electrodes of the first and second thin film transistors are formed on the gate insulating layer. A second step of forming a source / drain metal pattern comprising a; A first contact hole forming a passivation layer covering the source / drain metal pattern, exposing the drain electrode of the first thin film transistor through the passivation layer, and a second contact penetrating the passivation layer to expose the first protruding electrode A third contact hole exposing the common voltage line through the hole, the passivation layer; a fourth contact hole exposing the drain electrode of the second thin film transistor; and a fifth exposing the second protruding electrode through the passivation layer. Forming a contact hole; And a first contact electrode connecting the drain electrode of the first thin film transistor and the first protruding electrode through the first contact hole and the second contact hole, and the common voltage line and the common electrode through the third contact hole. A second transparent electrode pattern including a common electrode connecting the second electrode and a second contact electrode connecting the drain electrode of the second thin film transistor and the second protruding electrode through the fourth contact hole and the fifth contact hole; And a fourth step of forming the first thin film transistor, wherein the first thin film transistor is formed at an intersection of the j (j is two or more natural numbers) data lines and the k (k is two or more natural numbers) gate lines. Is connected to the k-th gate line, a source electrode is connected to the j-th data line, and a drain electrode is adjacent to the j-1th data line or the j + 1th data line That extended from the first protruding electrode and which is connected through the first contact electrode is characterized.

In the present invention, since the pixel electrode and the protruding electrode are formed on the same plane as the gate metal pattern, the pixel electrode and the drain electrode of the TFT can be connected by using the protruding electrode extending from the pixel electrode. As a result, the present invention can form a common voltage line between adjacent pixel electrodes in parallel with the data line, thereby preventing the reduction of the aperture ratio due to the common voltage line.

In addition, the present invention may form a gate metal pattern including a gate line and a gate electrode, and a transparent electrode pattern including a pixel electrode and a protruding electrode extending therefrom in one mask process. As a result, the present invention can reduce the manufacturing cost.

Furthermore, in the present invention, even though the source drive IC supplies the data voltages to the data lines in a column inversion manner, the pixel electrodes of the pixel array of the liquid crystal display panel are driven to satisfy the horizontal 2 dot inversion and the vertical 1 dot inversion at the same time. do. As a result, according to the present invention, the number of source drive ICs can be reduced, the power consumption can be reduced, and the DC afterimage of the liquid crystal can be prevented by the column inversion method.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
2 is an exemplary diagram illustrating subpixels of a pixel array according to a first exemplary embodiment of the present invention.
3 is a diagram illustrating data voltages and gate signals supplied to a pixel array according to an exemplary embodiment of the present invention.
4 is a plan view showing in detail two of the two sub-pixels of FIG.
5 is a cross-sectional view taken along line II ′ and II-II ′ of FIG. 4.
6 is an exemplary diagram illustrating subpixels of a pixel array according to a second exemplary embodiment of the present invention.
7 is a diagram illustrating subpixels of a pixel array according to a third exemplary embodiment of the present invention.
8 is a flowchart illustrating a manufacturing method of a liquid crystal display according to an exemplary embodiment of the present invention.
9A to 9D are cross-sectional views of II ′ and II-II ′ according to the first to fourth mask processes.
FIG. 10 is a flow chart showing details of the first mask process of FIG. 8; FIG.
11A-11F are cross-sectional views of II ′ illustrating the first mask process in detail.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of the ease of preparation of the specification, and may be different from the actual component names.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10 in which a pixel array PA is formed, and source drive integrated circuits 12. , A gate driving circuit 13, and a timing controller 11. A backlight unit for uniformly irradiating light onto the liquid crystal display panel 10 may be disposed under the liquid crystal display panel 10.

The liquid crystal display panel 10 includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer interposed therebetween. The pixel array PA is formed in the liquid crystal display panel 10. The pixel array PA displays digital video data using subpixels arranged in a matrix in a pixel area defined by an intersection structure of data lines, gate lines, and common voltage lines. The lower glass substrate of the pixel array PA includes data lines, gate lines, common voltage lines, thin film transistors (hereinafter referred to as TFTs), pixel electrodes of subpixels connected to TFTs, and A storage capacitor connected to the pixel electrode, and the like. Each of the subpixels of the pixel array PA displays an image by adjusting the amount of light transmitted by driving the liquid crystal of the liquid crystal layer by a voltage difference between a pixel electrode charged with a data voltage through a TFT and a common electrode applied with a common voltage. do. A detailed arrangement of the subpixels of the pixel array PA will be described in detail with reference to FIGS. 2, 5, and 6.

The black matrix and the color filter are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode is formed on the upper glass substrate in the case of the vertical electric field driving method such as TN (TwiPREd Nematic) mode and VA (Vertical Alignment) mode, and the In-Plane Switching (IPS) mode and the FFS (Fringe Field Switching) In the case of a horizontal electric field driving method such as), it is formed on the lower glass substrate together with the pixel electrode. In the embodiment of the present invention, the liquid crystal display is described as being implemented in the IPS mode. However, the present invention is not limited thereto, and the liquid crystal display may be implemented in any liquid crystal mode as well as in the TN mode, VA mode, IPS mode, and FFS mode. shall. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a tape carrier package (TCP) 15, bonded to a lower glass substrate of the liquid crystal display panel 10 by a tape automated bonding (TAB) process, and a source printed circuit board (PCB). 14). The source drive ICs 12 may be adhered to the lower glass substrate of the liquid crystal display panel 10 by a chip on glass (COG) process.

Each of the source drive ICs 12 receives digital video data and a source timing control signal from the timing controller 11. The source drive ICs 12 convert digital video data into positive / negative data voltages in response to a source timing control signal, and supply the digital video data to data lines of the pixel array PA. The source drive ICs 12 output data voltages to the data lines in a column inversion manner under the control of the timing controller 11. The column inversion method refers to a method of supplying data voltages having opposite polarities to neighboring data lines and maintaining the same polarity of data voltages supplied to each of the data lines for one frame period. For example, the source drive ICs 12 may output data voltages whose polarities are inverted in a column inversion manner to the data lines as shown in FIG. 7.

The gate driving circuit 13 receives a gate timing control signal from the timing controller 11. The gate driving circuit 13 sequentially supplies gate pulses (or scan pulses) to gate lines of the pixel array in response to the gate timing control signal. The gate driving circuit 13 may be mounted on the TCP and bonded to the lower glass substrate of the liquid crystal display panel 10 by a TAB process. Alternatively, the gate driving circuit 13 may be directly formed on the lower glass substrate simultaneously with the pixel array PA by a gate in panel (GIP) process. The gate driving circuit 13 may be disposed on one side of the pixel array PA or both sides of the pixel array PA as shown in FIG. 1.

The timing controller 11 receives digital video data and timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock from an external system board. The timing controller 11 may control a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing for controlling the operation timing of the gate driving circuit 13 based on the digital video data and the timing signals. Generate a control signal. The timing controller 11 supplies digital video data and a source timing control signal to the source drive ICs 12. The timing controller 11 supplies the gate timing control signal to the source drive ICs 12. The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 may be connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

2 is an exemplary diagram illustrating pixel electrodes of a pixel array according to a first exemplary embodiment of the present invention. 2 illustrates only some of the data lines and some of the gate lines formed in the pixel array for convenience of description. That is, FIG. 2 shows the first through fourth data lines D1, D2, D3, and D4 and the first through fourth gate lines G1, G2, G3, and G4 crossing them.

Referring to FIG. 2, common voltage lines VcomL are formed between the adjacent data lines and parallel to the data lines. That is, the common voltage line VcomL is formed between the j-th (j is two or more natural numbers) data line Dj and the j-1 th data line Dj-1. For example, as shown in FIG. 2, a common voltage line VcomL is formed between the first data line D1 and the second data line D2. In particular, the common voltage line VcomL may be formed between the pixel electrodes existing between the j th data line Dj and the j-1 th data line Dj-1. For example, the common voltage line VcomL is disposed between the first pixel electrode PE1 and the second pixel electrode PE2 that exist between the first data line D1 and the second data line D2 as shown in FIG. 2. Can be formed on.

Pixel electrodes are formed in the pixel region defined by the intersection of the data lines, the gate lines, and the common voltage lines VcomL. TFTs are formed at intersections of the data lines and the gate lines. Each of the pixel electrodes is connected to a TFT to receive a data voltage applied to a data line. Specifically, the source electrode of the TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk is connected to the j-th data line Dj and the drain electrode is adjacent to the j-th data line Dj. Is connected to the non-pixel electrode, that is, the pixel electrode adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1. In contrast, the source electrode of the TFT formed at the intersection of the j th data line Dj and the k-1 th gate line Gk-1 or the k + 1 th gate line Gk + 1 is the j th data line Dj. The drain electrode is connected to the pixel electrode adjacent to the j th data line Dj. For example, as shown in FIG. 2, the source electrode of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1 and is a drain electrode. May be connected to the second pixel electrode PE2 adjacent to the second data line D2 and not adjacent to the first data line D1. In contrast, the source electrode of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the first data line D1 and the drain electrode is connected to the first data line. It may be connected to the first pixel electrode PE1 adjacent to (D1). TFT and j-th data line Dj and k-th gate line Gk-1 or k + 1 th gate line Gk formed at the intersection of j-th data line Dj and k-th gate line Gk A detailed description of the connection structure of the TFTs formed at the intersections of +1) will be given later with reference to FIG.

In addition, only one of the pixel electrodes adjacent to the j th data line Dj is connected to the j th data line Dj in the same horizontal line, and the other pixel electrode is the j-1 data line Dj-1 or It is connected to the j + 1th data line Dj + 1. For example, as shown in FIG. 2, only the third pixel electrode PE3, which is adjacent to the second data line D2 and the third pixel electrode PE3, is connected to the second data line D2. The second pixel electrode PE2 may be connected to the first data line D1. 2, only the tenth pixel electrode PE10 of the tenth pixel electrode PE10 and the eleventh pixel electrode PE11 adjacent to the third data line D3 is connected to the third data line D3. The eleventh pixel electrode PE11 may be connected to the fourth data line D4.

Furthermore, the pixel electrodes between the j-th data line Dj and the j-th data line Dj-1 or the j + 1th data line Dj + 1 may be connected to only the jth data line Dj or j-th. It is connected only to the -1 data line Dj-1 or the j + 1th data line Dj + 1. For example, as illustrated in FIG. 2, the first pixel electrode PE1 and the second pixel electrode PE2 between the first data line D1 and the second data line D2 are connected only to the first data line D1. Can be. In addition, as illustrated in FIG. 2, the seventh pixel electrode PE7 and the eighth pixel electrode PE8 between the first data line D1 and the second data line D2 may be connected only to the second data line D2. have.

3 is a diagram illustrating data voltages and gate signals supplied to a pixel array according to an exemplary embodiment of the present invention. 3 shows data voltages output from the source drive IC 12 and gate pulses output from the gate driving circuit 13 during the Nth (N is a natural number) frame period and the N + 1th frame period. In FIG. 3, for convenience of description, the first to fourth data voltages DV1 to DV4 supplied to the first to fourth data lines D1 to D4 of FIG. 2, and the first to fourth parts of FIG. 2. Only the first to fourth gate pulses GP1 to GP4 supplied to the gate lines G1 to G4 are illustrated. That is, DV1 is the first data voltages supplied to the first data line D1, DV2 is the second data voltages supplied to the second data line D2, and DV3 is supplied to the third data line D3. The third data voltages DV4 refer to fourth data voltages supplied to the fourth data line D4. GP1 is a first gate pulse supplied to the first gate line G1, GP2 is a second gate pulse supplied to the second gate line G2, and GP3 is a third gate pulse supplied to the third gate line G3. GP4 denotes a fourth gate pulse supplied to the fourth gate line GP4.

Referring to FIG. 3, the source drive IC 12 supplies data voltages to data lines in a column inversion manner. The column inversion method refers to a method of supplying data voltages having opposite polarities to neighboring data lines and maintaining the same polarity of data voltages supplied to each of the data lines for one frame period. For example, the source drive IC 12 supplies the first data voltages DV1 of the first polarity to the first data line D1 during the Nth frame period, as shown in FIG. 3, and the second of the second polarity. The data voltages DV2 are supplied to the second data line D2, the third data voltages DV3 of the first polarity are supplied to the third data line D3, and the fourth data voltages of the second polarity are supplied. Field DV4 is supplied to the fourth data line D4. In addition, the source drive IC 12 supplies the first data voltages DV1 of the second polarity to the first data line D1 during the N + 1 frame period, as shown in FIG. 3, and the second of the first polarity. The data voltages DV2 are supplied to the second data line D2, the third data voltages DV3 of the second polarity are supplied to the third data line D3, and the fourth data voltage of the first polarity is supplied. Field DV4 is supplied to the fourth data line D4. In FIG. 3, the first polarity is the positive polarity and the second polarity is the negative polarity. However, the present invention is not limited thereto. That is, the first polarity may be implemented as a negative polarity, and the second polarity may be implemented as a positive polarity.

The gate driving circuit 13 sequentially outputs gate pulses to the gate lines. For example, the gate driving circuit 13 outputs the first gate pulse GP1 to the first gate line G1 in each of the Nth frame period and the N + 1th frame period, as shown in FIG. 3, and the second gate. The second gate pulse GP2 is output to the line G2, the third gate pulse GP3 is output to the third gate line G3, and the fourth gate pulse GP4 is output to the fourth gate line G4. Outputs Each of the gate pulses is generated at the gate high voltage VGH for a predetermined period of time. The predetermined period may be implemented as two horizontal periods 2H as shown in FIG. 3, in which case the gate pulses may overlap each other by approximately one horizontal period 1H as shown in FIG. 3. However, the predetermined period is not limited thereto, and may be implemented as one horizontal period 1H or several horizontal periods. One horizontal period 1H means one line scanning time in which digital video data is written in pixels of one horizontal line in the display panel 10.

Hereinafter, a method of supplying data to the pixel electrodes of the pixel array during the N frame period will be described in detail with reference to FIGS. 2 and 3.

The second, fourth, and sixth pixel electrodes PE2, PE4, and PE6 are supplied with data voltages in response to the first gate pulse GP1 during the first period t1 and the second period t2. The second pixel electrode PE2 connected to the first data line D1 is charged with the first data voltage DV1 of the first polarity supplied during the second period t2. The fourth pixel electrode PE4 connected to the second data line D2 is charged with the second data voltage DV2 of the first polarity supplied during the second period t2. The sixth pixel electrode PE6 connected to the third data line D3 is charged with the third data voltage DV3 of the first polarity supplied during the second period t2.

The first, third, and fifth pixel electrodes PE1, PE3, and PE5 receive the data voltages in response to the second gate pulse GP2 during the second period t2 and the third period t3. The first pixel electrode PE1 connected to the first data line D1 is charged with the first data voltage DV1 of the first polarity supplied during the third period t3. The third pixel electrode PE3 connected to the second data line D2 is charged with the second data voltage DV2 of the first polarity supplied during the third period t3. The fifth pixel electrode PE5 connected to the third data line D3 is charged with the third data voltage DV3 of the first polarity supplied during the third period t3.

During the third period t3 and the fourth period t4, the eighth, tenth, and twelfth pixel electrodes PE8, PE10, and PE12 receive data voltages in response to the third gate pulse GP3. The eighth pixel electrode PE8 connected to the second data line D2 is charged with the second data voltage DV2 of the second polarity supplied during the fourth period t4. The tenth pixel electrode PE10 connected to the third data line D3 is charged with the third data voltage DV3 of the first polarity supplied during the fourth period t4. The twelfth pixel electrode PE12 connected to the fourth data line D4 is charged with the fourth data voltage DV4 of the second polarity supplied during the fourth period t4.

During the fourth period t4 and the fifth period t5, the seventh, ninth, and eleventh pixel electrodes PE7, PE9, and PE11 receive data voltages in response to the fourth gate pulse GP4. The seventh pixel electrode PE7 connected to the second data line D2 is charged with the second data voltage DV2 of the second polarity supplied during the fifth period t5. The ninth pixel electrode PE9 connected to the third data line D3 is charged with the third data voltage DV3 of the first polarity supplied during the fifth period t5. The eleventh pixel electrode PE11 connected to the fourth data line D4 is charged with the fourth data voltage DV4 of the second polarity supplied during the fifth period t5.

In sum, the pixel electrodes of the pixel array according to the first exemplary embodiment of the present invention are implemented to satisfy both horizontal 2 dot inversion and vertical 1 dot inversion as shown in FIG. 2. The horizontal two dot inversion means that the polarity of the data voltage charged in every two pixel electrodes in the horizontal direction (the x-axis direction of FIG. 2) is changed. Vertical 1 dot inversion means that the polarity of the data voltage charged per pixel electrode in the vertical direction (y-axis direction in FIG. 2) is changed. For example, the first and second pixel electrodes PE1 and PE2 are supplied with a data voltage of a first polarity, and the third and fourth pixel electrodes PE3 and PE4 are supplied with a data voltage of a second polarity. The fifth and sixth pixel electrodes PE5 and PE6 satisfy the horizontal 2-dot inversion since the data voltages of the first polarity are supplied. In addition, since the data voltages of the first polarity are supplied to the first and second pixel electrodes PE1 and PE2, and the data voltages of the second polarity are supplied to the seventh and eighth pixel electrodes PE7 and PE8. Satisfies vertical 1 dot inversion.

As a result, although the source drive IC 12 supplies the data voltages to the data lines in a column inversion manner, the pixel electrodes of the pixel array of the liquid crystal display panel 10 simultaneously perform horizontal two dot inversion and vertical one dot inversion. Driven to satisfy. As a result, according to the first embodiment of the present invention, the number of source drive ICs can be reduced, the power consumption can be significantly reduced, and the DC afterimage can be prevented.

In addition, the third, fourth, seventh, and eighth pixel electrodes PE3, PE4, PE7, and PE8 may include a fourth pixel electrode PE4, a third pixel electrode PE3, an eighth pixel electrode PE8, The data voltages are charged in the order of the seventh pixel electrode PE7. The fifth, sixth, ninth, and tenth pixel electrodes PE5, PE6, PE9, and PE10 are the sixth pixel electrode PE6, the fifth pixel electrode PE5, the ninth pixel electrode PE9, and the tenth pixel electrode. The data voltages are charged in the pixel electrode PE10 order.

On the other hand, the conventional "E-inversion" technique described in the background art charges the data voltages to the pixel electrodes in a different order from the above. Because of this, the conventional "E-Inversion" technique supplies peak black gray scale data voltages to the red and green pixel electrodes among the red, green, and blue pixel electrodes and peaks to the blue pixel electrodes. In the case of supplying data voltages of white gray scale, peak black gray and peak white gray are successively supplied to one blue pixel electrode during a charging period (gate pulse supply period), and to other blue pixel electrodes. Peak white gradation was continuously supplied during the charging period (the gate pulse supply period). As a result, a difference occurs in the data voltage charged between the blue pixel electrodes, thereby causing a blue spot. However, in the data supply method to the pixel electrodes of the pixel array according to the first embodiment of the present invention, all of the blue pixel electrodes are continuously supplied with the peak black gray and the peak white gray during the charging period (the gate pulse supply period). Thus, the present invention can solve the blue spot problem that occurred in the conventional "E-inversion" technology.

4 is a plan view illustrating in detail a first subpixel including a first pixel electrode and a second subpixel including a second pixel electrode of FIG. 2. In FIG. 4, only the first subpixel including the first pixel electrode PE1 and the second subpixel including the second pixel electrode PE2 are illustrated for convenience of description. In FIG. 4, the first and second subpixels have been described as being implemented in the IPS mode, which is a horizontal electric field method. However, the present invention is not limited thereto and may be implemented in an FFS mode, a TN mode, or a VA mode. In FIG. 4, the first TFT T1 is a TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk, and the source electrode is connected to the j-th data line Dj and the drain electrode is An example of a TFT connected to a pixel electrode not adjacent to the j th data line Dj, that is, a pixel electrode adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1 It became. The second TFT T2 is a TFT formed at an intersection of the j-th data line Dj and the k-th gate line Gk-1 or the k + 1th gate line Gk + 1, and is a source electrode. Is connected to the j th data line Dj and the drain electrode is described as an example of a TFT connected to the pixel electrode adjacent to the j th data line Dj.

Referring to FIG. 4, the data lines D1 and D2 are formed in a vertical direction (y axis direction). The gate lines G1 and G2 are formed in a horizontal direction (x-axis direction) to intersect the data lines D1 and D2. The common voltage lines VcomL are formed in the vertical direction (y-axis direction) in parallel with the data lines D1 and D2. The common voltage line VcomL is formed between adjacent data lines D1 and D2. In particular, the common voltage line VcomL may be formed between the first and second pixel electrodes PE1 and PE2 existing between the adjacent data lines D1 and D2. The common electrode VcomE is connected to the common voltage line VcomL through the third contact hole CNT3. When implemented in the IPS mode as shown in FIG. 4, the first and second pixel electrodes PE1 and PE2 are formed over the entire pixel area, but the common electrode VcomE is formed in a slit shape in the pixel area. As a result, the first and second pixel electrodes PE1 and PE2 and the common electrode VcomE may form a horizontal electric field. The pixel region in which the first and second pixel electrodes PE1 and PE2 are formed is defined by the intersection of the data lines D1 and D2, the gate lines G1 and G2, and the common voltage line VcomL. .

TFTs T1 and T2 are formed at intersections of the data lines D1 and D2 and the gate lines G1 and G2. Each of the first and second pixel electrodes PE1 and PE2 is connected to a TFT to receive a data voltage applied to a data line. Specifically, the source electrode of the TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk is connected to the j-th data line Dj and the drain electrode is adjacent to the j-th data line Dj. Is connected to the non-pixel electrode, that is, the pixel electrode adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1. In contrast, the source electrode of the TFT formed at the intersection of the j th data line Dj and the k-1 th gate line Gk-1 or the k + 1 th gate line Gk + 1 is the j th data line Dj. The drain electrode is connected to the pixel electrode adjacent to the j th data line Dj.

For example, as shown in FIG. 4, the source electrode SE1 of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1. However, the drain electrode DE1 may be connected to the second pixel electrode PE2 adjacent to the second data line D2 instead of adjacent to the first data line D1. In particular, the drain electrode DE1 extends from the second pixel electrode PE2 through the first contact electrode CE1 formed in the first contact hole CNT1 and the second contact hole CNT2. ) Can be connected. That is, the first contact electrode CE1 is connected to the drain electrode DE1 of the first TFT T1 in the first contact hole CNT1 and the first protruding electrode STE1 in the second contact hole CNT2. Connected. The length of the first protruding electrode STE1 may be longer than that of the drain electrode DE1 of the first TFT T1.

In addition, as shown in FIG. 4, the source electrode SE2 of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the second data line D2. The drain electrode DE2 may be connected to the first pixel electrode PE1 adjacent to the first data line D1. The drain electrode DE2 of the second TFT T2 is formed in the second protruding electrode STE2, the fourth contact hole CNT4, and the fifth contact hole CNT5 extending from the first pixel electrode PE1. It may be connected through the contact electrode CE2. That is, the second contact electrode CE2 is connected to the drain electrode DE2 of the second TFT T2 in the fourth contact hole CNT4 and the second protruding electrode STE2 in the fifth contact hole CNT5. Connected. In this case, the length of the second protrusion electrode STE2 may be shorter than the length of the first protrusion electrode STE1 and shorter than the length of the drain electrode DE2 of the second TFT T2.

4, a portion of the first protrusion electrode STE1 overlaps a portion of the drain electrode DE1 of the first TFT T1, and a portion of the second protrusion electrode STE2 is the second TFT T2. It may be overlapped with a part of the drain electrode DE2 of, but is not limited thereto. That is, the first protruding electrode STE1 may be formed so as not to overlap the drain electrode DE1 of the first TFT T1 at all, and the second protruding electrode STE2 is the drain electrode of the second TFT T2. It may be formed so as not to overlap with DE2) at all.

5 is a cross-sectional view taken along line II ′ and II-II ′ of FIG. 4. 4 and 5, on the lower substrate SUB, a gate line, an upper layer GE1U of the gate electrode GE1 of the first TFT T1, and an upper layer of the gate electrode GE2 of the second TFT T2 ( A gate metal pattern including GE2U, a lower layer GE1B of the gate electrode GE1 of the first TFT T1, a lower layer GE2B of the gate electrode GE2 of the second TFT T2, a pixel electrode, and a first A first transparent electrode pattern including the first protruding electrode STE1 and the second protruding electrode STE2 is formed. That is, the gate electrode GE1 of the first TFT T1 and the gate electrode GE2 of the second TFT T2 have a double layer structure of a lower layer GE1B of the first transparent electrode pattern and an upper layer GE1U of the gate metal pattern. Is formed.

A gate insulating layer GI covering the gate metal pattern and the first transparent electrode pattern is formed on the entire surface of the lower substrate SUB. A semiconductor pattern SEM is formed on the gate insulating layer GI, and a data line, a source electrode SE1 and a drain electrode DE1 of the first TFT T1, and a source electrode of the second TFT T2 are formed on the semiconductor pattern GI. A source / drain metal pattern including SE2), drain electrode DE2, and common voltage line VcomL is formed.

The passivation film PAS covering the source / drain metal pattern is formed on the entire surface of the lower substrate SUB. After the passivation layer PAS is formed, the first contact hole CNT1, the gate insulating layer GI, and the passivation layer PAS are formed through the passivation layer PAS to expose the drain electrode DE1 of the first TFT T1. A second contact hole CNT2 penetrating to expose the first protruding electrode STE1 and a third contact hole CNT3 penetrating the passivation layer PAS to expose the common voltage line VcomL are formed. In addition, the second projecting electrode C penetrates through the fourth contact hole CNT4 exposing the drain electrode DE2 of the second TFT T2 through the passivation layer PAS, the gate insulating layer GI, and the passivation layer PAS. A fifth contact hole CNT5 exposing STE2) is formed.

After forming the contact holes, a second transparent electrode pattern including the common electrode VcomE, the first contact electrode CE1, and the second contact electrode CE2 is formed. The common electrode VcomE is connected to the common voltage line VcomL through the third contact hole CNT3. The first contact electrode CE1 is connected to the drain electrode DE1 of the first TFT T1 through the first contact hole CNT1, and the first protruding electrode STE1 through the second contact hole CNT2. Connected. That is, the first contact electrode CE1 connects the drain electrode DE1 of the first TFT T1 and the first protruding electrode STE1. In addition, the second contact electrode CE2 is connected to the drain electrode DE2 of the second TFT T2 through the fourth contact hole CNT4 and the second protruding electrode STE2 through the fifth contact hole CNT5. ) Is connected. That is, the second contact electrode CE2 connects the drain electrode DE2 of the second TFT T2 and the second protruding electrode STE2.

4 and 5 illustrate only the first subpixel including the first pixel electrode PE1 and the second subpixel including the second pixel electrode PE2 in FIG. 2. However, the seventh sub-pixel including the seventh pixel electrode PE7 and the eighth sub-pixel including the eighth pixel electrode PE8 may include TFTs connected to the pixel electrodes and the first protruding electrode STE1. ) And only the formation position of the second protruding electrode STE2 may be substantially the same as described with reference to FIGS. 4 and 5. That is, the connection configuration of the seventh TFT T7 connected to the seventh pixel electrode PE7 is a TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk, and the source electrode is j-th. The drain electrode connected to the data line Dj and not adjacent to the j th data line Dj, that is, the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1 It can be formed similarly to the first TFT (T1) of FIG. 2 illustrated as a TFT connected to an adjacent pixel electrode. The connection configuration of the eighth TFT T8 connected to the eighth pixel electrode PE8 may include a j-th data line Dj and a k-th gate line Gk-1 or a k-th gate line Gk + 1. As a TFT formed at an intersection portion of the second TFT of FIG. 2 illustrated as a TFT connected to a source electrode connected to a j th data line Dj and a drain electrode connected to a pixel electrode adjacent to a j th data line Dj. It can be formed similarly to T2).

As described above, the present invention forms the pixel electrode on the same plane as the gate metal pattern, so that the pixel electrode and the drain electrode of the TFT can be connected by using the protruding electrode extending from the pixel electrode. As a result, the present invention can form a common voltage line between adjacent pixel electrodes in parallel with the data line, thereby reducing the reduction in openings caused by the common voltage line.

6 is an exemplary diagram illustrating subpixels of a pixel array according to a second exemplary embodiment of the present invention. For convenience of description, only some of the data lines and some of the gate lines of the pixel array are illustrated in FIG. 6. That is, FIG. 6 shows the first to fourth data lines D1, D2, D3, and D4 and the first to fourth gate lines G1, G2, G3, and G4 crossing them. The gate lines, the data lines, and the common voltage line VcomL of FIG. 6 are substantially the same as described with reference to FIG. 2. Therefore, description thereof will be omitted.

Referring to FIG. 6, each of the pixel electrodes is connected to a TFT to receive a data voltage applied to a data line. Specifically, the source electrode of the TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk is connected to the j-th data line Dj and the drain electrode is adjacent to the j-th data line Dj. Is connected to the non-pixel electrode, that is, the pixel electrode adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1. In contrast, the source electrode of the TFT formed at the intersection of the j th data line Dj and the k-1 th gate line Gk-1 or the k + 1 th gate line Gk + 1 is the j th data line Dj. The drain electrode is connected to the pixel electrode adjacent to the j th data line Dj. For example, as shown in FIG. 6, the source electrode of the second TFT T2 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the first data line D1 and drained. The electrode may be connected to the second pixel electrode PE2 adjacent to the second data line D2 without being adjacent to the first data line D1. In contrast, the source electrode of the first TFT T1 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1, and the drain electrode is connected to the first data. It may be connected to the first pixel electrode PE1 adjacent to the line D1.

In particular, the TFT and the j-th data line Dj and the k-th gate line Gk-1 or the k + 1th gate line formed at the intersection of the j-th data line Dj and the k-th gate line Gk The connection structure of the TFT formed at the intersection of (Gk + 1) has already been described in detail with reference to FIG. In the pixel array shown in FIG. 6, only the formation positions of the TFTs connected to the pixel electrodes, the first protrusion electrode STE1, and the second protrusion electrode STE2 differ, and are substantially the same as those described with reference to FIGS. 4 and 5. The same can be formed.

In addition, only one of the pixel electrodes adjacent to the j th data line Dj is connected to the j th data line Dj in the same horizontal line, and the other pixel electrode is the j-1 data line Dj-1 or It is connected to the j + 1th data line Dj + 1. For example, as shown in FIG. 6, only the third pixel electrode PE3, which is adjacent to the second data line D2 and the third pixel electrode PE3, is connected to the second data line D2. The second pixel electrode PE2 may be connected to the first data line D1. 6, only the tenth pixel electrode PE10 of the tenth pixel electrode PE10 and the eleventh pixel electrode PE11 adjacent to the third data line D3 is connected to the third data line D3. The eleventh pixel electrode PE11 may be connected to the fourth data line D4.

Furthermore, the pixel electrodes between the j-th data line Dj and the j-th data line Dj-1 or the j + 1th data line Dj + 1 may be connected to only the jth data line Dj or j-th. It is connected only to the -1 data line Dj-1 or the j + 1th data line Dj + 1. For example, as illustrated in FIG. 6, the first pixel electrode PE1 and the second pixel electrode PE2 between the first data line D1 and the second data line D2 are connected only to the first data line D1. Can be. In addition, as shown in FIG. 6, the seventh pixel electrode PE7 and the eighth pixel electrode PE8 between the first data line D1 and the second data line D2 may be connected only to the second data line D2. have.

Furthermore, data pixels and gate signals may be supplied to the subpixels of the pixel array according to the second exemplary embodiment of the present invention. The subpixels of the pixel array according to the second exemplary embodiment of the present invention only differ in the charging order of the pixel electrodes, and the detailed driving method is substantially the same as described with reference to FIG. 3. Therefore, even though the source drive IC 12 supplies data voltages to the data lines in a column inversion manner, the pixel electrodes of the pixel array of the liquid crystal display panel 10 simultaneously perform horizontal two dot inversion and vertical one dot inversion. Driven to satisfy. As a result, according to the second embodiment of the present invention, the number of source drive ICs can be reduced, the power consumption can be significantly reduced, and the DC afterimage of the liquid crystal can be prevented by the column inversion method.

6, the third, fourth, seventh, and eighth pixel electrodes PE3, PE4, PE7, and PE8 may include the third pixel electrode PE3, the fourth pixel electrode PE4, and the eighth pixel electrode. PE8 and the seventh pixel electrode PE7 are charged in the data voltages. The fifth, sixth, ninth, and tenth pixel electrodes PE5, PE6, PE9, and PE10 may include a fifth pixel electrode PE5, a sixth pixel electrode PE6, a tenth pixel electrode PE10, and a ninth pixel electrode. The data voltages are charged in the pixel electrode PE9 order. As a result, the present invention can solve the blue spot problem that occurred in the conventional "E-inversion" technique as described in FIG.

7 is an exemplary diagram illustrating subpixels of a pixel array according to a third exemplary embodiment of the present invention. For convenience of description, only some of the data lines and some of the gate lines of the pixel array are illustrated in FIG. 7. That is, FIG. 7 shows the first to fourth data lines D1, D2, D3, and D4 and the first to fourth gate lines G1, G2, G3, and G4 crossing them. The gate lines, the data lines, and the common voltage line VcomL of FIG. 7 are substantially the same as described with reference to FIG. 2. Therefore, description thereof will be omitted.

Referring to FIG. 7, each of the pixel electrodes is connected to a TFT to receive a data voltage applied to a data line. Specifically, the source electrode of the TFT formed at the intersection of the j-th data line Dj and the k-th gate line Gk is connected to the j-th data line Dj and the drain electrode is adjacent to the j-th data line Dj. Is connected to the non-pixel electrode, that is, the pixel electrode adjacent to the j-1 th data line Dj-1 or the j + 1 th data line Dj + 1. In contrast, the source electrode of the TFT formed at the intersection of the j th data line Dj and the k-1 th gate line Gk-1 or the k + 1 th gate line Gk + 1 is the j th data line Dj. The drain electrode is connected to the pixel electrode adjacent to the j th data line Dj. For example, as shown in FIG. 7, the source electrode of the second TFT T2 formed at the intersection of the first data line D1 and the first gate line G1 is connected to the first data line D1 and drained. The electrode may be connected to the second pixel electrode PE2 adjacent to the second data line D2 without being adjacent to the first data line D1. In contrast, the source electrode of the first TFT T1 formed at the intersection of the first data line D1 and the second gate line G2 is connected to the first data line D1, and the drain electrode is connected to the first data. It may be connected to the first pixel electrode PE1 adjacent to the line D1.

In particular, the TFT and the j-th data line Dj and the k-th gate line Gk-1 or the k + 1th gate line formed at the intersection of the j-th data line Dj and the k-th gate line Gk The connection structure of the TFT formed at the intersection of (Gk + 1) has already been described in detail with reference to FIG. The pixel array shown in FIG. 7 differs only from the formation positions of the TFTs connected to the pixel electrodes, the first protrusion electrode STE1, and the second protrusion electrode STE2, and is substantially the same as described with reference to FIGS. 4 and 5. The same can be formed.

In addition, only one of the pixel electrodes adjacent to the j th data line Dj is connected to the j th data line Dj in the same horizontal line, and the other pixel electrode is the j-1 data line Dj-1 or It is connected to the j + 1th data line Dj + 1. For example, as shown in FIG. 7, only the third pixel electrode PE3, which is adjacent to the second data line D2 and the third pixel electrode PE3, is connected to the second data line D2. The second pixel electrode PE2 may be connected to the first data line D1. In addition, as shown in FIG. 7, only the tenth pixel electrode PE10 of the tenth pixel electrode PE10 and the eleventh pixel electrode PE11 adjacent to the third data line D3 is connected to the third data line D3. The eleventh pixel electrode PE11 may be connected to the fourth data line D4.

Furthermore, the pixel electrodes between the j-th data line Dj and the j-th data line Dj-1 or the j + 1th data line Dj + 1 may be connected to only the jth data line Dj or j-th. It is connected only to the -1 data line Dj-1 or the j + 1th data line Dj + 1. For example, as illustrated in FIG. 7, the first pixel electrode PE1 and the second pixel electrode PE2 between the first data line D1 and the second data line D2 are connected only to the first data line D1. Can be. In addition, as illustrated in FIG. 7, the seventh pixel electrode PE7 and the eighth pixel electrode PE8 between the first data line D1 and the second data line D2 may be connected only to the second data line D2. have.

Furthermore, data pixels and gate signals may be supplied to the subpixels of the pixel array according to the third exemplary embodiment of the present invention. The subpixels of the pixel array according to the third exemplary embodiment of the present invention only differ in the charging order of the pixel electrodes, and the detailed driving method is substantially the same as described with reference to FIG. 3. Therefore, even though the source drive IC 12 supplies data voltages to the data lines in a column inversion manner, the pixel electrodes of the pixel array of the liquid crystal display panel 10 simultaneously perform horizontal two dot inversion and vertical one dot inversion. Driven to satisfy. As a result, according to the third embodiment of the present invention, the number of source drive ICs can be reduced, the power consumption can be significantly reduced, and the DC afterimage can be prevented.

In FIG. 7, the third, fourth, seventh, and eighth pixel electrodes PE3, PE4, PE7, and PE8 may include the fourth pixel electrode PE4, the third pixel electrode PE3, and the seventh pixel electrode ( PE7 and the data voltages are charged in order of the eighth pixel electrode PE8. The fifth, sixth, ninth, and tenth pixel electrodes PE5, PE6, PE9, and PE10 are the sixth pixel electrode PE6, the fifth pixel electrode PE5, the ninth pixel electrode PE9, and the tenth pixel electrode. The data voltages are charged in the pixel electrode PE10 order. As a result, the present invention can solve the blue spot problem that occurred in the conventional "E-inversion" technique as described in FIG.

8 is a flowchart illustrating a manufacturing method of a liquid crystal display according to an exemplary embodiment of the present invention. 9A through 9D are cross-sectional views of II ′ and II-II ′ according to the first to fourth mask processes. Hereinafter, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9A to 9D.

First, the lower substrate SUB includes a gate line, an upper layer GE1U of the gate electrode GE1 of the first TFT T1, and an upper layer GE2U of the gate electrode GE2 of the second TFT T2. The gate metal pattern, the lower layer GE1B of the gate electrode GE1 of the first TFT T1, the lower layer GE2B of the gate electrode GE2 of the second TFT T2, the pixel electrode PE2, and the first A first transparent electrode pattern including the protruding electrode STE1 and the second protruding electrode STE2 is formed using a first mask process. The gate metal pattern may be formed of an opaque metal such as copper (Cu), aluminum (Al), or an aluminum alloy, and the first transparent electrode pattern may be formed of ITO or IZO. The first mask process will be described in detail with reference to FIGS. 10A to 10F. (S101)

Secondly, a gate insulating layer GI covering the gate metal pattern and the first transparent electrode pattern is formed on the entire surface of the lower substrate SUB. Then, on the gate insulating film GI, the semiconductor layer SEM, the data line, the source electrode SE1 and the drain electrode DE1 of the first TFT T1, and the source electrode SE2 of the second TFT T2. A source / drain metal pattern including the drain electrode DE2 and the common voltage line VcomL is formed by a second mask process. Specifically, after the semiconductor layer and the source / drain metal layer are deposited on the gate insulating layer GI, the semiconductor pattern SEM, the data line, the source electrode SE1 of the first TFT T1, A source / drain metal pattern including the drain electrode DE1, the source electrode SE2 and the drain electrode DE2 of the second TFT T2, and the common voltage line VcomL is formed. In order to form the semiconductor pattern SEM and the source / drain metal pattern in one mask process, the second mask process may be implemented as a halftone mask process. The source / drain metal pattern may be formed of an opaque metal such as molybdenum (Mo). (S102)

Third, the passivation film PAS covering the semiconductor pattern SEM and the source / drain metal pattern is formed on the entire surface of the lower substrate SUB. Thereafter, the first protruding electrode penetrates through the passivation layer PAS and exposes the first contact hole CNT1 exposing the drain electrode DE1 of the first TFT T1, the gate insulating layer GI, and the passivation layer PAS. The second contact hole CNT2 exposing the STE1 and the third contact hole CNT3 exposing the common voltage line VcomL through the passivation layer PAS and the passivation layer PAS. The fourth contact hole CNT4 exposing the drain electrode DE2 of the second electrode) and the fifth contact hole CNT5 exposing the second protruding electrode STE2 through the gate insulating layer GI and the passivation layer PAS. It forms in 3 mask processes. That is, the first contact hole CNT1, the third contact hole CNT3, and the fourth contact hole CNT4 are formed to pass through the passivation layer PAS, and the second contact hole CNT2 and the fifth contact hole C are formed. CNT5 is formed to pass through the gate insulating film GI and the passivation film PAS. (S103)

Fourth, the second transparent electrode pattern including the common electrode VcomE, the first contact electrode CE1, and the second contact electrode CE2 is formed on the passivation layer PAS by a fourth mask process. Specifically, the second transparent electrode layer is deposited on the entire surface of the passivation layer PAS, and then the common electrode VcomE, the first contact electrode CE1, and the second contact electrode CE2 are formed by the fourth mask process. A second transparent electrode pattern is formed. The second transparent electrode pattern may be formed of ITO, IZO, or the like. The common electrode VcomE is connected to the common voltage line VcomL through the third contact hole CNT3, and the first contact electrode CE1 is drained of the first TFT T1 through the first contact hole CNT1. It is connected to the electrode DE1 and is formed to be connected to the first protruding electrode STE1 through the second contact hole CNT2. In addition, the second contact electrode CE2 is connected to the drain electrode DE2 of the second TFT T2 through the fourth contact hole CNT4 and the second protruding electrode STE2 through the fifth contact hole CNT5. It is formed to be connected to). (S104)

As described above, the present invention forms the pixel electrode and the protruding electrode on the same plane as the gate metal pattern, so that the pixel electrode and the drain electrode of the TFT can be connected using the protruding electrode extending from the pixel electrode. As a result, the present invention can form a common voltage line between adjacent pixel electrodes in parallel with the data line, thereby preventing the reduction of the aperture ratio due to the common voltage line. In addition, the present invention may form a gate metal pattern including a gate line and a gate electrode, and a transparent electrode pattern including a pixel electrode and a protruding electrode extending therefrom in one mask process. As a result, the present invention can reduce the manufacturing cost.

10 is a flowchart showing a first mask process in detail. 11A through 11F are cross-sectional views of II ′ illustrating the first mask process in detail. Hereinafter, the first mask process will be described in detail with reference to FIGS. 11A through 11F.

First, as illustrated in FIG. 11A, the first transparent electrode layer 201 is deposited on the lower substrate SUB. The first transparent electrode layer 201 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or the like. Then, the gate metal layer 202 is deposited on the first transparent electrode layer 201. The gate metal layer 202 may be formed of an opaque metal such as copper (Cu), aluminum (Al), or an aluminum alloy. (S201)

Secondly, photo resist patterns PR1 and PR2 are formed using a halftone mask as shown in FIG. 11B. Specifically, a photoresist layer is formed on the gate metal layer 202, and exposure and development are performed by using a halftone mask HMASK. The halftone mask HMASK transmits less light than the light blocking layer BL that completely blocks the incident light, the first transparent layer TL1 that transmits the incident light, and the first incident layer TL1. The second transmission layer TL2 is included. When a positive type photoresist pattern PR that is exposed and developed when receiving light is used, a region in which the light blocking layer BL of the halftone mask HMASK is to be formed with a gate metal pattern as shown in FIG. 11B The first transmission layer TL1 is formed in the region where the gate metal pattern and the first transparent electrode pattern are not formed, and the second transmission layer TL2 is formed in the region where the first transparent electrode pattern is to be formed. Can be. When performing exposure and development using the halftone mask HMASK, the first photoresist pattern PR1 is formed in the region where the first transparent electrode pattern is to be formed, and the first photoresist is formed in the region where the gate metal pattern is to be formed. Photoresist pattern PR2 having a thickness thicker than photoresist pattern PR1 is formed. Meanwhile, when a negative type photoresist pattern PR is used, the halftone mask HMASK is formed in a region where the light blocking layer BL is not formed with the gate metal pattern and the first transparent electrode pattern. The first transmission layer TL1 may be formed in the region where the gate metal pattern is to be formed, and the second transmission layer TL2 may be formed in the region where the first transparent electrode pattern is to be formed. (S202)

Third, as shown in FIG. 11C, the first and second photoresist patterns PR1 and PR2 are formed through a first etching process using an etching material capable of simultaneously etching the first transparent electrode layer 201 and the gate metal layer 202. This unformed area is etched. The etching material should be formed of a material capable of etching both the first transparent electrode layer 201 made of ITO or IZO and the gate metal layer 202 made of copper (Cu), aluminum (Al), or aluminum alloy. do. (S203)

Fourth, as shown in FIG. 11D, the first and second photoresist patterns PR1 and PR2 having the thickness of the first photoresist pattern PR1 are removed through a first ashing process. (S204)

Fifth, a region in which the second photoresist pattern PR2 is not formed is etched through the second etching process as shown in FIG. 11E. Thus, the gate metal layer 202 on the first transparent electrode layer 201 may be etched. (S205)

Sixth, as shown in FIG. 11F, the second photoresist pattern PR2 remaining through the second ashing process is removed. As a result, the pixel electrode PE2, the first transparent electrode pattern 211, and the gate metal pattern 212 are completed. (S206)

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: LCD panel 11: timing controller
12: source drive integrated circuit 13: gate driving circuit

Claims (17)

Data lines, gate lines intersecting the data lines, common voltage lines formed parallel to the data lines between the data lines, the data lines, the gate lines, and the common voltage line. A liquid crystal display panel including pixel electrodes formed in a pixel region defined by intersections of the pixels, and thin film transistors formed at intersections of the data lines and the gate lines;
The thin film transistor,
A second pixel electrode is formed at an intersection of the jth (j is at least two natural numbers) data line and the k (k is at least two natural numbers) gate line to be adjacent to the j-1th data line or the j + 1th data line. A first thin film transistor connected to the j-th data line; And
A second thin film transistor formed at an intersection of the j th data line and the k th -th gate line or the k + 1 th gate line to connect a first pixel electrode adjacent to the j th data line with the j th data line Including;
The gate electrode of the first thin film transistor is connected to the k-th gate line, the source electrode is connected to the j-th data line, and the drain electrode is adjacent to the j-1 data line or the j + 1 data line Connected to the first protruding electrode extending from the second pixel electrode through the first contact electrode,
A gate electrode of the second thin film transistor is connected to the k-th gate line or the k-th + 1 gate line, a source electrode is connected to the j-th data line, and a drain electrode is adjacent to the j-th data line. Connected via a second protruding electrode and a second contact electrode of the first pixel electrode,
And the common voltage line is formed between the first pixel electrode and the second pixel electrode.
delete The method of claim 1,
And the first protrusion electrode is longer than the second protrusion electrode.
delete The method of claim 1,
The first protrusion electrode, the second protrusion electrode, and the pixel electrodes are formed of the same transparent metal material on the same plane as the gate line, the gate electrode of the first thin film transistors, and the gate electrode of the second thin film transistor. Liquid crystal display device characterized in that. The method of claim 1,
A portion of the first protrusion electrode overlaps a portion of the drain electrode of the first thin film transistor, and a portion of the second protrusion electrode overlaps a portion of the drain electrode of the second thin film transistor. . The method of claim 1,
The liquid crystal display panel,
A gate insulating layer covering the gate line, the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, the first protrusion electrode, the second protrusion electrode, and the pixel electrodes;
A passivation layer covering the data line, the common voltage line, a source electrode and a drain electrode of the first thin film transistor, a source electrode and a drain electrode of the second thin film transistor, a semiconductor pattern, and a drain electrode formed on the gate insulating layer;
A first contact hole penetrating the passivation layer to expose a drain electrode of the first thin film transistor; And
A second contact hole penetrating the gate insulating film and the passivation film to expose the first protruding electrode;
And the first contact electrode connects the drain electrode of the first thin film transistors and the first protruding electrode through the first contact hole and the second contact hole. The method of claim 7, wherein
The liquid crystal display panel,
A third contact hole penetrating the passivation layer to expose the common voltage line;
A fourth contact hole penetrating the passivation layer to expose a drain electrode of the second thin film transistor;
A fifth contact hole penetrating the gate insulating layer and the passivation layer to expose the second protruding electrode; And
A common electrode formed in the pixel area on the passivation layer;
The common voltage line is connected to the common electrode through the third contact hole,
And the second contact electrode connects the drain electrode of the second thin film transistors and the second protruding electrode through the fourth contact hole and the fifth contact hole. The method of claim 8,
The gate line, the gate electrode of the first thin film transistor, and the gate electrode of the second thin film transistor are formed of a first opaque metal material,
The source electrode and the drain electrode of the first thin film transistor, the source electrode and the drain electrode of the second thin film transistor, the data line, and the common voltage line are formed of a second opaque metal material.
And the first protrusion electrode, the second protrusion electrode, the pixel electrodes, the first contact electrode, the second contact electrode, and the common electrode are formed of the same transparent metal material. The method of claim 1,
Data voltages of a first polarity are applied to the j th data line, and data voltages of a second polarity are applied to the j-1 th data line or the j + 1 th data line.
Only one of the pixel electrodes adjacent to the j th data line in the same horizontal line is connected to the j th data line, and the other is connected to the j th data line or the j th +1 data line,
Pixel electrodes disposed between the j-th data line and the j-th data line or the j-th +1 data line may be connected to only the j-th data line or the j-1th data line or the j-th + 1 data A liquid crystal display device, characterized in that connected only to the line. A gate metal pattern including a gate line, an upper layer of a gate electrode of the first and second thin film transistors, and the pixel electrodes, the first protruding electrode, the second protruding electrode, and the first and second thin film transistors on a lower substrate. Forming a first transparent electrode pattern including a lower layer of the gate electrode;
A gate insulating layer covering the gate metal pattern and the first transparent electrode pattern is formed, and a semiconductor pattern, a data line, a common voltage line, and source and drain electrodes of the first and second thin film transistors are formed on the gate insulating layer. A second step of forming a source / drain metal pattern comprising a;
A first contact hole forming a passivation layer covering the source / drain metal pattern, exposing the drain electrode of the first thin film transistor through the passivation layer, and a second contact penetrating the passivation layer to expose the first protruding electrode A third contact hole exposing the common voltage line through the hole, the passivation layer; a fourth contact hole exposing the drain electrode of the second thin film transistor; and a fifth exposing the second protruding electrode through the passivation layer. Forming a contact hole; And
A first contact electrode connecting the drain electrode of the first thin film transistor and the first protruding electrode through the first contact hole and the second contact hole, and a common voltage line and a common electrode through the third contact hole; A second transparent electrode pattern including a common electrode to be connected and a second contact electrode to connect the drain electrode of the second thin film transistor and the second protruding electrode through the fourth contact hole and the fifth contact hole; A fourth step of doing,
The thin film transistor,
A second pixel electrode is formed at an intersection of the jth (j is at least two natural numbers) data line and the k (k is at least two natural numbers) gate line to be adjacent to the j-1th data line or the j + 1th data line. A first thin film transistor connected to the j-th data line; And
A second thin film transistor formed at an intersection of the j th data line and the k th -th gate line or the k + 1 th gate line to connect a first pixel electrode adjacent to the j th data line with the j th data line Including;
The gate electrode of the first thin film transistor is connected to the k-th gate line, the source electrode is connected to the j-th data line, and the drain electrode is adjacent to the j-1 data line or the j + 1 data line Connected to the first protruding electrode extending from the second pixel electrode through the first contact electrode,
A gate electrode of the second thin film transistor is connected to the k-th gate line or the k-th + 1 gate line, a source electrode is connected to the j-th data line, and a drain electrode is adjacent to the j-th data line. Connected via a second protruding electrode and a second contact electrode of the first pixel electrode,
And wherein the common voltage line is formed between the first pixel electrode and the second pixel electrode.
delete The method of claim 11,
And the first protruding electrode is formed longer than the second protruding electrode.
delete The method of claim 11,
A portion of the first protrusion electrode overlaps a portion of the drain electrode of the first thin film transistor, and a portion of the second protrusion electrode overlaps a portion of the drain electrode of the second thin film transistor. Manufacturing method. The method of claim 11,
The first step,
Depositing a first transparent electrode layer on the lower substrate and depositing a gate metal layer on the first transparent electrode layer;
Forming a photoresist layer on the gate metal layer and forming a first photoresist pattern and a second photoresist pattern thicker than the first photoresist pattern by using a halftone mask;
Etching the first transparent electrode layer and the gate metal layer in a region where the first and second photoresist patterns are not formed;
Removing only the first photoresist pattern;
Etching only the gate metal layer in a region where the second photoresist pattern is not formed;
And removing the second photoresist pattern. The method of claim 16,
Forming a photoresist layer on the gate metal layer, and forming a first photoresist pattern and a second photoresist pattern thicker than the first photoresist pattern using a halftone mask,
And forming the first photoresist pattern in a region where the first transparent electrode pattern is to be formed, and forming the second photoresist pattern in a region where the gate metal pattern is to be formed.

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