KR102542876B1 - Liquid crystal display device - Google Patents

Abstract

The present invention provides a liquid crystal display capable of improving image quality defects that occur when implementing a single color. An embodiment of the present invention includes a lower gate wire and an upper gate wire disposed between sub-pixels adjacent to each other in one direction, and the lower gate wire and the upper gate wire are disposed in a horizontal direction M (M is a positive integer greater than or equal to 2). It is characterized in that each sub-pixel crosses each other.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device driven by a double rate driving (DRD) method.

A liquid crystal display device includes an upper substrate having a color filter, a lower substrate having a switching element and a pixel electrode, and a liquid crystal layer formed between the upper substrate and the lower substrate. It is a device that displays an image by adjusting the arrangement of the light and adjusting the transmittance of light accordingly.

The liquid crystal display device includes a gate line connected to the switching element to apply a gate signal to the switching element, and a data line connected to the switching element to apply a data signal to the switching element. Also, the liquid crystal display device includes a gate driver electrically connected to the gate wire to drive the gate wire, and a data driver electrically connected to the data wire to drive the data wire.

In the case of such a liquid crystal display device, the number of source driver ICs constituting the gate driver and the data driver increases as size and high resolution are required.

However, since the data driver is relatively expensive compared to other devices, research has been conducted on ways to reduce the number of source drive ICs constituting the data driver in order to reduce the production cost of the liquid crystal display, and as a result, a liquid crystal display driven by the DRD method. device has been proposed.

A liquid crystal display driven by the DRD method reduces the number of source drive ICs constituting the data driver by 1/2 the number of data wires instead of doubling the number of gate wires compared to conventional liquid crystal displays. /2 can be reduced. In the case of a liquid crystal display driven by the DRD method, the source driver IC may be driven by a column inversion method for supplying data voltages of different polarities to adjacent data wires.

However, in the case of a conventional DRD liquid crystal display, when displaying a single color, polarity cancellation is not smoothly performed between a plurality of sub-pixels connected to one gate line, resulting in poor quality such as horizontal crosstalk on the screen. this may occur. Horizontal crosstalk may be perceived by a user in the form of a band of horizontal lines.

A technical problem of the present invention is to provide a liquid crystal display capable of improving image quality defects that occur when implementing a single color.

An embodiment of the present invention includes a plurality of pixel electrodes, a lower gate wire and an upper gate wire disposed between the pixel electrodes adjacent to each other in one direction, and a data wire intersecting the lower gate wire and the upper gate wire. . The lower gate wiring and the upper gate wiring cross each other at every M (M is a positive integer greater than or equal to 2) pixel electrodes in the horizontal direction.

In an embodiment of the present invention, a plurality of pixel electrodes arranged in one horizontal line include two gate lines (an upper gate line and a lower gate line) and a number of data lines corresponding to 1/2 of the number of the plurality of pixel electrodes. It can be driven by the DRD method used. Therefore, in the embodiment of the present invention, since the number of data lines corresponding to 1/2 of the number of the plurality of pixel electrodes is required, the number of source drive ICs constituting the data driver can be reduced by 1/2, thereby reducing the production cost. there is.

Also, according to an embodiment of the present invention, lower gate wires and upper gate wires adjacent to each other are arranged to cross each other at every M (M is a positive integer greater than or equal to 2) pixel electrodes in a horizontal direction. Accordingly, the exemplary embodiment of the present invention can smoothly drive polarity cancellation between a plurality of sub-pixels connected to one gate line when displaying a single color. As a result, the embodiment of the present invention has an effect of preventing picture quality defects such as horizontal crosstalk from occurring on the screen.

In addition, in an embodiment of the present invention, the upper gate wire and the lower gate wire are provided on different layers, and the upper gate wire and the gate electrode are connected using a gate contact hole. Therefore, the present invention has an effect of reducing the design area of the gate wiring compared to the prior art in which two gate wirings are provided on the same layer. As a result, the embodiment of the present invention has an effect of widening the aperture ratio of the liquid crystal display as much as the design area of the gate line is reduced.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a perspective view showing a liquid crystal display device according to an exemplary embodiment of the present invention.
FIG. 2 is a plan view illustrating an array substrate, a gate driver, a source drive IC, a flexible film, a circuit board, and a timing controller of FIG. 1 .
3 is an exemplary diagram showing sub-pixels of a pixel array according to an embodiment of the present invention.
4 is an exemplary diagram illustrating data voltages and gate signals supplied to a pixel array according to an exemplary embodiment of the present invention.
FIG. 5 is a plan view showing in detail an area where the lower gate line and the upper gate line of FIG. 3 intersect.
FIG. 6 is a cross-sectional view taken along line II′ of FIG. 5 .
FIG. 7 is a cross-sectional view taken along line II-II' of FIG. 5 .
FIG. 8 is a cross-sectional view taken along line III-III' of FIG. 5 .
FIG. 9 is a cross-sectional view taken along line IV-IV' of FIG. 5 .

The meaning of terms described in this specification should be understood as follows.

Singular expressions should be understood to include plural expressions unless the context clearly defines otherwise, and terms such as “first” and “second” are used to distinguish one component from another, The scope of rights should not be limited by these terms. It should be understood that terms such as "comprise" or "having" do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It means a combination of all items that can be presented from one or more. The term "on" is meant to include not only a case in which a component is formed directly on top of another component, but also a case in which a third component is interposed between these components.

Hereinafter, a preferred example of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

1 is a perspective view showing a liquid crystal display device according to an exemplary embodiment of the present invention. FIG. 2 is a plan view illustrating an array substrate, a gate driver, a source drive IC, a flexible film, a circuit board, and a timing controller of FIG. 1 .

Referring to FIGS. 1 and 2 , a liquid crystal display device 100 according to an exemplary embodiment of the present invention includes a liquid crystal display panel 110, a gate driver 120, and a source drive integrated circuit (hereinafter, referred to as “IC”). ) 130, a flexible film 140, a circuit board 150, and a timing controller 160.

The liquid crystal display panel 110 includes an array substrate 111 and a counter substrate 112 . The counter substrate 112 may be an encapsulation substrate. The array substrate 111 and the counter substrate 112 may be plastic or glass substrates.

Gate wires, data wires, and pixels are formed on one surface of the array substrate 111 facing the counter substrate 112 . The pixels are provided in an area defined by a cross structure of gate lines and data lines. As shown in FIG. 2 , the liquid crystal display panel 110 may be divided into a display area DA in which pixels are formed to display an image and a non-display area NDA in which an image is not displayed. Gate lines, data lines, and pixels may be formed in the display area DA. The gate driver 120 and pads may be formed in the non-display area NDA.

The gate driver 120 supplies gate signals to the gate wires according to the gate control signal input from the timing controller 160 . The gate driver 120 may be formed in the non-display area DA outside one or both sides of the display area DA of the liquid crystal display panel 110 in a gate driver in panel (GIP) method. Alternatively, the gate driver 120 is manufactured as a driving chip and mounted on a flexible film, and the non-display area DA on one side or both sides of the display area DA of the liquid crystal display panel 110 is formed by a tape automated bonding (TAB) method. ) may be attached.

The source drive IC 130 receives digital video data and a source control signal from the timing controller 160 . The source driver IC 130 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source drive IC 130 is manufactured as a driving chip, it may be mounted on the flexible film 140 in a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area NDA of the liquid crystal display panel 110 . Wires connecting pads and the source drive IC 130 and wires connecting pads and wires of the circuit board 150 may be formed on the flexible film 140 . The flexible film 140 is attached to the pads using an anisotropic conducting film, and thereby the pads and the wires of the flexible film 140 can be connected.

The circuit board 150 may be attached to the flexible films 140 . A plurality of circuits implemented as driving chips may be mounted on the circuit board 150 . For example, the timing controller 160 may be mounted on the circuit board 150 . The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

The timing controller 160 receives digital video data and timing signals from an external system board through a cable of the circuit board 150 . The timing controller 60 generates a gate control signal for controlling the operation timing of the gate driver 120 and a source control signal for controlling the source drive ICs 130 based on the timing signal. The timing controller 160 supplies gate control signals to the gate driver 120 and supplies source control signals to the source drive ICs 130 .

3 is an exemplary diagram showing sub-pixels of a pixel array according to an embodiment of the present invention.

Referring to FIG. 3 , the pixel array of the liquid crystal display according to an exemplary embodiment of the present invention includes lower gate lines BGLk-1 to BGLk+1, upper gate lines TGLk-1 to TGLk+1, and data lines DLj -2 to DLj+2), common voltage wires VcomL, and a plurality of pixel electrodes PE.

The lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1 are disposed between pixel electrodes PE adjacent to each other in one direction. The lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1 may be disposed parallel to each other. The lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1 include M (M is a positive integer greater than or equal to 2) pixel electrodes PE in the horizontal direction (Y-axis direction). ) may be provided so as to cross each other. For example, as shown in FIG. 3 , the lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1 may be provided to cross each other at every four pixel electrodes PE. there is.

Specifically, the lower gate wires BGLk-1 to BGLk+1 are the k-1th, kth, and k+1th lower gate wires BGLk-1, which are arranged side by side in a vertical direction (X-axis direction). BGLk, BGLk+1) may be included. The upper gate wires TGLk-1 to TGLk+1 are the k-1th, kth, and k+1th upper gate wires TGLk-1, TGLk, and TGLk disposed side by side in a vertical direction (X-axis direction). +1) can be included. Here, k may be defined as a positive integer that satisfies 2<k<n.

The k−1 th lower gate wire BGLk−1 is disposed adjacent to the k−1 th upper gate wire TGLk−1, and the k th lower gate wire BGLk is disposed adjacent to the k th upper gate wire TGLk. They may be placed adjacent to each other. Also, the k+1 th lower gate line BGLk+1 may be disposed adjacent to the k+1 th upper gate line TGLk+1. In this case, the k−1 th lower gate wire BGLk-1 and the k−1 th upper gate wire TGLk−1 disposed adjacent to each other may cross each other, and the adjacent k th lower gate wire BGLk and the k th upper gate line TGLk may cross each other. Also, the k+1 th lower gate line BGLk+1 and the k+1 th upper gate line TGLk+1 may cross each other.

A region where the k−1 th lower gate wire BGLk−1 and the k−1 th upper gate wire TGLk−1 cross each other and the k+1 th lower gate wire BGLk+1 adjacent to each other according to an embodiment A region where and the k+1 th upper gate line TGLk+1 intersect may overlap the same data line. In this case, a region where the k−1 th lower gate wire BGLk−1 and the k−1 th upper gate wire TGLk−1 cross each other, and the k th lower gate wire BGLk and the k th upper gate are adjacent to each other. An area where the wiring TGLk crosses may overlap with another data wiring. For example, a region where the k−1 th lower gate line BGLk−1 and the k−1 th upper gate line TGLk−1 cross each other includes the j−1 th data line DLj−1 and the j+1 th upper gate line DLj−1. It may overlap with the data line DLj+1. In addition, a region where the k+1 th lower gate line BGLk+1 and the k+1 th upper gate line TGLk+1 cross each other includes the j−1 th data line DLj−1 and the j+1 th data line It can overlap with (DLj+1). In this case, a region where the kth lower gate line BGLk and the kth upper gate line TGLk cross may overlap the jth data line DLj.

Between the k−1 th lower gate wire BGLk−1 and the k−1 th upper gate wire TGLk−1 and the k th lower gate wire BGLk and the k th upper gate wire TGLk, the first through eighth Pixel electrodes PE1 to PE8 may be disposed. Further, between the kth lower gate line BGLk and the kth upper gate line TGLk, the k+1th lower gate line BGLk+1 and the k+1th upper gate line TGLk+1, the ninth to ninth to th upper gate lines TGLk+1 are interposed. 16 pixel electrodes PE9 to PE16 may be disposed. In this case, a region between the k-1th lower gate line BGLk-1 and the k-1th upper gate line TGLk-1, and a region between the k-th lower gate line BGLk and the kth upper gate line TGLk. , and in the region between the k+1th lower gate line BGLk+1 and the k+1th upper gate line TGLk+1, pixel electrodes may not be provided.

The lower gate wires BGLk-1 to BGLk+1 and the upper gate wires TGLk-1 to TGLk+1 according to an embodiment of the present invention may be provided on different layers. That is, the lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1 may be disposed on different layers with at least one insulating layer interposed therebetween. Accordingly, the lower gate wires BGLk-1 to BGLk+1 and the upper gate wires TGLk-1 to TGLk+1 may not contact each other.

Gate signals for driving the thin film transistors T connected to the lower gate wires BGLk-1 to BGLk+1 may be applied to the lower gate wires BGLk-1 to BGLk+1. In addition, gate signals for driving the thin film transistors T connected to the upper gate wires TGLk-1 to TGLk+1 may be applied to the upper gate wires TGLk-1 to TGLk+1.

The data lines DLj-2 to DLj+2 are arranged side by side in a horizontal direction (Y-axis direction) different from a vertical direction (X-axis direction). The data lines DLj-2 to DLj+2 are provided to cross the lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1. The data lines DLj-2 to DLj+2 may include the j-2 to j+2 data lines DLj-2 to DLj+2 as shown in FIG. 3 . For example, the data lines DLj-2 to DLj+2 may be formed as straight lines, but are not necessarily limited thereto. That is, the data lines DLj-2 to DLj+2 may be formed as straight lines bent according to the shape of each of the pixel electrodes PE.

The number of data lines DLj-2 to DLj+2 according to an embodiment of the present invention may correspond to 1/2 of the number of pixel electrodes disposed on any one horizontal line. For example, according to an embodiment of the present invention, a plurality of pixel electrodes PE2 to PE7 arranged on a horizontal line include two gate lines (an upper gate line and a lower gate line) and pixel electrodes PE2 to PE7. It can be driven in the DRD method using the number of data wires (DLj-1, DLj, DLj+2) corresponding to 1/2 of the number of . Therefore, in the embodiment of the present invention, since the number of data lines corresponding to 1/2 of the number of the plurality of pixel electrodes is required, the number of source drive ICs constituting the data driver can be reduced by 1/2, thereby reducing the production cost. There is an effect.

The common voltage lines VcomL may be provided between the data lines DLj-2 to DLj+2. The common voltage lines VcomL may be disposed in parallel with the data lines DLj−2 to DLj+2. The common voltage lines VcomL may be disposed at boundaries between pixel electrodes PE that do not include the data lines DLj−2 to DLj+2. A common voltage for driving the liquid crystal of the liquid crystal layer may be applied to the common voltage wires VcomL.

According to an embodiment of the present invention, by the cross structure of the lower gate wires (BGLk-1 to BGLk+1) and the upper gate wires (TGLk-1 to TGLk+1) and the data wires (DLj-2 to DLj+2) Sub-pixels may be defined. Each of the sub-pixels may include a thin film transistor T and a plurality of pixel electrodes PE electrically connected to the thin film transistor T. The thin film transistors T may be provided in regions where the lower gate lines BGLk-1 to BGLk+1 and the data lines DLj-2 to DLj+2 intersect. In addition, the thin film transistors T may be provided in regions where the upper gate lines TGLk-1 to TGLk+1 and the data lines DLj-2 to DLj+2 intersect.

The plurality of pixel electrodes PE displays images in the liquid crystal display. A plurality of pixel electrodes PE may be provided on one side and the other side of one data line, for example, on the left side and the right side, respectively. For example, a fourth pixel electrode including a thin film transistor T driven by the j-th data line DLj and the k-1-th lower gate line BGLk-1 is located on the left side of the j-th data line DLj. (PE4) may be provided. In addition, a twelfth pixel electrode PE12 including a thin film transistor T driven by the j th data line DLj and the k th lower gate line BGLk is provided on the left side of the j th data line DLj. can In addition, a fifth pixel electrode PE5 including a thin film transistor T driven by the j th data line DLj and the k th lower gate line BGLk is provided on the right side of the j th data line DLj. can In addition, a 14th pixel electrode PE14 including a thin film transistor T driven by the j th data line DLj and the k+1 th lower gate line BGLK+1 is located on the right side of the j th data line DLj. ) can be provided.

Meanwhile, the liquid crystal display device according to the exemplary embodiment of the present invention analyzes digital video data input to the liquid crystal display panel, and the first to fourth pixel electrodes PE1 to 4 disposed in the horizontal direction (Y-axis direction) as shown in FIG. PE4) may be set as one pixel P1. In this case, the first pixel electrode PE1 is a white sub-pixel, the second pixel electrode PE2 is a red sub-pixel, the third pixel electrode PE3 is a green sub-pixel, and the fourth pixel electrode PE4 is a It may be a blue sub-pixel. Hereinafter, for convenience of description, the one pixel P1 disposed in the horizontal direction is defined as a first pixel.

As shown in FIG. 3 , the first pixel P1 may include first to fourth pixel electrodes PE1 to PE4 disposed side by side in a horizontal direction (Y-axis direction). In this case, the first pixel electrode PE1 is connected to the k−1th upper gate line TGLk−1, and the second and third pixel electrodes PE2 and PE3 are connected to the kth upper gate line TGLk. can be connected to. Also, the fourth pixel electrode PE4 may be connected to the k−1 th lower gate line BGLk−1.

The second pixel P2 adjacent to the first pixel P1 in the horizontal direction (Y-axis direction) may include fifth to eighth pixel electrodes PE5 to PE8 disposed side by side in the horizontal direction. In this case, the fifth pixel electrode PE5 and the eighth pixel electrode PE8 are connected to the kth lower gate line BGLk, and the sixth pixel electrode PE6 is connected to the k−1th lower gate line BGLk−1. ) can be accessed. In addition, the seventh pixel electrode PE7 may be connected to the k−1 th upper gate line TGLk−1.

However, the present invention is not limited thereto, and the liquid crystal display device according to the exemplary embodiment of the present invention analyzes digital video data input to the liquid crystal display panel and includes a row of first pixel electrodes PE1 arranged in a rectangular shape as shown in FIG. An image may be displayed by setting the second pixel electrode PE2 and the ninth pixel electrode PE9 and the tenth pixel electrode PE10 in another row as one pixel PX. In this case, the first pixel electrode PE1 is a white sub-pixel, the second pixel electrode PE2 is a red sub-pixel, the ninth pixel electrode PE9 is a green sub-pixel, and the tenth pixel electrode PE10 is a It may be a blue sub-pixel. In this case, the ninth pixel electrode PE9 may be connected to the k+1th upper gate line TGLk+1, and the tenth pixel electrode PE10 may be connected to the kth lower gate line BGLk. .

Hereinafter, for convenience of description, digital video data input to the display panel is analyzed to set sub-pixels arranged in a horizontal direction as one pixel P1 or sub-pixels arranged in a rectangular shape as one pixel PX. The method of setting is referred to as the M+ algorithm.

In the case of a conventional liquid crystal display using the above-described M+ algorithm, when displaying a single color, polarity offset between a plurality of sub-pixels connected to one gate line is not smoothly performed, resulting in horizontal crosstalk on the screen. There is a problem that such a quality defect occurs.

However, in an embodiment of the present invention, lower gate lines BGLk-1 to BGLk+1 and upper gate lines TGLk-1 to TGLk+1 are provided between pixel electrodes PE adjacent to each other in one direction, The lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1 are arranged to cross each other at every M (M is a positive integer greater than or equal to 2) pixel electrodes in the horizontal direction. Accordingly, the exemplary embodiment of the present invention can smoothly drive polarity cancellation between a plurality of sub-pixels connected to one gate line when displaying a single color. As a result, the embodiment of the present invention has an effect of preventing picture quality defects such as horizontal crosstalk from occurring on the screen.

4 is an exemplary diagram illustrating data voltages and gate signals supplied to a pixel array according to an exemplary embodiment of the present invention. 4 shows data voltages output from the source driver IC during the Nth (N is a natural number) frame period and the N+1th frame period, and gate pulses output from the gate driver.

In FIG. 4 , for convenience of description, the first to fifth data voltages DV1 to DV5 supplied to the data lines DLj-2 to DLj+2 of FIG. 3 and the lower gate lines BGLk-1 to BGLk+1 ) supplied to the first, third, and sixth gate pulses GP1, GP3, and GP6, and the second, fourth, and fifth gate pulses GP2 and GP4 supplied to the upper gate lines TGLk-1 to TGLk+1. , GP5) was exemplified. That is, DV1 is the first data voltages supplied to the j-2th data line DLj-2, DV2 is the second data voltages supplied to the j-1th data line DLj-1, and DV3 is the j-th data voltage. The third data voltages DV4 supplied to the data line DLj are the fourth data voltages supplied to the j+1th data line DLj+1, and DV5 are supplied to the j+2th data line DLj+2. This means the supplied fifth data voltages.

In addition, GP1 is a first gate pulse supplied to the k-1 th lower gate line BGLk-1, GP2 is a second gate pulse supplied to the k-1 th upper gate line TGLk-1, and GP3 is a k-th upper gate pulse supplied. A third gate pulse supplied to the lower gate line BGLk, GP4 is a fourth gate pulse supplied to the kth upper gate line TGLk, and GP5 is a third gate pulse supplied to the k+1th upper gate line TGLk+1. 5 gate pulse, GP6 means a sixth gate pulse supplied to the k+1th lower gate line BGLk+1.

Referring to FIG. 4 , the source drive IC ( 130 in FIG. 2 ) supplies data voltages to data lines in a column inversion method. The column inversion method refers to a method of supplying data voltages having opposite polarities to adjacent data lines and maintaining the same polarity of the data voltages supplied to each of the data lines for one frame period. For example, the source drive IC 130 supplies the first data voltages DV1 of the first polarity to the j−2 th data line DLj-2 during the Nth frame period, and supplies the second data voltages DV1 of the second polarity to the j−2th data line DLj−2. The data voltages DV2 are supplied to the j−1th data line DLj−1, the third data voltages DV3 of the first polarity are supplied to the jth data line DLj, and the second polarity of the third data voltages DV3 is supplied. The fourth data voltages DV4 are applied to the j+1th data line DLj+1, and the fifth voltages of the first polarity are supplied to the j+2th data line DLj+2.

In addition, the source drive IC 130 supplies the first data voltages DV1 of the second polarity to the j−2 th data line DLj-2 during the N+1 th frame period, and supplies the second polarity second data voltages DV1 of the first polarity. The data voltages DV2 are supplied to the j−1th data line DLj−1, and the third data voltages DV3 of the second polarity are supplied to the jth data line DLj, and the first polarity of the third data voltages DV3 is supplied. The fourth data voltages DV4 are supplied to the j+1th data line DLj+1, and the fifth data voltages DV5 of the second polarity are supplied to the j+2th data line DLj+2.

In FIG. 4 , the first polarity is described as positive polarity and the second polarity is negative polarity, but it should be noted that it is not limited thereto. That is, the first polarity may be implemented as negative polarity, and the second polarity may be implemented as positive polarity. Here, the data voltage of positive polarity may be defined as a voltage higher than the common voltage based on the common voltage, and the data voltage of negative polarity may be defined as a voltage lower than the common voltage.

The gate driver ( 120 in FIG. 2 ) sequentially outputs gate pulses to the lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1. For example, as shown in FIG. 4 , the gate driver 120 outputs the first gate pulse GP1 to the k−1 th lower gate line BGLk−1 in each of the N th frame period and the N+1 th frame period, and , the second gate pulse GP2 is output to the k−1 th upper gate wire TGLk−1, the third gate pulse GP3 is output to the k th lower gate wire BGLk, and the k th upper gate wire The fourth gate pulse GP4 is output to (TGLk), the fifth gate pulse GP5 is output to the k+1th upper gate wire TGLk+1, and the k+1th lower gate wire BGLk+1 ) to output the sixth gate pulse GP5. Each of the gate pulses is generated with a gate high voltage (VGH) for a predetermined period. As shown in FIG. 4 , the predetermined period may be implemented as one horizontal period (1H). However, the predetermined period is not limited thereto, and may be implemented as one horizontal period (1H) or several horizontal periods. One horizontal period (1H) means one wire scanning time in which digital video data is written to pixels of one horizontal line in the liquid crystal display panel 110 . Hereinafter, a method of supplying data to the pixel electrodes of the pixel array during the N frame period will be described in detail with reference to FIGS. 3 and 4 .

During the first period t1, the fourth and sixth pixel electrodes PE4 and PE6 receive data voltages in response to the first gate pulse GP1. The fourth pixel electrode PE4 connected to the jth data line DLj is charged with the supplied third data voltage DV3 of the first polarity during the first period t1. The sixth pixel electrode PE6 connected to the j+1th data line DLj+1 is charged with the fourth data voltage DV4 of the second polarity supplied during the first period t1.

During the second period t2, the first and seventh pixel electrodes PE1 and PE7 receive data voltages in response to the second gate pulse GP2. The first pixel electrode PE1 connected to the j-1th data line DLj-1 is charged with the second data voltage DV2 of the second polarity supplied during the second period t2. The seventh pixel electrode PE7 connected to the j+2th data line DLj+2 is charged with the fifth data voltage DV5 of the first polarity supplied during the second period t2.

During the third period t3, the tenth, twelfth, fifth, and eighth pixel electrodes PE10, PE12, PE5, and PE8 receive data voltages in response to the third gate pulse GP3. The tenth pixel electrode PE10 connected to the j-1th data line DLj-1 is charged with the second data voltage DV2 of the second polarity supplied during the third period t3. The twelfth pixel electrode PE12 connected to the jth data line DLj is charged with the supplied third data voltage DV3 of the first polarity during the third period t3. The fifth pixel electrode PE5 connected to the jth data line DLj is charged with the supplied third data voltage DV3 of the first polarity during the third period t3. The eighth pixel electrode PE8 connected to the j+1th data line DLj+1 is charged with the fourth data voltage DV4 of the second polarity supplied during the third period t3.

During the fourth period t4, the second, third, thirteenth, and fifteenth pixel electrodes PE2 , PE3 , PE13 , and PE15 receive data voltages in response to the fourth gate pulse GP4 . The second pixel electrode PE2 connected to the j-2th data line DLj-2 is charged with the first data voltage DV1 of the first polarity supplied during the fourth period t4. The third pixel electrode PE3 connected to the j-1th data line DLj-1 is charged with the second data voltage DV2 of the second polarity supplied during the fourth period t4. The thirteenth pixel electrode PE13 connected to the j+1th data line DLj+1 is charged with the fourth data voltage DV4 of the second polarity supplied during the fourth period t4. The fifteenth pixel electrode PE15 connected to the j+2th data line DLj+2 is charged with the fifth data voltage DV5 of the first polarity supplied during the fourth period t4.

During the fifth period t5, the ninth and sixteenth pixel electrodes PE9 and PE16 are supplied with data voltages in response to the fifth gate pulse GP5. The ninth pixel electrode PE9 connected to the j-2th data line DLj-2 is charged with the first data voltage DV1 of the first polarity supplied during the fifth period t5. The sixteenth pixel electrode PE16 connected to the j+1th data line DLj+1 is charged with the fourth data voltage DV4 of the second polarity supplied during the fifth period t5.

During the sixth period t6, the eleventh and fourteenth pixel electrodes PE11 and PE14 receive data voltages in response to the sixth gate pulse GP6. The eleventh pixel electrode PE11 connected to the j−1th data line DLj−1 is charged with the second data voltage DV2 of the second polarity supplied during the sixth period t6. The fourteenth pixel electrode PE14 connected to the jth data line DLj is charged with the third data voltage DV3 of the first polarity supplied during the sixth period t6.

As described above, the source drive IC 130 according to an embodiment of the present invention may supply data voltages to data wires in a column inversion method. Accordingly, the embodiment of the present invention has an effect of reducing the number of source drive ICs and significantly reducing power consumption in a column inversion method.

Also, the first, second, third, and fourth pixel electrodes PE1 , PE2 , PE3 , and PE4 include the fourth pixel electrode PE4 , the first pixel electrode PE, and the second and third pixel electrodes ( Data voltages are charged in order of PE2 and PE3). In this case, the second and third pixel electrodes PE2 and PE3 simultaneously charge data voltages. In addition, the fifth, sixth, seventh, and eighth pixel electrodes PE5 , PE6 , PE7 , and PE8 include the sixth pixel electrode PE6 , the seventh pixel electrode PE7 , the fifth and eighth pixel electrodes ( PE5, PE8) charge the data voltages in order. In this case, the fifth and eighth pixel electrodes PE5 and PE8 simultaneously charge the data voltages.

FIG. 5 is a plan view showing in detail an area where the lower gate line and the upper gate line of FIG. 3 intersect.

Referring to FIG. 5 , an embodiment of the present invention includes lower gate wires (BGLk-1 to BGLk+1), upper gate wires (TGLk-1 to TGLk+1), data wires (DLj-1 to DLj+1), It includes a plurality of common voltage lines VcomL, a plurality of thin film transistors T, a plurality of pixel electrodes PE, and a plurality of common electrodes CE.

The lower gate wires BGLk-1 to BGLk+1 and the upper gate wires TGLk-1 to TGLk+1 extend in a horizontal direction (Y-axis direction). The lower gate lines BGLk-1 to BGLk+1 include a lower line gate electrode GE1 for functioning as a gate of the thin film transistor T for each sub-pixel. The lower wire gate electrode GE1 corresponds to a region having a relatively wide wire width in the lower gate wires BGLk-1 to BGLk+1. The lower wire gate electrode GE1 may be provided in sub-pixels to which gate pulses are applied by the lower gate wires BGLk−1 to BGLk+1.

A gate electrode GE2 is provided on the same layer as the lower gate lines BGLk-1 to BGLk+1. The gate electrode GE2 is provided in sub-pixels in which the lower wiring gate electrode GE1 is not provided. That is, the gate electrode GE2 is provided in sub-pixels to which gate pulses are applied by the upper gate wires TGLk-1 to TGLk+1. The gate electrode GE2 functions as a gate of the thin film transistor T provided in sub-pixels to which gate pulses are applied by the upper gate wires TGLk-1 to TGLk+1. In this case, the gate electrode GE2 may be spaced apart from the lower gate wires BGLk-1 to BGLk+1 by a predetermined distance. For example, the gate electrode GE2 may be provided in an island shape. The gate electrode GE2 may be connected to the upper gate wires TGLk-1 to TGLk+1 through the gate contact hole CNT1. The gate electrode GE2 may be provided at the same time using the same process as the lower gate lines BGLk-1 to BGLk+1. Also, the gate electrode GE2 may be formed of the same material as the lower gate lines BGLk-1 to BGLk+1.

As described above, in the embodiment of the present invention, the upper gate wires (TGLk-1 to TGLk+1) and the lower gate wires (BGLk-1 to BGLk+1) are provided on different layers, and the upper gate wires (TGLk- 1 to TGLk+1) and the gate electrode GE2 are electrically connected through the gate contact hole CNT1. Therefore, the present invention has an effect of reducing the design area of the gate wiring compared to the prior art in which two gate wirings are provided on the same layer. As a result, the embodiment of the present invention has an effect of widening the aperture ratio of the liquid crystal display as much as the design area of the gate line is reduced.

The data lines DLj-1 to DLj+1 extend in the vertical direction (X-axis direction). The data lines DLj-1 to DLj+1 are provided to cross the lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1. A plurality of pixel electrodes are provided on the right and left sides of the data lines DLj-1 to DLj+1. For example, the third and eleventh pixel electrodes PE3 and PE11 are provided on the right side of the j−1th data line DLj−1. In addition, the fourth and twelfth pixel electrodes PE4 and PE12 are provided on the left side of the jth data line DLj, and the fifth and thirteenth pixel electrodes PE5 and PE13 are provided on the right side. In this case, a common voltage line VcomL may be disposed between the third and eleventh pixel electrodes PE3 and PE11 and the fourth and twelfth pixel electrodes PE4 and PE12.

The source electrode SE of the thin film transistor T is connected to each of the data lines DLj-1 to DLj+1. In addition, the drain electrode DE of the thin film transistor T is disposed to face the source electrode SE. The drain electrode DE is electrically connected to the pixel electrode PE3 through the drain contact hole CNT2.

The data lines DLj-1 to DLj+1, the source electrode SE, and the drain electrode DE may be made of the same material and provided on the same layer. In addition, the data lines DLj-1 to DLj+1, the source electrode SE, and the drain electrode DE are provided with the aforementioned lower gate lines BGLk-1 to BGLk+1 and the gate electrode GE. It is formed on the upper layer than the layer.

The plurality of common voltage lines VcomL are provided to cross the lower gate lines BGLk-1 to BGLk+1 and the upper gate lines TGLk-1 to TGLk+1. The plurality of common voltage lines VcomL may be provided between the aforementioned data lines DLj-2 to DLj+2.

The data lines DLj−1 to DLj+1 and the plurality of common voltage lines VcomL may be made of the same material and may be provided on the same layer. The data lines DLj−1 to DLj+1 and the plurality of common voltage lines VcomL may be provided at the same time using the same process. In this case, in order to prevent a short between the wires, the plurality of common voltage wires VcomL are connected to the data wires DLj-1 to DLj+1, the source electrode SE, and the drain electrode DE. may not be contacted. The plurality of common voltage lines VcomL are electrically connected to the plurality of common electrodes CE through the common line contact hole CNT3.

The plurality of thin film transistors T are connected to each of the pixel electrodes PE provided in the sub-pixels. Each of the plurality of thin film transistors T may include a lower wiring gate electrode GE1, a source electrode SE, and a drain electrode DE. Alternatively, each of the plurality of thin film transistors T may include a gate electrode GE2, a source electrode SE, and a drain electrode DE.

The plurality of pixel electrodes PE are connected to the drain electrode DE of the thin film transistor T through the drain contact hole CNT2. In this case, the plurality of pixel electrodes PE may be provided on the same layer as the upper gate lines TGLk-1 to TGLk+1. Also, the plurality of pixel electrodes PE may be provided on the same layer as the plurality of common electrodes CE. A plurality of pixel electrodes according to an example may have a finger structure. For example, the third, fifth, eleventh, and fourteenth pixel electrodes PE3 , PE5 , PE11 , and PE14 may have a finger shape extending upward. Also, the fourth, sixth, twelfth, and thirteenth pixel electrodes PE4 , PE5 , PE12 , and PE13 may have a finger shape extending downward.

Each of the plurality of common electrodes CE is alternately arranged with each of the pixel electrodes PE to form an electric field between them for driving the liquid crystal. The plurality of common electrodes CE are electrically connected to the plurality of common voltage lines VcomL through the common line contact hole CNT3. The common voltage applied through the plurality of common voltage wires VcomL may be transferred to each of the common electrodes CE provided for each sub-pixel.

In an embodiment of the present invention, a plurality of pixel electrodes PE arranged in one horizontal line are two gate lines (an upper gate line and a lower gate line) and 1/2 of the number of the plurality of pixel electrodes PE. It can be driven in a DRD method using the number of data lines corresponding to . Therefore, since the liquid crystal display device according to the embodiment of the present invention requires data lines corresponding to 1/2 the number of the plurality of pixel electrodes, the number of source drive ICs constituting the data driver can be reduced by 1/2. The production cost can be lowered.

FIG. 6 is a cross-sectional view taken along the line II′ of FIG. 5 and is a cross-sectional view of a region including the jth data line DLj of FIG. 5 .

Referring to FIG. 6 , the liquid crystal display according to the exemplary embodiment includes an array substrate 111 , a counter substrate 112 , and a liquid crystal layer 119 . A first insulating layer I1 is formed on the array substrate 111 , and a semiconductor layer ACT is formed on the first insulating layer I1 . A jth data line DLj is formed on the semiconductor layer ACT, and a second insulating film I2, a color filter CF, and a third insulating film I3 are sequentially formed on the jth data line DLj. there is. Common electrodes CE are provided on the third insulating layer I3 in parallel with the jth data line DLj. In addition, on the third insulating layer I3, a fourth pixel electrode PE4 is provided on the left side of the jth data line DLj, and a fifth pixel electrode PE5 is provided on the right side.

In an exemplary embodiment of the present invention, the arrangement direction of the liquid crystal layer 119 is controlled by a horizontal electric field between the common electrode CE and the pixel electrode PE. That is, the present invention can be driven in an IPS (In-plane Switching) mode in which the arrangement direction of the liquid crystal layer 119 is controlled by the horizontal electric field between the common electrode CE and the pixel electrode PE4, but is necessarily limited thereto However, it may be driven in FFS (Fringe Field Switching) mode. Also, the common electrode CE and the pixel electrode PE do not necessarily have to be formed on the same layer, and may be formed on different layers in some cases. For example, an additional insulating layer may be formed on the common electrode CE, and the pixel electrode PE may be formed on the additional insulating layer.

When the present invention is a COT structure, a separate structure may not be formed on the counter substrate 112, but is not necessarily limited thereto. Also, as described above, when the present invention is not a COT structure, a black matrix and the color filter CF may be formed on the counter substrate 112 .

The liquid crystal layer 119 is formed between the array substrate 111 and the counter substrate 112, and the arrangement direction is controlled by an electric field between the common electrode CE and the pixel electrode PE.

FIG. 7 is a cross-sectional view taken along line II-II' of FIG. 5 and is a cross-sectional view of a region including the common voltage line VcomL and the common electrode CE of FIG. 5 .

Referring to FIG. 7 , a liquid crystal display device according to an exemplary embodiment of the present invention includes an array substrate 111 , a counter substrate 112 , and a liquid crystal layer 119 . A first insulating layer I1 is formed on the array substrate 111 , and a common voltage line VcomL is formed on the first insulating layer I1 . A second insulating layer I2, a color filter CF, and a third insulating layer I3 are sequentially formed on the common voltage line VcomL. A common electrode CE is provided on the third insulating layer I3. In this case, a common wiring contact hole CNT3 exposing the common voltage line VcomL is provided in the second insulating film I2, the color filter CF, and the third insulating film I3. The common electrode CE may be electrically connected to the common voltage line VcomL through the common line contact hole CNT3.

FIG. 8 is a cross-sectional view taken along line III-III' of FIG. 5 . This is a cross-sectional view of a region where the k th lower gate line BGLk and the k th upper gate line TGLk intersect in FIG. 5 , and only the configuration of the array substrate 111 is shown for convenience.

Referring to FIG. 8 , a kth lower gate line BGLk is provided on the array substrate 111 of the present invention. A first insulating film I1 is formed on the kth lower gate line BGLk, and a jth data line DLj is formed on the first insulating film I1. A second insulating layer I2, a color filter CF, and a third insulating layer I3 are sequentially formed on the jth data line DLj. A kth upper gate wire TGLk is formed on the third insulating layer I3. In this case, the k th lower gate line BGLk and the k th upper gate line TGLk are insulated from each other by at least one insulating layer. That is, the k-th lower gate line BGLk and the k-th upper gate line TGLk have the first insulating film I1, the second insulating film I2, the color filter CF, and the third insulating film I3 interposed therebetween. They can be placed on different floors.

As described above, in an exemplary embodiment of the present invention, the k th lower gate line BGLk and the k th upper gate line TGLk may be disposed on different layers with at least one insulating layer interposed therebetween. Accordingly, the k th lower gate line BGLk and the k th upper gate line TGLk may cross each other without contacting each other.

FIG. 9 is a cross-sectional view taken along line IV-IV' of FIG. 5 . This is a cross-sectional view of a region where the kth upper gate line TGLk and the gate electrode GE2 are connected in FIG. 5 , and only the configuration of the array substrate 111 is shown for convenience.

Referring to FIG. 9 , a gate electrode GE2 is provided on the array substrate 111 of the present invention. A first insulating layer I1, a second insulating layer I2, a color filter CF, and a third insulating layer I3 are sequentially formed on the gate electrode GE2. A kth upper gate wire TGLk is formed on the third insulating layer I3. In this case, a gate contact hole CNT1 exposing the gate electrode GE2 is provided in the first insulating layer I1, the second insulating layer I2, the color filter CF, and the third insulating layer I3. The kth upper gate line TGLk may be electrically connected to the gate electrode GE2 through the gate contact hole CNT1. In this case, the gate electrode GE2 functions as a gate of the thin film transistor T provided in sub-pixels to which gate pulses are applied by the upper gate lines TGLk-1 to TGLk+1.

Since the upper gate wires TGLk-1 to TGLk+1 are electrically connected to the gate electrode GE2, the embodiment of the present invention uses gate signals applied to the upper gate wires TGLk-1 to TGLk+1. Thus, the thin film transistors T connected to the upper gate wires TGLk-1 to TGLk+1 may be driven.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present invention. It will be clear to those who have knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

100: liquid crystal display device 110: liquid crystal display panel
111: array substrate 112: counter substrate
120: gate driver 130: source drive IC
140: flexible film 150: circuit board
160: timing control unit BGLk-1 to BGLk+1: lower gate wiring
DLj-2 to DLj+2: data line TGLk-1 to TGLk+1: top gate wiring
VcomL: common voltage lines T: thin film transistor
PE: pixel electrodes CE: common electrodes
GE1: lower wiring gate electrode GE2: gate electrode
SE: source electrode DE: drain electrode

Claims (10)

a plurality of pixel electrodes;
a lower gate wire and an upper gate wire disposed between pixel electrodes adjacent to each other in one direction; and
a data line intersecting the lower gate line and the upper gate line;
The lower gate wire and the upper gate wire cross each other at every M (M is a positive integer greater than or equal to 2) pixel electrodes in a horizontal direction. According to claim 1,
The liquid crystal display device according to claim 1 , wherein the lower gate wiring and the upper gate wiring are provided on different layers. According to claim 1,
The area where the k−1th (k is a positive integer satisfying 2<k<n) lower gate wiring and the k−1th upper gate wiring cross each other, and the kth lower gate wiring and the kth upper gate wiring are adjacent to each other The liquid crystal display device characterized in that the intersecting area overlaps with different data lines. According to claim 3,
The area where the k-1th (k is a positive integer satisfying 2<k<n) lower gate wiring and the k-1th upper gate wiring that are adjacent to each other intersect, and the k+1th lower gate wiring and the k+th lower gate wiring that are adjacent to each other cross each other. 1 A liquid crystal display device characterized in that a region where the upper gate wiring crosses overlaps the same data wiring. According to claim 3,
The first pixel includes first to fourth pixel electrodes disposed side by side in a horizontal direction, the first pixel electrode is connected to the k-1th upper gate line, and the second pixel electrode and the third pixel electrode are connected to the k-th upper gate wire, and wherein the fourth pixel electrode is connected to the k−1-th lower gate wire. According to claim 5,
A second pixel horizontally adjacent to the first pixel includes fifth to eighth pixel electrodes disposed side by side in a horizontal direction, and the fifth pixel electrode and the eighth pixel electrode are connected to the kth lower gate wire. wherein the sixth pixel electrode is connected to the k−1 th lower gate wire, and the seventh pixel electrode is connected to the k−1 th upper gate wire. According to claim 2,
a gate electrode provided on the same layer as the lower gate line; and
Further comprising at least one insulating film provided on the gate electrode,
The upper gate wire is connected to the gate electrode through a gate contact hole penetrating the at least one insulating layer. According to claim 7,
The lower gate wire and the upper gate wire are insulated from each other with the at least one insulating film interposed therebetween. According to claim 1,
The liquid crystal display device according to claim 1 , wherein the upper gate wiring and the plurality of pixel electrodes are provided on the same layer. According to claim 1,
The liquid crystal display device, characterized in that the number of data lines corresponds to 1/2 of the number of pixel electrodes disposed on any one horizontal line.

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