KR102202870B1 - Display device using drd type - Google Patents

Abstract

The present invention relates to a display device, and in particular, provides a display device using a DRD method in which two pixels surrounded by two gate lines and two data lines can have parasitic capacitors of the same size. Making it a technical task. To this end, in the display device using the DRD method according to the present invention, two pixel electrodes formed in a pixel area surrounded by an m-th gate line, an m+1-th gate line, an n-th data line, and an n+1-th data line Each is electrically connected to the n-th data line, and is adjacent to both the n-th data line and the n+1-th data line.

Description

Display device using the RD method {DISPLAY DEVICE USING DRD TYPE}

The present invention relates to a display device, and more particularly, to a display device using a double rate driving (DRD) method.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. Flat panel displays include a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display device (OLED), and more recently, an electrophoretic display device. (EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among flat panel displays (hereinafter simply referred to as'display devices'), a liquid crystal display (LCD) is a device that displays an image using the optical anisotropy of liquid crystal, and has advantages such as thin, small size, low power consumption and high quality. Because of this, it is widely used.

Among display devices, an organic light emitting display device uses a self-luminous device that emits light by itself, and thus has advantages such as fast response speed, high luminous efficiency, high brightness and large viewing angle. Therefore, it is attracting attention as a next-generation flat panel display device.

Recently, in order to reduce the number of data drivers or the number of data lines DL of a display device, a double rate driving (hereinafter simply referred to as'DRD') method has been used.

In a display device using the DRD method, the number of horizontal gate lines is reduced by 1/2, instead of doubling the number of horizontal gate lines compared to the conventional one. That is, the DRD method is a method capable of implementing the same resolution while reducing the number of required data drives or the number of data lines in half.

Display devices using the DRD method are published in Publication Nos. 10-2013-0067923 and 10-2013-0108872 filed by the present applicant.

A display device using a conventional DRD method uses a two-dot inversion method. However, in a display device using the 2-dot inversion method, a large amount of power consumption is required, and a vertical line DIM may occur.

In order to overcome this, various types of Z-inversion methods using the DRD method have been developed.

However, in the conventional display device using the Z-inversion method, the positions of the switching transistors formed in each pixel and the connection type between the electrodes constituting the switching transistor and the data line may be formed differently for each pixel. I can.

In this case, for each pixel, an affected capacitance, for example, a capacitance Cdp between a data line and a pixel electrode is different. Accordingly, a phenomenon in which the charging amount is different for each pixel occurs, and accordingly, the image quality of the display device may be deteriorated.

The present invention has been proposed to solve the above-described problem, and two pixels surrounded by two gate lines and two data lines can have parasitic capacitors of the same size, and display using the DRD method. It is a technical challenge to provide a device.

In a display device using the DRD method according to the present invention for achieving the above-described technical problem, d×g pixels arranged in a matrix form by an intersection structure of d/2 data lines and 2g gate lines are double A panel formed in a rate driving (DRD) method and in which a pixel electrode is formed on each of the pixels; A gate driver sequentially supplying scan pulses to the gate lines; A data driver supplying data voltages to the data lines; And a timing controller for controlling driving timings of the gate driver and the data driver, and formed in a pixel area surrounded by an m-th gate line, an m+1-th gate line, an n-th data line, and an n+1-th data line. Each of the two pixel electrodes is electrically connected to the n-th data line, and is adjacent to both the n-th data line and the n+1-th data line.

According to the present invention, even if the horizontal 2-dot Z-inversion method using the DRD method is applied, the same size of capacitance Ddp can be applied to all pixels. Accordingly, the problem of image quality deterioration can be improved.

Further, according to the present invention, the load of the data line can be reduced, and thus, sufficient charging time can be secured.

1 is a configuration diagram of an embodiment of a display device using a DRD method according to the present invention.
2 is a plan view showing a part of a panel of a display device using a DRD method according to the present invention.
3 is an exemplary view illustrating a method of driving a display device using a DRD method according to the present invention.
4 is an exemplary view showing waveforms of various signals applied to a display device using a DRD method according to the present invention.
5 is an exemplary view schematically showing the configuration of a panel of a display device using a DRD method according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an embodiment of a display device using a DRD method according to the present invention.

In the display device using the DRD method according to the present invention, as shown in FIG. 1, by a cross structure of d/2 data lines DL1 to DLd/2 and 2g gate lines GL1 to GL2g. The d×g pixels arranged in a matrix form are formed in a double-rate driving (DRD) method, and each of the pixels includes a panel 100 on which a pixel electrode is formed, and scan pulses are sequentially applied to the gate lines. And a gate driver 200 for supplying data, a data driver 300 for supplying data voltages to the data lines, and a timing controller 400 for controlling driving timings of the gate driver and the data driver.

In particular, in the display device using the DRD method according to the present invention, two pixel electrodes formed in a pixel area surrounded by an m-th gate line, an m+1-th gate line, an n-th data line, and an n+1-th data line Each of them is electrically connected to the nth data line, and is adjacent to both the nth data line and the n+1th data line.

First, the panel 100 basically uses a double rate driving (hereinafter simply referred to as “DRD”) method.

The DRD method is one of methods for reducing the number of data drivers 300 or the number of data lines DL of a display device. In a panel using the DRD method, as compared to the prior art, the number of data lines DL is reduced by half instead of doubling the number of gate lines GL. That is, the DRD method is a method capable of implementing the same resolution while reducing the number of data drives 300 required or the number of data lines DL in half.

That is, in the display device using the DRD method according to the present invention, d pixels arranged on one horizontal line of the panel 100 are provided with two gate lines GL formed above and below the horizontal line and d/ It may be driven using two data lines DL.

The panel 100 may be various types of panels such as a liquid crystal panel, an organic light emitting panel, or an electrophoretic display panel.

The panel 100 is formed by bonding a first substrate and a second substrate. An intermediate layer is formed between the first substrate and the second substrate.

The first substrate and the second substrate may be made of glass, plastic, metal, or the like.

The intermediate layer may have different configurations according to the type of the display device using the DRD method according to the present invention. For example, when the display device using the DRD method according to the present invention is a liquid crystal display device (LCD), the intermediate layer may include a liquid crystal. When the display device using the DRD method according to the present invention is an organic light emitting display device (OLED), the intermediate layer may include an organic compound that outputs light. When the display device using the DRD method according to the present invention is an electrophoretic display device (EPD), the intermediate layer may include an electrophoretic dispersion or the like.

A detailed structure of the panel 100 and the pixel using the DRD method will be described in detail below with reference to FIGS. 2 to 3. In particular, hereinafter, the present invention will be described by taking the case where the panel 100 is a liquid crystal panel as an example.

Next, the timing controller 400 uses a vertical/horizontal synchronization signal and a clock signal supplied from an external system (not shown) to control the gate driver 200 by using a gate control signal GCS and the data driver ( 300) outputs a data control signal (DCS).

In addition, the timing controller 400 samples the input image data input from the external system and rearranges it, and supplies the rearranged digital image data RGB to the data driver 300.

That is, the timing controller 400 rearranges the input image data supplied from the external system and transmits the rearranged digital image data to the data driver 300. The timing controller 400 uses a clock signal supplied from the external system, a horizontal synchronization signal, a vertical synchronization signal (the signals are simply referred to as timing signals), and a data enable signal, and the gate driver 200 A gate control signal GCS for controlling) and a data control signal DCS for controlling the data driver 300 are generated and transmitted to the gate driver 200 and the data driver 300.

In particular, in order to achieve the above object, the timing controller 400 includes a receiving unit receiving the input image data and various signals as described above from the external system, and the input of the signals received from the receiving unit. An image data processing unit for rearranging image data to fit the panel to generate the rearranged digital image data, and for controlling the gate driver 200 and the data driver 300 using signals received from the receiving unit. A control signal generation unit for generating the gate control signal GCS and the data control signal DCS, and the image data and the control signals generated by the image data processing unit are converted into the data driving unit 300 or the gate driving unit ( 200) may be configured to include a transmitter for output.

Next, the data driver 300 converts the image data input from the timing controller 400 into an analog data voltage, and a data voltage corresponding to one horizontal line for every horizontal period in which the gate pulse is supplied to the gate line. Is supplied to the data lines. That is, the data driver 300 converts the image data into a data voltage using gamma voltages supplied from a gamma voltage generator (not shown) and outputs the converted image data to the data lines.

That is, the data driver 300 shifts a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC) to generate a sampling signal. Further, the data driver 300 latches the pixel data RGB (image data) input according to the source shift clock SSC according to a sampling signal, changes to a data voltage, and enables the source output. The data voltage is supplied to the data lines in units of horizontal lines in response to a (Source Output Enable; SOE) signal.

To this end, the data driver 300 may include a shift register unit, a latch unit, a digital to analog conversion unit, and an output buffer.

In particular, when the panel 100 is a liquid crystal panel, the data driver 300 may supply data voltages of different polarities to the adjacent data lines during one frame period. For example, the data driver 300 supplies a data voltage of + polarity to the nth data line, supplies a data voltage of -polarity to the n+1th data line, and + Polarity data voltage can be supplied.

Also, the data driver 300 may invert polarities of the data voltages at least every one frame period. For example, during a first frame period, a data voltage of + polarity is supplied to an nth data line, a data voltage of -polarity is supplied to an n+1th data line, and a data voltage of + polarity is supplied to the n+2th data line. A data voltage can be supplied, and during the second frame period, a data voltage of -polarity is supplied to the nth data line, a data voltage of +polarity is supplied to the n+1th data line, and -Polar data voltage can be supplied.

The polarity change of the data voltage as described above may be performed by a polarity control signal transmitted from the timing controller 400. To this end, the timing controller 400 may generate the polarity control signal for converting the polarities of data voltages for each preset frame and transmit the generated polarity control signal to the data driver 300, and the data driver 300 By using the polarity control signal, the polarity of the data voltage to be transmitted to each data line can be reversed.

Finally, the gate driver 200 sequentially supplies scan pulses to the gate lines GL1 to GL2g of the panel 100 in response to the gate control signal input from the timing controller 400. Accordingly, switching transistors formed in each pixel of a corresponding horizontal line to which the scan pulse is input are turned on, so that an image can be output to each pixel.

That is, the gate driver 200 shifts the gate start pulse (GSP) transmitted from the timing controller 400 according to a gate shift clock (GSC), and sequentially shifts the gate lines. A scan pulse having a gate-on voltage Von is supplied to (GL1 to GLg). In addition, the gate driver 200 supplies the gate-off voltage Voff to the gate lines GL1 to GL2g during the remaining period when the scan pulse of the gate-on voltage Von is not supplied.

The gate driver 200 may be formed independently of the panel 100 and may be configured in a form capable of being electrically connected to the panel 100 in various ways, but a gate mounted in the panel 100 It can also be configured in a Gate In Panel (GIP) method. In this case, the gate control signals for controlling the gate driver 200 may include a start signal VST and a gate clock GCLK.

Further, in the above description, although the data driver 300, the gate driver 200, and the timing controller 400 have been described as being independently configured, at least one of the data driver 300 or the gate driver 200 Either one may be integrally configured with the timing controller 400.

2 is a plan view showing a part of a panel of a display device using a DRD method according to the present invention. Hereinafter, among the pixels shown in FIG. 2, in particular, two pixels formed in a first pixel area surrounded by an m-th gate line, an m+1-th gate line, an n-th data line, and an n+1-th data line The present invention is described using electrodes as an example.

As described above, in the display device using the DRD method, pixels disposed on one horizontal line of the panel 100 are formed with two gate lines and d/2 data lines formed above and below the horizontal line. It can be driven using (DL)s.

For example, as shown in FIG. 2, an m-th gate line GLm, an m+1-th gate line GLm+1, an n-th data line DLn, and an n+1-th data line DLn+1 The two pixel electrodes P1 and P2 formed in the first pixel area PA1 surrounded by) are the m-th gate line GLm, the m+1-th gate line GLm+1, and the n-th It is driven by the data line DLn.

First, when the scan pulse is input to the m-th gate line GLm, the first switching transistor TR1 connected to the first pixel electrode P1 of the two pixel electrodes P1 and P2 is turned on. Accordingly, the data voltage supplied to the n-th data line DLn is supplied to the first pixel electrode P1 through the first switching transistor TR1. Accordingly, an image may be output from the first pixel electrode P1.

Next, when the scan pulse is input to the m+1th gate line GLm+1, a second switching transistor connected to the second pixel electrode P2 of the two pixel electrodes P1 and P2 TR2 is turned on, and accordingly, the data voltage supplied to the n-th data line DLn is supplied to the second pixel electrode P2 through the second switching transistor TR2. Accordingly, an image may be output from the second pixel electrode P2.

To this end, each of the two pixel electrodes P1 and P2 is electrically connected to the n-th data line DLn.

In particular, each of the two pixel electrodes P1 and P2 is adjacent to both the nth data line DLn and the n+1th data line DLn+1.

For example, the first pixel electrode P1 is formed in the shape of a'', and the left side is adjacent to the n-th data line DLn, and the right side protruding from the left side in a right direction. Is adjacent to the n+1th data line DLn+1.

In addition, the second pixel electrode P2 is formed in the shape of a'"', so that the right side is adjacent to the n+1th data line DLn+1, and the left side protruding from the right side in a left direction. A surface is adjacent to the n-th data line DLn.

That is, the two pixel electrodes are formed on one horizontal line and are commonly connected to one data line.

Of the two pixel electrodes, the first pixel electrode P1 is electrically connected to the m-th gate line GLm, and a second pixel electrode P2 of the two pixel electrodes is the m+ It is electrically connected to the 1 gate line (GLm+1).

That is, the two pixel electrodes are formed on one horizontal line, and the first pixel electrode P1 of the two pixel electrodes is formed with the m-th gate line GLm formed on the upper end of the horizontal line. The second pixel electrode P2 is connected to the m+1th gate line GLm+1 formed below the horizontal line.

In particular, among the two pixel electrodes, the first pixel electrode P1 is electrically connected to the n-th data line DLn and the m-th gate line GLm in the upper left portion of the first pixel area PA1. The second pixel electrode P2 of the two pixel electrodes is connected to the n-th data line DLn and the m+1-th gate line at the lower left of the first pixel area PA1. It is electrically connected to GLm+1).

To further explain, the first switching transistor TR1 for driving the first pixel P1 is formed in the upper left portion of the first pixel area PA1, as shown in FIG. It is electrically connected to the n data line DLn and the m-th gate line GLm. In addition, a second switching transistor TR2 for driving the second pixel P2 is formed in the lower left portion of the first pixel area PA1, as shown in FIG. 2, and the n-th data line It is electrically connected to (DLn) and the m+1th gate line GLm+1.

In this case, the two pixels P1 and P2 are spaced apart from each other along a line formed from a direction of the nth data line DLn to a direction of the n+1th data line DLn+1.

' 형태로 형성된 라인을 따라 서로 이격되어 있다. For example, the two pixels P1 and P2 shown in FIG. 2 are '

They are spaced apart from each other along a line formed in a shape.

In the line, the two pixels P1 and P2 may be spaced apart from each other along the line formed from a direction of the n-th data line DLn to a direction of the n+1 data line DLn+1. So, it can be formed in various shapes. For example, the line may be formed in a'/' shape or a'\' shape.

In this case, the line has a parasitic capacitance between the first pixel electrode P1, the n-th data line DLn, and the n+1 data line DLn+1 among the two pixel electrodes, Among the two pixel electrodes, the second pixel electrode P2, the n-th data line DLn, and the n+1-th data line DLn+1 may be formed to have the same or similar parasitic capacitance. .

' 형태로 형성된 라인을 따라 서로 이격되어 있기 때문에, 상기 두 개의 픽셀들(P1, P2)의 모양은 실질적으로는 동일하다. For example, as shown in FIG. 2, the two pixels P1 and P2 are '

Since the two pixels P1 and P2 are spaced apart from each other along a line formed in the'shape', the shapes of the two pixels P1 and P2 are substantially the same.

Accordingly, the parasitic capacitance CdpL1 between the first pixel P1 and the n-th data line DLn is a parasitic capacitance between the second pixel P2 and the n+1th data line DLn+1 ( Same as CdpR2). In addition, the parasitic capacitance CdpR1 between the first pixel P1 and the n+1th data line DLn+1 is a parasitic capacitance between the second pixel P2 and the nth data line DLn. CdpL).

In addition, all pixels formed in the panel 100 have the same parasitic capacitance according to the above-described type.

According to the present invention as described above, since all pixels have the same parasitic capacitance, the amount of charge charged in each pixel can be uniform, and thus, deterioration of image quality can be prevented.

To further explain, the present invention is a display device using a horizontal two-dot Z-inversion method of a DRD method, and as compared to a conventional horizontal two-dot Z-inversion method, image quality can be improved.

In addition, in the present invention, since a separate additional line is not required in order to keep the parasitic capacitance of each pixel the same, the aperture ratio can be improved.

3 is an exemplary diagram for explaining a method of driving a display device using a DRD method according to the present invention. FIG. 3 shows a panel to which additional pixels are connected below the pixels shown in FIG. 2. 4 is an exemplary diagram showing waveforms of various signals applied to a display device using a DRD method according to the present invention.

First, when the scan pulse is input to the m-th gate line GLm during a first frame period, a first pixel among the two pixel electrodes P1 and P2 formed on the k-th horizontal line HLk The first switching transistor TR1 connected to the electrode P1 is turned on.

Next, when the first switching transistor TR1 is turned on, the data voltage of + polarity supplied to the n-th data line DLn is applied to the first pixel electrode P1 through the first switching transistor TR1. Is supplied as Accordingly, an image may be output from the first pixel electrode P1.

Next, when the scan pulse is input to the m+1th gate line GLm+1, the second pixel among the two pixel electrodes P1 and P2 formed on the kth horizontal line HLk The second switching transistor TR2 connected to the electrode P2 is turned on.

Next, when the second switching transistor TR2 is turned on, the data voltage of + polarity supplied to the n-th data line DLn is transferred to the second pixel electrode P2 through the second switching transistor TR2. Is supplied as Accordingly, an image may be output from the second pixel electrode P2.

Next, when the scan pulse is input to the m+2th gate line GLm+1, the second of the two pixel electrodes P3 and P4 formed on the k+1th horizontal line HLk+1 The third switching transistor connected to the 3-pixel electrode P3 is turned on.

Next, when the third switching transistor is turned on, a data voltage of + polarity supplied to the nth data line DLn is supplied to the third pixel electrode P3 through the third switching transistor. Accordingly, an image may be output from the third pixel electrode P3.

Next, when the scan pulse is input to the m+3th gate line GLm+3, one of the two pixel electrodes P3 and P4 formed on the k+1th horizontal line HLk+1 The fourth switching transistor connected to the fourth pixel electrode P4 is turned on.

Next, when the fourth switching transistor is turned on, the positive data voltage supplied to the n-th data line DLn is supplied to the fourth pixel electrode P4 through the fourth switching transistor. Accordingly, an image may be output from the fourth pixel electrode P4.

Finally, the method described above is also commonly applied to pixels formed on the k+2th horizontal line HLk+2 and the k+3th horizontal line HLk+3.

Accordingly, the fifth pixel P5, the sixth pixel P6, the seventh pixel P7, and the eighth pixel P8 shown in FIG. 3 are sequentially driven to output an image.

By the above-described method, a shape in which an image is output to the pixels has a shape similar to a Z shape, as shown in FIG. 3. Accordingly, the display device using the DRD method according to the present invention has a Z-inversion structure.

In addition, as shown in FIG. 3, in the display device using the DRD method according to the present invention, two adjacent pixels P1, P2 or P3, P4 or P5, P6 or P7, in one horizontal line, P8) is driven by data voltages having the same polarity. Therefore, it can be seen that the present invention is driven in a horizontal 2-dot method.

Accordingly, the present invention uses a horizontal 2-dot Z-inversion method of the DRD method.

In this case, the data driver supplies data voltages of different polarities to the adjacent data lines during one frame period, as shown in FIGS. 3 and 4, and at least every one frame period, the data You can reverse the polarity of the voltages.

For example, as shown in FIG. 3, during the first frame period, a data voltage of -polarity is supplied to the n-1th data line DLn-1, and + is supplied to the nth data line DLn. A polarity data voltage is supplied, and a negative polarity data voltage is supplied to the n+1th data line DLn+1. 4 shows a data voltage (Data), a scan pulse (Gate), and a common voltage (Vcom) supplied to the n-th data line DLn. During a first frame period (1 Frame), the n-th data line ( It can be seen that the data voltage of + polarity is supplied to DLn).

However, during the second frame period (2Frame), a data voltage of -polarity is supplied to the n-th data line DLn, as shown in FIG. 4.

In this case, a data voltage of + polarity is supplied to the n-1th data line DLn-1 and the n+1th data line DLn+1.

To this end, the timing controller may change a polarity control signal for controlling the polarity of the data voltage to change, at least every one frame period.

The data driver may change the polarity of the data voltage output to each data line, as described above, at least every one frame period according to a control signal included in the polarity control signal.

Accordingly, vertical line DIM may be reduced, and image quality may be improved.

5 is an exemplary diagram schematically showing the configuration of a panel of a display device using a DRD method according to the present invention. Referring to FIG. 5, the DRD scheme according to the present invention is briefly summarized as follows.

As described above and shown in FIG. 5, in the display device using the DRD method according to the present invention, pixels disposed on one horizontal line of the panel 100 are two gate lines formed above and below the horizontal line. And d/2 data lines DL.

In this case, the first pixel region surrounded by the m-th gate line GLm, the m+1-th gate line GLm+1, the n-th data line DLn, and the n+1-th data line DLn+1 ( The two pixel electrodes P1 and P2 formed on PA1) are driven by the m-th gate line GLm, the m+1-th gate line GLm+1, and the n-th data line DLn. .

To this end, each of the two pixel electrodes P1 and P2 is electrically connected to the n-th data line DLn.

In particular, each of the two pixel electrodes P1 and P2 is adjacent to both the nth data line DLn and the n+1th data line DLn+1.

In addition, a first switching transistor TR1 for driving the first pixel P1 is formed at an upper left portion of the first pixel area PA1, the n-th data line DLn and the m-th gate It is electrically connected to the line GLm. In addition, a second switching transistor TR2 for driving the second pixel P2 is formed in a lower left portion of the first pixel area PA1, and is formed at the nth data line DLn and the m+th It is electrically connected to the 1-gate line (GLm+1).

The two pixels surrounded by the two data lines and the two gate lines are formed in the same shape as the first pixel P1 and the second pixel P2 described above.

In this case, the two pixels P1 and P2 are spaced apart from each other along a line formed from a direction of the nth data line DLn to a direction of the n+1th data line DLn+1.

For example, the two pixels P1 and P2 shown in FIG. 5 are spaced apart from each other along a line crossing the two pixels.

' 형태로 형성될 수도 있고, '／' 형태 또는 '＼' 형태로 형성될 수도 있으며, 기타, 두 개의 상기 픽셀들이 동일한 형태를 갖도록 다양한 형태로 형성될 수 있다. The above line is'

It may be formed in the form of'/', or'\', and in addition, the two pixels may be formed in various shapes so that they have the same shape.

The line has a parasitic capacitance between the first pixel electrode P1, the n-th data line DLn, and the n+1 data line DLn+1 among the two pixel electrodes, and the two pixels Among the electrodes, the second pixel electrode P2 and the n-th data line DLn and the n+1-th data line DLn+1 may be formed to have the same or similar parasitic capacitance.

In the display device including the panel 100 having the above configuration, as shown in FIG. 5, each pixel may be sequentially driven in a Z shape during one frame period.

In addition, in a display device including the panel 100 having the above configuration, the data driver 300 supplies data voltages of different polarities to the adjacent data lines during one frame period. In addition, polarities of the data voltages may be inverted at least every one frame period.

Those skilled in the art to which the present invention pertains will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: panel 200: gate driver
300: data driver 400: timing controller

Claims (6)

A panel in which pixels are provided in crossing regions of data lines and gate lines, and pixel electrodes are formed in each of the pixels;
A gate driver sequentially supplying scan pulses to the gate lines;
A data driver supplying data voltages to the data lines; And
A timing controller for controlling driving timings of the gate driver and the data driver,
Each of the two pixel electrodes formed in the pixel area surrounded by the m-th gate line, the m+1-th gate line, the n-th data line, and the n+1-th data line is electrically connected to the n-th data line, and , Are adjacent to both the nth data line and the n+1th data line (m and n are natural numbers),
The two pixels are '

A display device using a double rate driving (DRD) (hereinafter referred to as DRD) method, characterized in that they are spaced apart from each other along a line formed in a'shape or'/' shape or a'\' shape. The method of claim 1,
A first pixel electrode of the two pixel electrodes is electrically connected to the mth gate line, and a second pixel electrode of the two pixel electrodes is electrically connected to the m+1th gate line. Display device using method. The method of claim 1,
A first pixel electrode of the two pixel electrodes is electrically connected to the n-th data line and the m-th gate line at an upper left portion of the pixel area,
A display device using a DRD method in which a second pixel electrode among the two pixel electrodes is electrically connected to the n-th data line and the m+1-th gate line at a lower left portion of the pixel area. The method of claim 1,
The data driver supplies data voltages of different polarities to adjacent data lines during one frame period, and reverses polarities of the data voltages in at least one frame period. The method of claim 1,
The parasitic capacitance between the first pixel electrode, the n-th data line, and the n+1-th data line among the two pixel electrodes, is a second pixel electrode, the n-th data line, and the A display device using a DRD method, characterized in that the parasitic capacitance between n+1 data lines is the same. The display device of claim 1, wherein the two pixels are spaced apart from each other in a direction of the n-th data line and a direction of the n+1-th data line.

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