KR102008778B1 - Liquid crystal display device and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to provide a liquid crystal display device and a driving method thereof capable of inputting a clock to both ends of a panel-embedded gate driver (GIP). To this end, a liquid crystal display according to the present invention includes a panel in which pixels are formed at intersections of data lines and gate lines; A data driver for supplying a data voltage to the data lines; A timing controller driving the data driver; And a first panel embedded gate driver which is embedded in the first non-display area of the panel and driven by the same clocks input from the timing controller to sequentially supply scan signals to the gate lines.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a large area and a high resolution and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and more recently, an electrophoretic display. (EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among flat panel display devices, liquid crystal display devices are the most widely used due to the advantages of mass production technology, ease of driving means, and high quality.

1 is an exemplary view showing a conventional high resolution liquid crystal display device.

As the manufacturing technology of the liquid crystal display device develops, a large area and a high resolution liquid crystal display device have been manufactured.

In a large area and high resolution liquid crystal display, the panel load increases due to the large area, and high speed driving is required due to the high resolution.

However, when a panel built-in gate driver (GIP: Gate In panel) is formed in the liquid crystal display device which is formed in a large area and is driven at a high speed as described above, delay of signal transmission is seriously generated, and thus the charge ( There is a lack of charging and poor color mixing. Therefore, in the liquid crystal display device having a large area and a high resolution, the panel embedded gate driver GIP cannot operate normally.

That is, in a large area and high resolution liquid crystal display device, since the number of gate lines is increased to twice the number of gate lines in a liquid crystal display device having a normal resolution, the delay according to the clock capacitance CLK Cap increases, and thus Therefore, the gate falling time of the clock CLK input to the gate driver increases. Therefore, in a large-area and high-resolution liquid crystal display device, a panel-embedded gate driver (GIP) in which elements for outputting a scan signal to a gate line are formed directly on a panel cannot be normally operated.

Therefore, in a large-area and high-resolution liquid crystal display device, for example, a UD-class liquid crystal display device, as shown in FIG. 1, each of the integrated gate drive ICs is mounted on a tape carrier package (TCP) to form a TAB ( The gate driver 20 is configured in the form of being connected to the panel 10 by Tape Automated Bonding. In addition, the gate driver 20 applied to a large area and high resolution liquid crystal display device may be mounted on the non-display area 11 of the panel 10 in a chip on glass (COG) manner.

In general, in the large-area and high-resolution liquid crystal display device as shown in FIG. 1, the gate driver 20 is mounted in the non-display areas 11 on both the left and right sides of the panel 10, and the panel ( The data driver 30 is mounted in the non-display area 11 at both the upper and lower sides of 10), and two timing controllers 40 for controlling the two data drivers 30 are independent of the main board 50. Can be mounted on each.

In detail, among the conventional liquid crystal display devices which input a signal only at the upper left and right sides of the panel, a liquid crystal display device that uses a-Si, has a size of 21.6 ”to 60”, and is driven by FHD It is produced using a panel embedded gate driver (GIP). However, the liquid crystal display device having a large area of 72 ”or more and driven at FHD and ultra high resolution (UD class) has a load (R / C) more than twice as large as the conventional liquid crystal display device and is charged. Since Charging Time is reduced by 2 times, it cannot be driven by a conventional general panel embedded gate driver (GIP).

That is, when a liquid crystal display device having a large area of 72 ”or more and driven at FHD and ultra high resolution (UD-class) is composed of a conventional general GIP, the cap / resistance applied to the clock CLK is large and the delay is already made. Since the clock CLK in this severe state is input to the panel embedded gate driver GIP, even if the design of the panel embedded gate driver GIP is optimized, normal driving of the liquid crystal display device is impossible.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problem, and a technical object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of inputting a clock to both ends of a panel-embedded gate driver (GIP).

According to an aspect of the present invention, there is provided a liquid crystal display device including: a panel in which pixels are formed at intersections of data lines and gate lines; A data driver for supplying a data voltage to the data lines; A timing controller driving the data driver; And a first panel embedded gate driver which is embedded in the first non-display area of the panel and driven by the same clocks input from the timing controller to sequentially supply scan signals to the gate lines.

According to another aspect of the present invention, there is provided a liquid crystal display device including: a panel in which pixels are formed at intersections of data lines and gate lines; A first data driver connected to the panel in a third non-display area of the panel and supplying a data voltage to the data lines; A second data driver connected to the panel in a fourth non-display area facing the third non-display area of the panel and supplying a data voltage to the data lines; A first timing controller for driving the first data driver; A second timing controller for driving the second data driver; It is embedded in the first non-display area of the panel and is driven by a first clock input from the first timing controller and a second clock input from the second timing controller to sequentially scan the gate lines. A first panel embedded gate driver configured to supply a signal; And a third clock inputted from the first non-display area facing the first non-display area of the panel, the third clock being input from the first timing controller and the fourth clock being input from the second timing controller. And a second panel built-in gate driver which is driven to sequentially supply scan signals to the gate lines, wherein the first to fourth clocks have the same amplitude and period.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method comprising: generating a gate control signal, a data control signal, and image data by using timing signals input from an external system; Transmitting a clock included in the gate control signal to each of two different stages in the panel embedded gate driver embedded in the panel; Sequentially outputting scan signals generated using the two clocks to gate lines formed in the panel; And outputting the data voltage generated using the data control signal and the image data to the data lines while the scan signal is output to the gate line.

According to the present invention, since a liquid crystal display device applied to a large area and ultra high resolution (FHD / UD) television can be implemented by a panel built-in gate driver (GIP), a large area and ultra high resolution (FHD / UD) The manufacturing process of the liquid crystal display device applied to the television can be simplified, and the manufacturing cost can be reduced.

In addition, according to the present invention, since the gate driver IC can be omitted in a liquid crystal display device applied to a large area and ultra high resolution (FHD / UD) television, the manufacturing cost of the liquid crystal display device can be reduced, and the liquid crystal It is possible to improve the design of the display device.

1 is an exemplary view showing a conventional high resolution liquid crystal display device.
2 is a schematic view of a liquid crystal display device according to the present invention;
3 is a view showing a first embodiment of a panel-type gate driver applied to a liquid crystal display according to the present invention.
4 is a view showing a second embodiment of a panel-embedded gate driver applied to a liquid crystal display according to the present invention.
5 is another schematic view of a liquid crystal display device according to the present invention;

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a view schematically showing a liquid crystal display according to the present invention.

In the liquid crystal display according to the present invention, as illustrated in FIG. 2, a panel 100 in which pixels are formed at intersections of data lines DL1 to DLd and gate lines GL1 to GLg, and the data A data driver 300 for supplying data voltages to the lines DL1 to DLd, a timing controller 400 for driving the data driver 300, and a first non-display area of the panel 100, And a first panel embedded gate driver 200a which is driven by the same clocks input from the timing controller 400 and sequentially supplies scan signals to the gate lines GL1 to GLg.

First, the panel 100 includes pixels formed in regions defined by intersections of the gate lines GL1 to GLg and the data lines DL1 to DLd formed in the display area 110, and each of the pixels A thin film transistor TFT is formed thereon.

The thin film transistor TFT supplies a data voltage supplied from the data line to the pixel electrode in response to a scan signal supplied from the gate line. The transmittance of light is adjusted by driving the liquid crystal positioned between the pixel electrode and the common electrode in response to the data voltage.

As for the liquid crystal mode of the panel applied to this invention, not only TN mode, VA mode, IPS mode, FFS mode but any kind of liquid crystal mode is possible. In addition, the liquid crystal display according to the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display.

Next, the data driver 300 converts the digital image data transmitted from the timing controller 400 into a data voltage to convert the data voltage of one horizontal line for every one horizontal period during which a scan signal is supplied to the gate line. Supply to the data lines.

As illustrated in FIG. 2, the data driver 300 may include at least one source driver IC connected to the panel 100 in a chip on film (COF) form or a tape carrier package (TCP) method. . That is, the data driver 300 generically refers to a plurality of source drive ICs, and the functions of each of the source drive ICs are the same. Hereinafter, the data driver 300 refers to each of the source drive ICs.

The data driver 300 converts the image data into the data voltage using the gamma voltages supplied from a gamma voltage generator (not shown), and then outputs the image data to the data line. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal by using data control signals SSC and SSP received from the timing controller 400.

The latch unit latches the digital image data Data sequentially received from the timing controller 400, and simultaneously outputs the digital image data to the digital analog converter DAC.

The digital-to-analog converter converts the image data transmitted from the latch unit into a positive or negative data voltage at the same time and outputs the data voltage. That is, the digital-to-analog converter determines the image data according to the polarity control signal POL transmitted from the timing controller 400 by using the gamma voltage supplied from the gamma voltage generator (not shown). The data voltage is converted into a polarity or a negative data voltage and output to the data lines.

The output buffer is a data line DL of the panel according to the source output enable signal SOE transmitted from the timing controller 400 to the positive or negative data voltage transmitted from the digital analog converter. Output to

Next, the timing controller 400 uses the timing signal input from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. The gate control signal GCS for controlling the operation timing of the first panel embedded gate driver 200a and the data control signal DCS for controlling the operation timing of the data driver 300 are generated, and the data driver ( The image data to be transmitted to 300 is generated.

To this end, the timing controller 400 may include a receiver for receiving input image data and timing signals from the external system 600, a control signal generator for generating various control signals, and the input image data. Rearranging the data, a data alignment unit for outputting the rearranged image data, and an output unit 440 for outputting the control signals and the image data.

In other words, the timing controller 400 rearranges the input image data input from the external system 600 according to the structure and characteristics of the panel 100 and realigns the rearranged image data with the data driver. Send to 300. This function may be executed in the data alignment unit.

The timing controller 400 uses the timing signals transmitted from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. A data control signal DCS for controlling a driver and a gate control signal GCS for controlling the first panel embedded gate driver are generated, and the control signals are transmitted to the data driver and the first panel embedded gate driver. It performs the function. Such a function may be executed by the control signal generator 400b.

The gate control signals GCS generated by the control signal generator 400b include a gate output enable signal GOE, a gate start signal VST, a clock CLK, and the like.

The data control signals generated by the control signal generator 400b include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like. .

Lastly, the first panel embedded gate driver 200a sequentially uses the gate control signals GCS generated by the timing controller 400 to sequentially turn on the gate lines GL1 to GLg. To supply.

The gate-on signal refers to a voltage capable of turning on the switching thin film transistors connected to the gate lines. The voltage capable of turning off the switching thin film transistor is called a gate-off signal, and the gate-on signal and the gate-off signal are collectively called a scan signal.

When the thin film transistor is N type, the gate on signal is a high level voltage, and the gate off signal is a low level voltage. When the thin film transistor is a P type, the gate on signal is a low level voltage, and the gate off signal is a high level voltage.

On the other hand, the liquid crystal display device according to the present invention has a large area of 72 ″ or more and is driven at FHD and ultra high resolution (UD class). In such a large area high resolution liquid crystal display device, as shown in FIG. In each of the two non-display areas of the panel 100, panel-integrated gate drivers 200a and 200b are embedded. Hereinafter, for convenience of description, a non-display area formed on the left side of the panel 100 in FIG. 2 is called a first non-display area, and a non-display area facing the second non-display area is called a second non-display area. The non-display area formed on the upper side is called a third non-display area, and the non-display area facing the non-display area is called a fourth non-display area.

The panel embedded gate driver embedded in the first non-display area is referred to as a first panel embedded gate driver 200a, and the panel embedded gate driver embedded in the second non-display area is referred to as a second panel embedded gate driver. The data driver 300 connected to the third non-display area is referred to as a first data driver, and the data driver 300 connected to the fourth non-display area is referred to as a second data driver. do.

The first panel embedded gate driver 200a and the second panel embedded gate driver 200b have the same structure and function. Therefore, hereinafter, the present invention will be described with the first panel embedded gate 200a as an example.

The first panel embedded gate driver 200a receives the gate control signal generated by the timing controller and sequentially outputs the scan signal to the gate lines using the gate control signal.

The first panel embedded gate driver 200a may be provided through a first clock input from the timing controller through one side of the first panel embedded gate driver 200a and the other side of the first panel embedded gate driver 200a. The second clock is driven by a second clock input from the timing controller, and the first clock and the second clock have the same amplitude and period.

That is, the timing controller 400 outputs two clocks CLK1 and CLK2 having the same amplitude and period. As shown in FIG. 2, the first clock CLK1 of the two identical clocks is adjacent to one side of the first panel embedded gate driver 200a, that is, adjacent to the first data driver 300. The first panel embedded gate driver 200a is input to the first panel embedded gate driver 200a, and the second clock CLK2 is connected to the other end of the first non-display region, that is, the fourth non-display region. It is input to the gate driver 200a.

As illustrated in FIG. 2, the first clock CLK1 may include a first clock transmission line formed on a chip on film (COF) or a tape carrier package (TCP) on which the first data driver 300 is mounted. After being transmitted to the panel 100 through 210, it may be input to the first panel embedded gate driver 200a. However, the first clock CLK1 does not depend on the chip-on-film COF or the tape carrier package TCP on which the first data driver 300 is mounted, but instead of the timing controller 400 and the first clock CLK1. It may be transmitted from the timing controller 400 to the first panel embedded gate driver 200a through the first clock transmission line 210 directly connected to one side of the one panel embedded gate driver 200a.

As shown in FIG. 2, the second clock CLK2 connects the second clock transmission line 220 directly connected to the other side of the timing controller 300 and the first panel embedded gate driver 200a. Through the timing controller 400, the first panel embedded gate driver 200a may be transmitted. However, the second clock transmission line 220 has the same shape as the first clock transmission line 210 as shown in FIG. 2, and the first panel embedded gate driver 200a of the first non-display area. After being formed in one direction of, the second panel may extend along the first non-display area to the other side of the first panel embedded gate driver 200a and be connected to the first panel embedded gate driver 200a on the other side. That is, the second clock transmission line 220 may be formed of a general wire, formed on a film, or formed on the panel 100 in the form of line on glass.

A detailed internal configuration of the first panel embedded gate driver 200a will be described below with reference to FIGS. 3 and 4.

3 is a view showing a first embodiment of a panel-type gate driver applied to a liquid crystal display according to the present invention.

A first embodiment of a panel embedded gate driver applied to a liquid crystal display according to the present invention includes a plurality of stages 230 connected to each gate line, as shown in FIG. 3.

As described above, the liquid crystal display according to the present invention has a large area of 72 ”or more and is driven at FHD and ultra high resolution (UD class). Hereinafter, for convenience of description, the panel is of ultra high resolution (UD class). The present invention will be described taking the case of driving in a) as an example.

When the panel 100 is driven at an ultra high resolution UD, 2160 gate lines are formed in the panel 100.

Accordingly, 2160 stages Stage1 to Stage2160 are formed in the first panel embedded gate driver 200a, and the first scan signals VGOUT1 to 2160 scan signals VGOUT2160 are formed from the stages. Is output.

The internal configuration and function of the stage 230 may be configured in various forms by the current general technology, and a detailed description thereof will be omitted. In addition, since the gate control signal input to the stage may be variously formed according to an internal configuration and a function of the stage 230, below, basic signals, that is, the clock CLK and the gate start signal ( The invention is described using only VST).

In addition to the stages directly connected to the gate lines, the first panel gate driver 200a may further include dummy line stages.

First, the basic operation of the stage 230 will be described.

That is, when the gate start signal VST is input to the first stage Stage1 of the stages 230, the first stage Stage1 starts driving. The first stage Vstage1 generates a first scan signal (gate on signal) VGOUT1 using the clock CLK and the gate start signal VST, and outputs the first scan signal VGOUT1 to the first gate line GL1. The first scan signal is transmitted to a second stage Stgae. The second stage Stage2 starts driving by the first scan signal VGOUT1, and then generates a second scan signal VGOUT2 using the clock CLK and the gate start signal VST. Output to 2 gate lines GL2.

The operation as described above is repeated to the third stage (Stage3) to the 2160 stage (Stage2160).

That is, the stages sequentially output the scan signal VGOUT to each gate line using the clock CLK and the gate start signal VST.

Meanwhile, a characteristic of the first panel embedded gate driver 200a operated as described above is that the clock CLK used in the respective stages is configured to generate the scan signal. In addition, it is input through the 2160 stage (Stage2160).

That is, in the panel-type gate driver applied to the conventional liquid crystal display device, the clock CLK is input only to the first stage, but in the present invention, the first stage Stage1 and the second 160 stage Stage2160 It is input through).

In detail, when the first panel embedded gate driver 200a includes the first stage Stage1 to the 2160 stage Stage2160, the first panel embedded gate driver 200a may include the timing controller. The first clock CLK1 input from the 400 to the first stage Stage1 and the second clock CLK2 input from the timing controller to the nth stage Stagen are driven by the first clock CLK2. CLK1) and the second clock CLK2 have the same amplitude and period.

In this case, the first clock line 241 to which the first clock is transmitted and the second clock line 242 to which the second clock is transmitted are connected to each other.

Accordingly, a clock substantially input to the 1078th stage (Stage1078) to the 1082st stage (Stage1082) disposed at an intermediate position among the first stage (Stage1) to the second 160 stage (Stage2160) is the first clock. It may be the sum of CLK1 and the second clock CLK2. If the amplitude of the first clock CLK1 and the second clock CLK2 is appropriately set in consideration of the attenuation and delay in the first clock line 231 and the second clock line 242, the stage Delay time between the clocks that are substantially input to the can be reduced, thereby, a normal image can be output through the panel 100.

That is, in the first embodiment of the panel-type gate driver as described above, the first and second clocks CLK1 and CLK2 output from the timing controller 400 are the first panel-integrated gate driver. A first clock line 241 and a second clock CLK2 to which the first clock CLK1 is input; Two clock lines 242 are connected to each other.

4 is a view showing a second embodiment of a panel-type gate driver applied to a liquid crystal display according to the present invention. In the following description, the same or similar contents as those described with reference to FIGS. 2 and 3 will be omitted or simply described.

The second embodiment of the panel-embedded gate driver applied to the liquid crystal display according to the present invention includes a plurality of stages 230 connected to each gate line, as shown in FIG. 4.

A characteristic of the second panel embedded gate driver 200b is that the clock CLK used in the respective stages to generate the scan signal is not only the first stage Stage1 but also the nth stage ( It is also input through Stage2160 (n is called 2160).

In detail, when the first panel embedded gate driver 200a includes the first stage (Stage1) to the nth stage (Stage2160), the first panel embedded gate driver 200a may include the timing controller ( The first clock CLK1 input from the 400 to the first stage Stage1 and the second clock CLK2 input from the timing controller to the nth stage Stagen are driven by the first clock CLK2. CLK1) and the second clock CLK2 have the same amplitude and period.

In the first panel embedded gate driver 200a, the first clock line 241 to which the first clock is transmitted is, as illustrated in FIG. 4, an n / 2 stage from the first stage (Stage1). The second clock line 242 to which the second clock is transmitted is connected from the (n / 2) + th stage (Stage1081) to the nth stage (Stage2160).

In this case, the first clock CLK1 is inputted to the first stage Stage1 to the 1080 stage Stage1080 in the conventional FHD liquid crystal display device including 1080 gate lines. CLK) is the same as driving the first stage to the 1080 stage.

In addition, when the first clock CLK2 is input to the 1081 stage (Stage1081) to the 2160 stage (Stage2160), in the conventional FHD liquid crystal display device including 1080 gate lines, one clock ( It is equivalent to 1080 stages being sequentially driven by CLK).

That is, in the second embodiment of the panel-type gate driver as described above, the stages are driven in the same manner as the stages applied to the conventional FHD liquid crystal display device are driven. Therefore, a delay time between clocks input to the 2160 stages may be reduced, and thus, a normal image may be output through the panel 100.

In detail, in the second embodiment of the panel embedded gate driver as described above, the first clock CLK1 and the second clock CLK2 output from the timing controller 400 are the first panel embedded type. The first clock line 241 and the second clock CLK2, which are input to the first stage Stage1 and the last stage Stagen of the gate driver 200a, are input to the first clock CLK1. The input second clock lines 242 are separated from each other.

On the other hand, the liquid crystal display device according to the present invention, as described above with reference to Figure 2, is formed in the first panel built-in gate driver 200a and the second non-display area formed in the first non-display area The second panel may include an embedded gate driver 200b.

That is, the liquid crystal display according to the present invention may be embedded in a second non-display area facing the first non-display area of the panel 100, and may be inputted from the timing controller 400. And a second panel embedded gate driver 200b driven by the same clocks and sequentially supplying scan signals to the gate lines, and the two inputted to the first panel embedded gate driver 200a. Clocks CLK1 and CLK2 and the two clocks CLK3 and CLK4 input to the second panel embedded gate driver 200b have the same amplitude and period.

In this case, the second panel embedded gate driver 200b may be configured in the same form as the first panel embedded gate driver 200a.

5 is another view schematically showing a liquid crystal display according to the present invention. In the following description, the same or similar contents as those described with reference to FIGS. 2 to 4 will be omitted or simply described.

As described above, the liquid crystal display device according to the present invention has a large area of 72 ″ or more and is driven at FHD and ultra high resolution (UD class). In such a large area high resolution liquid crystal display device, it is shown in FIG. As described above, in addition to each of the two non-display regions of the panel 100, a panel-embedded gate driver is not only embedded therein, and each of the two non-display regions of the panel 100 includes the data driver ( 300a and 300b may be formed.

That is, in the large-area high-resolution liquid crystal display according to the present invention, as shown in FIG. 5, a panel 100 and pixels of each of the intersections of the data lines and the gate lines are formed. A first data driver 300a connected to the panel 100 in a third non-display area, the first data driver 300a supplying a data voltage to the data lines, and the third non-display area facing the third non-display area of the panel 100; A first timing controller 400a connected to the panel 100 in a non-display area and driving the first data driver 300a and a second data driver 300b to supply a data voltage to the data lines ), A first timing controller 400b for driving the second data driver 300b and a first non-display area of the panel 100 and input from the first timing controller 400a. A clock CLK1 and the first The first panel built-in gate driver 200a and the panel 100 are driven by a second clock CLK2 input from the second timing controller 400b to sequentially supply scan signals to the gate lines. A third clock CLK3 that is embedded in a second non-display area facing the first non-display area, and is input from the first timing controller 400a and a fourth input from the second timing controller 400b. And a second panel built-in gate driver 200b driven by a clock CLK4 to sequentially supply scan signals to the gate lines, wherein the first clocks CLK1 to the fourth clocks CLK4 may be provided. , Have the same amplitude and period.

The first timing controller 400a is mounted on the first main board 500a and receives timing signals and input image data from the external system 600 to generate gate control signals, data control signals, and image data. do. The first timing controller 400a may include the first clock CLK1 and the third clock CLK3 among the gate control signals of the first internal gate driver 210 and the second internal gate driver 210. Input to the first stage (Stage1).

The second timing controller 400b is mounted on the second main board 500b and receives timing signals and input image data from the external system 600 to generate gate control signals, data control signals, and image data. do. The second timing controller 400b may end the second clock signal CLK2 and the fourth clock CLK4 of the gate control signal with the last of the first internal gate driver 210 and the second internal gate driver 210. The second stages (Stage2160).

The first gate driver 210 and the second gate driver 220 may be formed as shown in FIG. 3, or may be formed as shown in FIG. 4.

That is, in the first panel embedded gate driver 200a, the first clock line to which the first clock CLK1 is transmitted and the second clock line to which the second clock is transmitted are connected to each other, and the second clock line is connected to each other. In the panel embedded gate driver 200b, a third clock line to which the third clock CLK3 is transmitted and a fourth clock line to which the fourth clock CLK4 is transmitted may be connected to each other.

In addition, when each of the first panel embedded gate driver 200a and the second panel embedded gate driver 200b is configured of the first stage to the nth stage, the first panel embedded gate driver 200a may be used. The first clock line to which the first clock CLK1 is transmitted is connected from the first stage Stage1 to the n / 2th stage Stagen / 2, and the second clock CLK2 is transmitted. The second clock line is connected from the (n / 2) +1 stage (Stage (n / 2) +1) to the nth stage (Stagen), and in the second panel embedded gate driver 200b, The third clock line through which the third clock CLK3 is transmitted is connected from the first stage Stage1 to the n / 2th stage Stagen / 2, and the fourth clock CLK4 is transmitted. The four clock lines may be connected from the (n / 2) + 1th stage (n / 2) +1 to the nth stage (Stagen).

That is, the driving method of the liquid crystal display according to the present invention configured as described above comprises the steps of: generating a gate control signal, a data control signal, and image data by using timing signals input from the external system 600; Transmitting a clock included in the gate control signal to each of two different stages in the panel embedded gate driver embedded in the panel 100, and scanning the scan signal generated using the two clocks. Sequentially outputting to the gate lines formed at 100 and the data voltages generated by using the data control signal and the image data, while the scan signal is output to the gate lines. It may include the step of outputting.

In the following, the contents described above are briefly summarized.

The biggest problem when the panel embedded gate driver (GIP) is used in a UD-class panel is that the clock with a large delay is input to the panel embedded gate driver because the cap / resistance applied to the clock CLK is large. . For this reason, even if the design of the panel-integrated gate driver is optimized, defects such as color mixing are likely to occur.

The present invention is to solve the above problems, by inputting the clock (CLK) to the dual (Dual) at the top and bottom of the panel, reduce the load on the clock (CLK) in half, delay It is to improve deterioration. As a result of the simulation, it was confirmed that the rising and falling time is improved by 10 to 12% compared to the conventional one. In addition, due to the effect of increasing the high voltage of the Q node of each stage by more than 1.0V, the rising time is improved by about 15%, and the defect due to lack of charging may be improved.

Particularly, in the present invention, as in the second embodiment, the clock CLK is input to the dual up and down, but the middle 1 to 1080, 1081 to 2160 stages are separated, and the load applied to the clock CLK is removed. You can cut it in half, even separate the drive itself, and even cut the panel load in half, improving the delay deterioration of the gate output.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: panel 200a, 200b: gate driver
300, 300a, 300b: data driver 400, 400a, 400b: timing controller
500, 500a, 500b: Motherboard 600: External system

Claims (10)

delete delete delete delete delete delete A panel in which pixels are formed at intersections of the data lines and the gate lines;
A first data driver connected to the panel in a third non-display area of the panel and supplying a data voltage to the data lines;
A second data driver connected to the panel in a fourth non-display area facing the third non-display area of the panel and supplying a data voltage to the data lines;
A first timing controller for driving the first data driver;
A second timing controller for driving the second data driver;
It is embedded in the first non-display area of the panel and is driven by a first clock input from the first timing controller and a second clock input from the second timing controller to sequentially scan the gate lines. A first panel embedded gate driver configured to supply a signal; And
It is built in a second non-display area facing the first non-display area of the panel, and is driven by a third clock input from the first timing controller and a fourth clock input from the second timing controller. And a second panel embedded gate driver configured to sequentially supply scan signals to the gate lines.
And the first to fourth clocks have the same amplitude and period. The method of claim 7, wherein
In the first panel embedded gate driver, a first clock line to which the first clock is transmitted and a second clock line to which the second clock is transmitted are connected to each other,
And a third clock line to which the third clock is transmitted and a fourth clock line to which the fourth clock is connected in the second panel embedded gate driver. The method of claim 7, wherein
Each of the first panel embedded gate driver and the second panel embedded gate driver may include a first stage to an nth stage.
In the first panel embedded gate driver, a first clock line to which the first clock is transmitted is connected from the first stage to an n / 2 stage, and a second clock line to which the second clock is transmitted is: Connected from the (n / 2) + 1th stage to the nth stage,
In the second panel embedded gate driver, a third clock line to which the third clock is transmitted is connected from the first stage to the n / 2 stage, and a fourth clock line to which the fourth clock is transmitted is A liquid crystal display device connected from the (n / 2) + 1th stage to the nth stage. delete

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