KR102148489B1 - Power supplying apparatus for display device - Google Patents

Abstract

In the power supply device of the display device according to the present invention, the first buck converter 151 generates and holds the first logic voltage VCC 3.3 at a first timing t1 by stepping down the input power Vin. ); The first logic voltage VCC 3.3 input through the first node N1 is stepped down to generate a second logic voltage VCC 1.2 lower than the first logic voltage VCC 3.3, and the A second buck converter 152 that outputs the second logic voltage VCC 1.2 to a timing controller at a second timing t2 following the first timing t1; And a third timing t3 following the second timing t2 of the first logic voltage VCC 3.3 switched according to the second logic voltage VCC 1.2 and held by the first buck converter 151. And a power sequence control switch (SW-ISO) outputting to the timing controller.

Description

Power supply for display device {POWER SUPPLYING APPARATUS FOR DISPLAY DEVICE}

The present invention relates to a power supply device for a display device.

Typical display devices include a liquid crystal display (LCD) using a liquid crystal, and an OLED display using an organic light emitting diode (OLED). OLED display devices and LCDs are applied in many fields in various sizes ranging from small to large, such as mobile phones, notebook computers, monitors, and TVs.

The display device includes a display panel that displays an image through a pixel matrix, a panel driving circuit that drives the display panel, a timing controller that controls the operation timing of the panel driving circuit, and a power supply circuit that generates power required for driving the panel. do.

Recently, the power supply circuit is integrated into one integrated circuit (hereinafter referred to as "IC"). Hereinafter, the IC in which the power supply device is built will be referred to as a power IC. When the power supply voltage switch of the display device is turned on, the input power of the power IC increases, and a logic voltage required for the operation of the timing controller is output.

The logic voltage applied to the timing controller is usually one, but may be plural in some cases. When there are multiple logic voltages required by the timing controller, these logic voltages must be applied to the timing controller according to the power sequence determined by the timing controller. However, in order to output a logic voltage according to a power sequence, there are several problems (increased manufacturing cost, increased circuit size), such as a complex external device must be added to the power IC.

Accordingly, an object of the present invention is to provide a power supply device for a display device that outputs a plurality of logic voltages according to a power sequence, and simplifies a circuit structure.

In the power supply device of the display device according to the exemplary embodiment of the present invention, the first buck is configured to generate and hold the first logic voltage VCC 3.3 at a first timing t1 by stepping down the input power Vin. Converter 151; The first logic voltage VCC 3.3 input through the first node N1 is stepped down to generate a second logic voltage VCC 1.2 lower than the first logic voltage VCC 3.3, and the A second buck converter 152 that outputs the second logic voltage VCC 1.2 to a timing controller at a second timing t2 following the first timing t1; And a third timing t3 following the second timing t2 of the first logic voltage VCC 3.3 switched according to the second logic voltage VCC 1.2 and held by the first buck converter 151. And a power sequence control switch (SW-ISO) outputting to the timing controller.

The power sequence control switch (SW-ISO) is incorporated in a power IC in which the first and second buck converters 151 and 152 are integrated.

In the power sequence control switch (SW-ISO), a first electrode is connected to the first node (N1), a second electrode is connected to an output terminal of the first logic voltage (VCC 3.3), and a control electrode is connected to the first node (N1). 2 connected to the output of the logic voltage (VCC 1.2); The first buck converter 151 includes a first capacitor C1 connected to the first node N1 and a first inductor L1 connected between the second node N2 and the first node N1. ), a control electrode is connected to the output terminal of the first logic voltage (VCC 3.3), a first electrode is connected to the input power (Vin), and a second electrode is connected to the second node (N2) (SW1); The second buck converter 152 is between a second capacitor C2 connected to an output terminal of the second logic voltage VCC 1.2, and an output terminal of the third node N2 and the second logic voltage VCC 1.2 A first inductor L2 connected to and a control electrode is connected to the output terminal of the second logic voltage VCC 1.2, a first electrode is connected to the first node N1, and a second electrode is connected to the third node. It includes a second switch (SW2) connected to (N3).

The power supply circuit of the present invention connects two buck converters each generating the first and second logic voltages using a built-in power sequence control switch, so that the first and second buck converters are optimized according to the power sequence through a simplified internal configuration as much as possible. It becomes possible to output the logic voltage. The present invention has a very advantageous effect in commercialization because it can significantly reduce manufacturing cost and circuit size compared to the case of adding a conventional complex external element.

1 is a block diagram showing a display device according to an exemplary embodiment of the present invention.
2 is a view showing a power IC that is a power supply circuit of the present invention.
3 is a diagram showing timings at which first and second logic voltages are output from the power IC of FIG. 2 according to a power sequence.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

1 shows a display device according to an embodiment of the present invention.

In the following description, the display device is described centering on the liquid crystal display device, but it should be noted that the technical idea of the present invention is not limited to the liquid crystal display device and can be applied to other display devices.

1, the display device of the present invention includes a display panel 10, a display panel driving circuit, a timing controller 11 for controlling the display panel driving circuit, a power supply circuit 15 for generating a power voltage, and the like. Include.

The display panel 10 includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer therebetween. The display panel 10 includes a pixel array that displays video data. The lower glass substrate includes TFTs formed at each intersection of the data lines D1 to Dm and the gate lines G1 to Gn, and pixel electrodes connected to the TFTs. Each of the liquid crystal cells of the pixel array is driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied, and is incident from the backlight unit 16. Display an image of video data by adjusting the amount of light transmitted.

A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, etc., and is formed on the upper glass substrate. It may be formed on a lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method.

A polarizing plate is attached to each of the upper and lower glass substrates of the display panel 10 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above. In addition, the display device of the present invention may be implemented in any form such as a transmissive display device, a transflective display device, and a reflective display device. In the transmissive liquid crystal display device and the transflective display device, the backlight unit 16 is required.

The display panel driving circuit includes a data driving circuit 12 connected to the data lines D1 to Dm of the display panel 10, and a gate driving circuit connected to the gate lines G1 to Gn of the display panel 10 ( 13). The display panel driving circuit converts digital video data input from the timing controller 11 into an analog data voltage and writes the video data to the pixels of the display panel 10. In addition, the display panel driving circuit sequentially supplies gate pulses (or scan pulses) for selecting pixels of one line into which video data is to be written to the gate lines G1 to Gn of the display panel 10.

The data driving circuit 12 includes a plurality of source drive ICs. Each of the source drive ICs samples digital video data (RGB) input from the timing controller 11 in response to data timing control signals (SSP, SSC, SOE) and polarity control signals (POL) from the timing controller 11. It latches and converts it into parallel data system data Each of the source drive ICs converts the digital video data converted by the parallel data transmission scheme into a positive/negative analog video data voltage to be charged in the liquid crystal cells using positive/negative gamma reference voltages. A gamma reference voltage generation circuit (not shown) divides VDD output from the power supply circuit 15 to generate positive gamma reference voltages between VDD and HVDD, and divides HVDD output from the power supply circuit 15 to HVDD. Negative gamma reference voltages between the and the ground voltage source GND are generated. Meanwhile, the positive gamma reference voltages and the negative gamma reference voltages may be generated by dividing VDD, and in this case, HVDD may be omitted. Each of the source drive ICs supplies positive/negative analog video data voltages to the data lines (D1 to Dm) and inverts the polarity of the positive/negative analog video data voltage in response to the polarity control signal (POL). .

The gate driving circuit 13 includes a plurality of gate driving ICs. The gate driving circuit 13 includes a shift register that sequentially shifts the gate driving voltage in response to a gate timing control signal (GSP, GSC, GOE) from the timing controller 11, and a gate pulse (or scan) is applied to the gate lines. Pulse) sequentially.

The timing controller 11 receives digital video data (RGB) from the host system 14, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), a dot clock ( It receives timing signals such as CLK). The timing controller 11 transmits digital video data (RGB) to the source drive ICs of the data driving circuit 12. The timing controller 11 includes data timing control signals SSP, SSC, SOE, POL for controlling the operation timing of the source drive ICs using timing signals Vsync, Hsync, DE, CLK, and a gate driving circuit 13 Generates gate timing control signals (GSP, GSC, GOE) for controlling the operation timing of ).

The data timing control signal includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), and a polarity control signal (POL). Include. The source start pulse SSP and the source sampling clock SSC control the sampling timing of data. If the signal transmission system between the timing controller 11 and the data driving circuit 12 is a mini LVDS interface, the source start pulse SSP may be omitted. The polarity control signal POL controls the polarity inversion timing of the data voltage output from the data driving circuit 12. The source output enable signal SOE controls output timing and charge share timing of the data driving circuit.

Gate timing control signals (GSP, GSC, SOE) include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), etc. . The gate start pulse GSP controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit 13.

The host system 14 includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), a dot clock (CLK), etc. along with RGB video data input from a broadcast reception circuit or an external video source. The timing signal of is transmitted to the timing controller 11 through the LVDS interface or the TMDS interface transmission circuit. The host system 14 includes a graphic processing circuit such as a scaler that interpolates the resolution of RGB video data input from a broadcast reception circuit or an external video source according to the resolution of a liquid crystal display panel and interpolates signals, and a power supply circuit 15 It includes a power generation circuit that generates a voltage Vin to be supplied.

The power supply circuit 15 starts to operate when the input power Vin supplied from the host system 14 is equal to or higher than the UVLO (Under Voltage Lock Out) level, and generates an output after a predetermined time delay. Outputs of the power supply circuit 15 include VGH, VGL, VCC 3.3, VCC 1.2, VDD, HVDD, and the like. VGH is a gate high voltage set to be equal to or higher than the threshold voltages of TFTs formed in the TFT array of the liquid crystal display panel, and may be approximately 30V or higher. VGL is a gate low voltage set to a voltage smaller than the threshold voltages of TFTs formed in the TFT array of the liquid crystal display panel, and may be a voltage of -5V. VGH and VGL are supplied to the gate driving circuit 13. VCC 3.3 is the first logic voltage for driving the timing controller 11 and may be a voltage of 3.3V. VCC 1.2 is a second logic voltage for driving the timing controller 11 and may be a voltage of 1.2V. VDD and HVDD are the high-potential power supply voltage and half the high-potential power supply voltage to be supplied to the voltage divider circuit that generates positive/negative gamma reference voltages. VDD may be 16V and HVDD may be 8V.

The power supply circuit 15 is implemented as a power IC. The power IC includes a power sequence control switch (SW-ISO in FIG. 2), thereby simplifying the circuit configuration as much as possible when performing a predetermined power sequence.

2 shows a power IC that is a power supply circuit of the present invention. In addition, FIG. 3 shows timings at which first and second logic voltages are output from the power IC of FIG. 2 according to the power sequence.

2 and 3, the power supply circuit 15 of the present invention includes a first buck converter 151, a second buck converter 152, and a power sequence control switch SW to perform a predetermined power sequence. -ISO).

The first buck converter 151 performs a function of stepping down the input power Vin to generate and then hold the first logic voltage VCC 3.3 at the first timing t1. To this end, the first buck converter 151 includes a first capacitor C1 connected to the first node N1 and a first inductor L1 connected between the second node N2 and the first node N1. ), and a first switch SW1 connected between the input power Vin and the second node N2. Here, in the first switch SW1, the control electrode is connected to the output terminal of the first logic voltage VCC 3.3, the first electrode is connected to the input power Vin, and the second electrode is connected to the second node N2. It can be connected and configured. The first switch SW1 may be implemented as an N-type MOSFET.

The second buck converter 152 steps down the first logic voltage VCC 3.3 input through the first node N1 to generate a second logic voltage VCC 1.2 lower than the first logic voltage VCC 3.3. ), and outputting the second logic voltage VCC 1.2 to the timing controller 11 at a second timing t2 following the first timing t1. To this end, the second buck converter 152 is between the second capacitor C2 connected to the output terminal of the second logic voltage VCC 1.2, and the output terminal of the third node N2 and the second logic voltage VCC 1.2. It may include a first inductor L2 connected to and a second switch SW2 connected between the first node N1 and the third node N3. Here, in the second switch SW2, the control electrode is connected to the output terminal of the second logic voltage VCC 1.2, the first electrode is connected to the first node N1, and the second electrode is connected to the third node N3. It can be connected to and configured. The second switch SW2 may be implemented as an N-type MOSFET.

The power sequence control switch (SW-ISO) is switched according to the second logic voltage (VCC 1.2) to connect the first logic voltage (VCC 3.3) held in the first buck converter 151 to the second timing (t2). By outputting to the timing controller at the third timing t3, the power sequence (1.2V->3.3V) of the timing controller 11 is satisfied.

The power sequence control switch (SW-ISO) is built in the power IC in which the first and second buck converters 151 and 152 are integrated, thereby simplifying the configuration of a power IC that satisfies the power sequence as much as possible. do. The power sequence control switch (SW-ISO) may be implemented as an N-type MOSFET.

As described above, the power supply circuit of the present invention connects the two buck converters each generating the first and second logic voltages using a built-in power sequence control switch, so as to fit the power sequence through a simplified internal configuration as much as possible. It becomes possible to output the first and second logic voltages. The present invention has a very advantageous effect in commercialization because it can significantly reduce manufacturing cost and circuit size compared to the case of adding a conventional complex external element.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
15: power supply circuit

Claims (3)

A first buck converter 151 for stepping down the input power Vin to generate and hold the first logic voltage VCC 3.3 at a first timing t1;
The first logic voltage VCC 3.3 input through the first node N1 is stepped down to generate a second logic voltage VCC 1.2 lower than the first logic voltage VCC 3.3, and the A second buck converter 152 that outputs the second logic voltage VCC 1.2 to a timing controller at a second timing t2 following the first timing t1; And
The first logic voltage VCC 3.3, which is switched according to the second logic voltage VCC 1.2 and held by the first buck converter 151, is applied at a third timing t3 following the second timing t2. A power supply device for a display device, comprising: a power sequence control switch (SW-ISO) outputting to a timing controller. The method of claim 1,
The power sequence control switch (SW-ISO) is a power supply device, characterized in that the first buck converter (151) and the second buck converter (152) are integrated in the integrated power IC. The method of claim 1,
In the power sequence control switch (SW-ISO), a first electrode is connected to the first node (N1), a second electrode is connected to an output terminal of the first logic voltage (VCC 3.3), and a control electrode is connected to the first node (N1). 2 connected to the output of the logic voltage (VCC 1.2);
The first buck converter 151 includes a first capacitor C1 connected to the first node N1 and a first inductor L1 connected between the second node N2 and the first node N1. ), a control electrode is connected to the output terminal of the first logic voltage (VCC 3.3), a first electrode is connected to the input power (Vin), and a second electrode is connected to the second node (N2) (SW1);
The second buck converter 152 is between a second capacitor C2 connected to an output terminal of the second logic voltage VCC 1.2, and an output terminal of the third node N3 and the second logic voltage VCC 1.2 A second inductor L2 connected to and a control electrode is connected to the output terminal of the second logic voltage VCC 1.2, a first electrode is connected to the first node N1, and a second electrode is connected to the third node. A power supply device for a display device comprising a second switch SW2 connected to (N3).

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