KR20160035194A - Power supplying apparatus for display device - Google Patents

Abstract

According to the present invention, a power supply apparatus for a display device comprises: a first buck converter (151) to step down input power (Vin) to generate a first logic voltage (VCC 3.3) at first timing (t1), and then hold the first logic voltage (VCC 3.3); a second buck converter (152) to step down the first logic voltage (VCC 3.3) inputted through a first node (N1) to generate a second logic voltage (VCC 1.2) lower than the first logic voltage (VCC 3.3), and output the second logic voltage (VCC 1.2) to a timing controller at second timing (t2) following the first timing (t1); and a power sequence control switch (SW-ISO) switched by the second logic voltage (VCC 1.2) to output the first logic voltage (VCC 3.3) held by the first buck converter (151) to the timing controller at third timing (t3) following the second timing (t2).

Description

POWER SUPPLYING APPARATUS FOR DISPLAY DEVICE

The present invention relates to a power supply of a display device.

Examples of the display device include a liquid crystal display (LCD) using liquid crystal, and an OLED display using an organic light emitting diode (OLED). OLED displays and LCDs are used in many fields ranging from small to large, such as mobile phones, notebooks, monitors, and TVs.

The display device includes a display panel for displaying an image through a pixel matrix, a panel drive circuit for driving the display panel, a timing controller for controlling the operation timing of the panel drive circuit, and a power supply circuit for generating power necessary for driving the panel do.

In recent years, power supply circuits are integrated into one integrated circuit (hereinafter referred to as "IC "). Hereinafter, an IC in which a power supply device is incorporated will be referred to as a power IC. When the power supply voltage switch of the display device is turned on, the input power of the power IC rises and an output of the logic voltage necessary for the operation of the timing controller is outputted.

The logic voltage applied to the timing controller may typically be one or more. If the timing controller requires a large number of logic voltages, these logic voltages must be applied to the timing controller in accordance with the power sequence specified in the timing controller. However, in order to output a logic voltage in accordance with a power sequence, there are various problems (increase in manufacturing cost and increase in circuit size) such that a complicated external device must be added to the power IC.

Accordingly, it is an object of the present invention to provide a power supply of a display device that outputs a plurality of logic voltages in accordance with a power sequence, but can simplify a circuit structure.

The power supply of the display device according to the embodiment of the present invention includes a first buck which generates and holds a first logic voltage VCC 3.3 at a first timing t1 by stepping down an input power supply Vin, A converter 151; Step down the first logic voltage (VCC 3.3) input through the first node (N1) to generate a second logic voltage (VCC 1.2) lower than the first logic voltage (VCC 3.3) A second buck converter (152) for outputting the second logic voltage (VCC 1.2) to the timing controller at a second timing (t2) subsequent to the first timing (t1); And a third timing (t3) after the second timing (t2) when the first logic voltage (VCC 3.3), which is switched according to the second logic voltage (VCC 1.2) and held in the first buck converter (151) And a power sequence control switch (SW-ISO) for outputting to the timing controller.

The power sequence control switch (SW-ISO) is embedded in the power IC in which the first buck converter 151 and the second buck converter 152 are integrated.

The power sequence control switch (SW-ISO) has a first electrode connected to the first node (N1), a second electrode connected to the output terminal of the first logic voltage (VCC 3.3) 2 logic voltage (VCC 1.2); The first buck converter 151 includes a first capacitor C1 connected to the first node N1 and a second inductor L1 connected between the second node N2 and the first node N1, A first electrode connected to the input power supply Vin, a second electrode connected to the second node N2, and a control electrode connected to the output terminal of the first logic voltage VCC 3.3, (SW1); The second buck converter 152 includes a second capacitor C2 connected to the output terminal of the second logic voltage VCC 1.2 and a second capacitor C2 connected between the third node N2 and the output terminal of the second logic voltage VCC 1.2 And a control electrode connected to an output terminal of the second logic voltage (VCC 1.2), a first electrode connected to the first node (N1), a second electrode connected to the third node And a second switch SW2 connected to the node N3.

The power supply circuit of the present invention connects the two buck converters, each of which generates the first and second logic voltages, with a built-in power sequence control switch, so that the first and second It becomes possible to output the logic voltage. The present invention can remarkably reduce the manufacturing cost and the circuit size compared with the case of adding a complicated external device in the past, which is very advantageous for commercialization.

1 is a block diagram showing a display device according to an embodiment of the present invention;
2 is a view showing a power IC which is a power supply circuit of the present invention;
3 is a timing chart showing the timing at which the first and second logic voltages are output in the power IC of FIG. 2 in accordance with the power sequence; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 shows a display device according to an embodiment of the present invention.

In the following description, the display device will be described mainly on the liquid crystal display device, but it should be noted that the technical idea of the present invention is not limited to the liquid crystal display device but can be applied to other display devices.

1, the display device of the present invention includes a display panel 10, a display panel driving circuit, a timing controller 11 for controlling the display panel driving circuit, a power supply circuit 15 for generating a power supply voltage, and the like .

The display panel 10 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The display panel 10 includes a pixel array for displaying video data. The lower glass substrate includes TFTs formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, and pixel electrodes connected to the TFTs. Each of the liquid crystal cells of the pixel array is driven by the voltage difference between the pixel electrode 1 for charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied and is incident from the backlight unit 16 The image of the video data is displayed by adjusting the transmission amount of light.

On the upper glass substrate of the display panel 10, a black matrix, a color filter, and a common electrode are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. The common electrode 2 is formed of a material such as IPS (In Plane Switching) mode, FFS And can be formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving system.

On the upper glass substrate and the lower glass substrate of the display panel 10, an alignment film for attaching a polarizing plate and setting a pre-tilt angle of liquid crystal is formed.

The liquid crystal mode of the display panel 10 applicable to the present invention can be implemented in any liquid crystal mode as well as the TN mode, the VA mode, the IPS mode, and the FFS mode described above. Further, the display device of the present invention can be implemented in any form such as a transmissive display device, a transflective display device, a reflective display device, and the like. In the transmissive liquid crystal display device and the transflective display device, the backlight unit 16 is required.

The display panel driving circuit includes a data driving circuit 12 connected to the data lines D1 to Dm of the display panel 10 and a gate driving circuit 12 connected to the gate lines G1 to Gn of the display panel 10 13). The display panel drive circuit converts the digital video data input from the timing controller 11 into an analog data voltage and writes the video data to the pixels of the display panel 10. [ The display panel driving circuit sequentially supplies gate pulses (or scan pulses) for selecting the pixels of one line to which video data is to be written to the gate lines G1 to Gn of the display panel 10 in sequence.

The data driving circuit 12 includes a plurality of source drive ICs. Each of the source drive ICs samples the digital video data RGB input from the timing controller 11 in response to the data timing control signals SSP, SSC and SOE from the timing controller 11 and the polarity control signal POL Latches and converts the data into data of a parallel data system. Each of the source drive ICs converts the digital video data converted into the parallel data transmission scheme into positive / negative analog video data voltages to be charged in the liquid crystal cells using positive / negative gamma reference voltages. The non-illustrated gamma reference voltage generating circuit divides VDD output from the power supply circuit 15 to generate positive polarity gamma reference voltages between VDD and HVDD, divides the HVDD output from the power supply circuit 15 to generate HVDD And a ground voltage source (GND). On the other hand, the positive gamma reference voltages and the negative gamma reference voltages may be generated with voltages divided by VDD, in which case the HVDD may be omitted. Each of the source drive ICs supplies a positive / negative analog video data voltage to the data lines D1 to Dm and inverts the polarity of the positive / negative analog video data voltage in response to the polarity control signal POL .

The gate drive circuit 13 includes a plurality of gate drive ICs. The gate driving circuit 13 includes a shift register for sequentially shifting the gate driving voltage in response to the gate timing control signals GSP, GSC and GOE from the timing controller 11, Pulse) are sequentially supplied.

The timing controller 11 receives digital video data RGB from the host system 14 and receives a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE, CLK) and the like. The timing controller 11 transfers the digital video data RGB to the source drive ICs of the data driving circuit 12. The timing controller 11 includes data timing control signals SSP, SSC, SOE and POL for controlling the operation timings of the source drive ICs using the timing signals Vsync, Hsync, DE and CLK, The gate timing control signals GSP, GSC, and GOE for controlling the operation timings of the gate control signals GSP, GSC, and GOE are generated.

The data timing control signal includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable (SOE) signal and a polarity control signal . The source start pulse SSP and the source sampling clock SSC control the sampling timing of the data. If the signal transmission system between the timing controller 11 and the data driving circuit 12 is a mini LVDS interface, the source start pulse SSP may be omitted. The polarity control signal POL controls the polarity inversion timing of the data voltage output from the data driving circuit 12. [ The source output enable signal SOE controls the output timing of the data driving circuit and the charge share timing.

The gate timing control signals GSP, GSC and SOE include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE) . The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive circuit 13. [

The host system 14 outputs the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, the dot clock CLK, and the like, together with the RGB video data input from the broadcast receiving circuit or the external video source To the timing controller 11 through the LVDS interface or the TMDS interface transmission circuit. The host system 14 is provided with a graphics processing circuit such as a scaler for interpolating and interpolating the resolution of RGB video data inputted from a broadcast receiving circuit or an external video source in accordance with the resolution of the liquid crystal display panel, And a power generation circuit for generating a voltage Vin to be supplied.

The power supply circuit 15 starts to operate when the input voltage Vin supplied from the host system 14 is equal to or higher than the Under Voltage Lock Out (UVLO) level, and generates an output after a predetermined time delay. The output of the power supply circuit 15 includes VGH, VGL, VCC 3.3, VCC 1.2, VDD, HVDD, and the like. VGH may be a gate high voltage set above the threshold voltage of the TFTs formed in the TFT array of the liquid crystal display panel, and may be a voltage of about 30 V or more. VGL may be a gate low voltage (Gate Low Voltage) set to a voltage smaller than the threshold voltage of the TFTs formed in the TFT array of the liquid crystal display panel, and may be a voltage of -5V. VGH and VGL are supplied to the gate drive circuit 13. VCC 3.3 may be a voltage of 3.3 V as a first logic voltage for driving the timing controller 11. [ VCC 1.2 may be a voltage of 1.2 V as a second logic voltage for driving the timing controller 11. [ VDD and HVDD are the high potential supply voltage and the 1/2 high potential supply voltage voltage to be supplied to the voltage divider circuit generating the positive / negative gamma reference voltages. VDD may be 16V, and HVDD may be 8V.

The power supply circuit 15 is implemented as a power IC. The power IC incorporates a power sequence control switch (SW-ISO in Fig. 2), so that the circuit configuration can be simplified as much as possible in performing a predetermined power sequence.

2 shows a power IC as a power supply circuit of the present invention. 3 shows the timing at which the first and second logic voltages are output in the power IC of FIG. 2 in accordance with the power sequence.

2 and 3, the power supply circuit 15 of the present invention includes a first buck converter 151, a second buck converter 152, and a power sequence control switch (SW) 152 to perform a predetermined power sequence. -ISO).

The first buck converter 151 steps down the input power supply Vin to generate and hold the first logic voltage VCC 3.3 at the first timing t1. To this end, the first buck converter 151 includes a first capacitor C1 connected to the first node N1, a first inductor L1 connected between the second node N2 and the first node N1, And a first switch SW1 connected between the input power supply Vin and the second node N2. Here, the first switch SW1 has a control electrode connected to the output terminal of the first logic voltage (VCC 3.3), a first electrode connected to the input power supply Vin, and a second electrode connected to the second node N2 And can be connected and configured. The first switch SW1 may be implemented as an N-type MOSFET.

The second buck converter 152 steps down the first logic voltage VCC 3.3 input through the first node N1 to generate a second logic voltage VCC 1.2 lower than the first logic voltage VCC 3.3 And outputs the second logic voltage VCC 1.2 to the timing controller 11 at the second timing t2 after the first timing t1. To this end, the second buck converter 152 is connected between a second capacitor C2 connected to the output of the second logic voltage VCC 1.2 and a second capacitor C2 connected between the output of the third node N2 and the second logic voltage VCC 1.2 A first inductor L2 connected to the first node N1 and a second switch SW2 connected between the first node N1 and the third node N3. Here, the second switch SW2 has a control electrode connected to the output terminal of the second logic voltage VCC 1.2, a first electrode connected to the first node N1, a second electrode connected to the third node N3, As shown in FIG. The second switch SW2 may be implemented as an N-type MOSFET.

The power sequence control switch SW-ISO is switched according to the second logic voltage VCC 1.2 to output the first logic voltage VCC 3.3 held at the first buck converter 151 at the second timing t2 And outputs to the timing controller at the third timing t3, thereby satisfying the power sequence of the timing controller 11 (1.2 V ---> 3.3 V).

This power sequence control switch (SW-ISO) is embedded in the power IC in which the first buck converter 151 and the second buck converter 152 are integrated, thereby simplifying the configuration of the power IC satisfying the power sequence as much as possible do. The power sequence control switch (SW-ISO) can be implemented as an N-type MOSFET.

As described above, the power supply circuit of the present invention connects two buck converters, each of which generates the first and second logic voltages, with a built-in power sequence control switch, It becomes possible to output the first and second logic voltages. The present invention can remarkably reduce the manufacturing cost and the circuit size compared with the case of adding a complicated external device in the past, which is very advantageous for commercialization.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
15: Power supply circuit

Claims (3)

A first buck converter 151 for stepping down the input power supply Vin to generate and hold the first logic voltage VCC 3.3 at the first timing t1;
Step down the first logic voltage (VCC 3.3) input through the first node (N1) to generate a second logic voltage (VCC 1.2) lower than the first logic voltage (VCC 3.3) A second buck converter (152) for outputting the second logic voltage (VCC 1.2) to the timing controller at a second timing (t2) subsequent to the first timing (t1); And
(VCC 3.3) which is switched according to the second logic voltage (VCC 1.2) and held in the first buck converter 151 at a third timing (t3) after the second timing (t2) And a power sequence control switch (SW-ISO) for outputting the power sequence control signal to the timing controller. The method according to claim 1,
Wherein the power sequence control switch (SW-ISO) is embedded in a power IC in which the first buck converter (151) and the second buck converter (152) are integrated. The method according to claim 1,
The power sequence control switch (SW-ISO) has a first electrode connected to the first node (N1), a second electrode connected to the output terminal of the first logic voltage (VCC 3.3) 2 logic voltage (VCC 1.2);
The first buck converter 151 includes a first capacitor C1 connected to the first node N1 and a second inductor L1 connected between the second node N2 and the first node N1, A first electrode connected to the input power supply Vin, a second electrode connected to the second node N2, and a control electrode connected to the output terminal of the first logic voltage VCC 3.3, (SW1);
The second buck converter 152 includes a second capacitor C2 connected to the output terminal of the second logic voltage VCC 1.2 and a second capacitor C2 connected between the third node N2 and the output terminal of the second logic voltage VCC 1.2 And a control electrode connected to an output terminal of the second logic voltage (VCC 1.2), a first electrode connected to the first node (N1), a second electrode connected to the third node And a second switch (SW2) connected to the third node (N3).

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