KR20160017871A

KR20160017871A - Liquid Crystal Display

Info

Publication number: KR20160017871A
Application number: KR1020140101330A
Authority: KR
Inventors: 김경록; 박용화; 권기태
Original assignee: 엘지디스플레이 주식회사
Priority date: 2014-08-06
Filing date: 2014-08-06
Publication date: 2016-02-17

Abstract

The present invention is to provide a liquid crystal display device which can improve a dim phenomenon due to a ripple phenomenon of common voltage. According to the present invention, the liquid crystal display device comprises: a liquid crystal display panel having a gate line and a data line formed therein; a gate driving unit outputting a gate pulse to the gate line; a timing controller outputting a dummy data enable signal and dummy data during a vertical blank period, and outputting a data enable signal and digital video data during a display period; and a data driving unit outputting the digital video data to the data line by converting the digital video data into data voltage with a first polarity based on the digital video data during a j^th (j is a natural number) frame period, and outputting dummy data voltage with a second polarity opposite to the first polarity based on the dummy data enable signal and the dummy data during a vertical blank period of a (j+1)^th frame period.

Description

[0001] Liquid crystal display [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

Pixels of a liquid crystal display device include TFTs in which a data line and a gate line are crossed and connected to the intersection. The TFT supplies the data voltage supplied through the data line to the pixel electrode of the liquid crystal cell in response to the gate pulse from the gate line. The liquid crystal cell is rotated by an electric field generated according to the voltage difference between the pixel electrode and the common voltage Vcom applied to the common electrode to control the light flux passing through the polarizer. The storage capacitor is connected to the pixel electrode of the liquid crystal cell to maintain the voltage of the liquid crystal cell. The common voltage Vcom applied to the common electrode may be ripple due to electrical coupling with the pixel electrode. The ripple phenomenon of the common voltage Vcom is proportional to the amount of change of the data voltage with time. Therefore, in the inversion method in which the polarity of the data voltage is varied, the ripple phenomenon of the common voltage Vcom is increased because the fluctuation of the data voltage is large at the moment when the polarity of the data voltage is changed. As described above, the ripple phenomenon of the common voltage Vcom causes a line-dim phenomenon along the horizontal direction, which causes the display quality to deteriorate.

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display capable of improving the dim phenomenon due to the ripple phenomenon of the common voltage.

A liquid crystal display device according to the present invention includes a liquid crystal display panel in which gate lines and data lines are formed, a gate driver for outputting gate pulses to gate lines, a dummy data enable signal and dummy data in a vertical blank period, A timing controller for outputting a data enable signal and digital video data during a frame period, and converting the digital video data to a data voltage of a first polarity based on the digital video data during a j-th (j is a natural number) And a data driver for outputting the dummy data voltage of the second polarity opposite to the first polarity to the data line based on the dummy data enable signal and the dummy data during the vertical blank period of the (j + 1) -th frame period do.

Since the present invention inputs dummy data during the vertical blank period to induce ripple phenomenon of the common voltage to occur by avoiding the display period, the dimming phenomenon due to the ripple phenomenon of the common voltage can be improved in the display period.

1 is a block diagram showing a configuration of a display device according to the present invention;
2 is a block diagram showing a configuration of a data driver according to the present invention;
3 is a waveform diagram showing an output signal of the timing controller and a data voltage output from the data driver according to the present invention;
FIGS. 4 and 5 are schematic diagrams showing a manner in which the gate driver of FIG. 1 scans the display panel. FIG.
6 is a block diagram showing a configuration of a display apparatus according to another embodiment of the present invention;
FIG. 7 and FIG. 8 are schematic diagrams showing the manner in which the gate driver of FIG. 6 scans the display panel.
9 to 11 are waveform diagrams showing output forms of dummy data according to an embodiment of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a block diagram showing a configuration of a liquid crystal display device according to the present invention.

Referring to FIG. 1, a liquid crystal display device according to the present invention includes a liquid crystal display panel 100, a timing controller 200, a data driver 300, and a gate driver 400. The data driver 300 includes a plurality of source driver ICs. The gate driver 400 includes a plurality of gate driver ICs.

The liquid crystal display panel 100 includes a TFT array substrate, a color filter array substrate opposed to the TFT array substrate, and a liquid crystal layer formed between the TFT array substrate and the color filter array substrate. In the liquid crystal layer between the TFT array substrate and the color filter array substrate, the liquid crystal cells Clc are arranged in a matrix form defined by the intersection structure of the data lines DL and the gate lines GL.

The TFT array substrate includes TFTs formed at intersections of data lines DL1 to DLn, gate lines GL1 to GLm, data lines DL1 to DLn and gate lines GL1 to GLm formed on a lower glass substrate, And a pixel electrode 1, a storage capacitor Cst, etc. connected to the TFTs at a ratio of 1: 1. The color filter array substrate includes a black matrix, a color filter, and the like formed on the upper glass substrate. An alignment film is formed on each of the upper glass substrate and the lower glass substrate to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

The common electrode 2 facing the pixel electrode 1 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) And is formed on the lower glass substrate together with the pixel electrode 1 in a horizontal electric field driving method such as FFS (Fringe Field Switching) mode.

The liquid crystal display panel 100 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies the data driver 102 with digital video data (DATA) of the input image input from the system board (not shown) during the display period. The timing controller 101 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board, And generates control signals for controlling the operation timing of the gate driving unit 300 and the gate driving unit 400. The control signals include a gate timing control signal for controlling the operation time of the gate driver 400, and a data timing control signal for controlling the operation timing of the data driver 300 and the vertical polarity of the data voltage.

The timing controller 200 generates the dummy data enable signal DDE during the vertical blank period and generates the dummy data DDATA output during the period in which the dummy data enable signal DDE is provided. The dummy data enable signal DDE and the dummy data DDATA improve the fact that the liquid crystal cell is approximately charged when the polarity of the data voltage is reversed at the beginning of the frame in which the polarity is changed. A detailed description thereof will be described later.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the data driver 102. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source drive ICs on the basis of the rising or falling edge. The polarity control signal POL controls the polarity inversion timing of the data voltages output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driver 102. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driver 102 is transmitted in the mini LVDS interface standard.

The data driver 400 includes a plurality of source drive ICs SIC # 1 to SIC # 4 and includes data lines DL1 to DL4 formed over the first panel block PB1 and the second panel block PB2, DLn. Each of the first to fourth source drive ICs SIC # 1 to SIC # 4 may be connected to the data lines of the liquid crystal display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) have.

2 is a diagram showing an internal circuit configuration of the first to fourth source drive ICs (SIC # 1 to SIC # 4). Each of the first to fourth source drive ICs SIC # 1 to SIC # 4 is connected to data lines DL formed in k (k is a positive integer) first and second panel blocks PB1 and PB2 And supplies positive / negative data voltages.

Each of the first to eighth source driver ICs SIC # 1 to SIC # 8 includes a shift register unit 241, a first latch 243, a second latch 245, a digital-analog converter 247 to Analog Converter (DAC), and an output unit 249.

The shift register unit 241 samples the RGB digital video data bits of the input image using the data control signals SSC and SSP supplied from the timing controller 200.

The first latch 243 samples and latches the digital video data bits according to the clocks sequentially supplied from the shift register unit 241, and simultaneously outputs the latched data. The second latch 245 latches the data provided from the first latch 243 and is responsive to the source output enable signal SOE in synchronization with the second latch 245 of the other source drive ICs 240, Simultaneously output one data.

The DAC 247 converts the video data input from the second latch 245 to the positive gamma compensation voltage GMAH and the negative gamma compensation voltage GMAL to generate the positive / negative analog video data voltage ADATA Occurs. The DAC 247 inverts the polarity of the data voltage ADATA for each frame in response to the polarity control signal POL.

The output unit 249 outputs the data voltage to the data lines DL1 and DL2 through the output buffer during the low logic period of the source output enable signal SOE. If the source driver ICs SIC # 1 to SIC # 4 perform charge sharing, the output unit 340 outputs a positive polarity data voltage and a negative polarity data voltage through charge sharing during a high logic period, And the common voltage Vcom to the data lines DL1 to DLn via the output buffer. During the charge sharing period, the output channels to which the positive data voltages are supplied and the output channels to which the negative data voltages are supplied are short-circuited in the source drive ICs (SIC # 1 to SIC # 4) And supplies an average voltage of the negative data voltages to the data lines DL1 to DLn.

The gate driver 400 generates a gate pulse signal GSP in response to the gate timing control signals GSP, GSC, and GOE input from the timing controller 200 during a display period using a shift register (not shown) and a level shifter (not shown) To the gate lines GL1 to GLm sequentially. The gate driver 400 may be mounted on a gate TCP (not shown) and bonded to a TFT array substrate of a liquid crystal display panel by a TAB process. Alternatively, the gate driver 400 may be directly mounted on a TFT array substrate .

The gate driver 400 does not output the gate pulse since the gate timing control signals GSP, GSC, and GOE are not generated during the vertical blank period BL. Therefore, the TFTs of the TFT array substrate maintain the OFF state, so that the target voltage is not supplied to the liquid crystal cells Clc.

FIG. 3 shows a waveform of a signal output from the timing controller 200 according to the present invention and a data voltage output from the data driver 300, and FIG. 4 is a diagram showing a scan sequence of the display panel according to the first embodiment . The driving of the liquid crystal display according to the present invention will now be described with reference to FIGS. 1 to 4. FIG.

During the display period of the j frame period, the data driver 300 outputs the analog data voltage ADATA by the digital video data DATA and the data enable signal DE of the input image. At this time, the data driver 300 outputs the first voltage level, for example, the negative data voltage ADATA by the polarity control signal POL provided from the timing controller 200.

The timing controller 200 generates a dummy data enable signal (DDE) in the vertical blanking period. The timing controller 200 can detect the vertical synchronization signal Vsync and the data enable signal DE and detect a certain section in which the data enable signal DE is not detected as the vertical blank period.

The timing controller 200 generates a dummy data enable signal (DDE) for a certain period of time within the vertical blanking period. The pulse width of the dummy data enable signal DDE is equal to the pulse width of the data enable signal DE. The dummy data enable signal DDE is held for the width of the period during which the data charging of the liquid crystal cell Clc by the data enable signal DE in the display period scans the gate line where the weak charging can occur. For example, assuming that a period in which two charges are generated in two gate lines GL in the start period of a frame and a period in which one gate line GL is scanned is two horizontal periods (2H), the dummy data enable signal DDE 2 > horizontal period (2H). For example, the dummy data enable signal (DDE) may be input during four horizontal periods (4H) as shown in the figure. Of course, the dummy data enable signal DDE does not exceed the vertical blank period Vsync. Also, the timing controller 200 provides the dummy data to the data driver 300 in response to the output of the dummy data enable signal DDE.

The data driver 300 outputs the dummy data voltage ADDATA based on the dummy data enable signal DDE and the dummy data DDATA in the vertical blanking period. At this time, the data driver 300 outputs a second voltage level, for example, a positive polarity data voltage ADATA, which is a voltage level opposite to the first voltage level, by the polarity control signal POL supplied from the timing controller 200 do.

The timing controller 200 supplies data timing control signals SSP, SSC, and SOE to the liquid crystal cells Clc of the liquid crystal display panel 100 during the display period so that the digital video data DATA of the input image can be addressed to the liquid crystal cells Clc of the liquid crystal display panel 100. [ , POL and gate timing control signals (GSP, GSC, GOE).

The data driver 300 outputs the data voltage ADATA by the data timing control signals DDC and digital video data DATA during the display period. The data driver 300 outputs the data voltage ADATA having the same polarity as the dummy data voltage ADDATA by the polarity control signal POL during the display period.

The gate driver 400 scans the first panel block PB1 during the j-th frame period and the second panel block PB2 during the (j + 1) -th frame period. The gate driver 400 sequentially scans starting from the center gate line of the first panel block PB1. The central gate line is a gate line located at the boundary between the first and second panel blocks PB1 and BP2. For example, when the total gate line GL of the display panel 100 is m, (M / 2) +1) th gate line GL [m / 2] and the [(m / 2) +1] That is, the gate driver 400 sequentially scans from the m / 2th gate line GL [m / 2] located in the first panel block PB1 to the first gate line He. The gate driver 400 sequentially applies the gate signal from the [(m / 2) +1] th gate line GL [(m / 2) +1] located in the second panel block PB2 to the mth gate line GLm .

Since the gate driver 400 sequentially drives the first and second panel blocks PB1 and BP2 starting from the center gate line of the display panel 100, the gate driver 400 sequentially drives the first and second panel blocks PB1 and BP2, It is possible to improve the generation of a dim in the form of a block in which the screen is separated. The brightness of the liquid crystal cells of the display panel 100 varies depending on the position at which the data voltage ADATA is supplied from the data driver 300. The leakage current between the drain and the source of the TFT in the liquid crystal cell increases as the liquid crystal cells far from the data driver 300 are driven, thereby lowering the brightness. In the method of dividing the display panel 100 into the first and second panel blocks PB1 and BP2 while the resolution of the display panel 100 is increased and scanning the first and second panel blocks PB1 and BP2 When the directions are the same, the first and second panel blocks PB1 and BP2 gradually decrease or increase the brightness along the same direction. As a result, when the first and second panel blocks PB1 and BP2 are scanned in the same direction, a dim phenomenon in block form occurs in the boundary region.

On the contrary, since the first and second panel blocks PB1 and BP2 are scanned in different directions, a dim phenomenon in block form occurs in the boundary region between the first and second panel blocks PB1 and BP2 Can be improved.

Further, the present invention can improve the occurrence of a line-dim phenomenon in several gate lines including a center gate line. Among the methods of scanning the first and second panel blocks PB1 and BP2 in different directions, as shown in FIG. 4, starting from the respective central gate lines located in the first and second panel blocks PB1 and BP2 When starting sequentially, the liquid crystal cells corresponding to the center gate line are charged first for each frame. Therefore, when the polarity control signal is inverted in one frame period, such as a column inversion or a Z-inversion, the center gate line is divided into a data voltage ADATA charged in the display period of the previous frame, The data voltage ADATA having the opposite polarity is charged. Accordingly, the data voltage ADATA input to the liquid crystal cells connected to the center gate line m / 2 of the first panel block PB1 is connected to the mth gate line GLm which is finally received in the previous frame The common voltage Vcom swings largely with respect to the liquid crystal cells. This ripple phenomenon causes a dim phenomenon in the horizontal line direction in the central gate line region.

On the other hand, since the display device of the present invention outputs the dummy data voltage during the vertical blank period, the period in which the data voltage ADATA swings to a large extent is shifted to the vertical blank period instead of the display period. Therefore, even if a ripple of the common voltage Vcom occurs, it is not a period for outputting the data voltage ADATA of the valid digital video data DATA, so that horizontal dimming can be prevented from occurring in the display period.

Since the dummy data voltage ADDATA changes the polarity of the data voltage ADATA in advance before the liquid crystal cells of the valid digital video data DATA are charged in the display period, It is possible to improve the filling of the lines.

5 is a schematic diagram showing a scanning method according to another embodiment using the liquid crystal display of FIG. Referring to FIG. 5, the scanning method according to the second embodiment scans the first panel block PB1 during the j-th frame period and the second panel block PB2 during the (j + 1) -th frame period . The gate driver 400 sequentially scans starting from the center gate line of the first panel block PB1. The gate driver 400 sequentially scans from the m / 2th gate line GL [m / 2] located in the first panel block PB1 to the first gate line GL1. The gate driver 400 sequentially applies the gate signal GL [(m / 2) +1] from the mth gate line GLm located at the second panel block PB2 to the [(m / 2) .

6 is a diagram showing a configuration of a display apparatus according to another embodiment of the present invention. In the embodiment of FIG. 6, substantially the same or substantially similar components as those of the embodiment of FIG. 1 described above are denoted by the same reference numerals, and a detailed description thereof will be omitted.

Referring to FIG. 6, a liquid crystal display according to another embodiment includes a liquid crystal display panel 101, a timing controller 201, data drivers 301 and 302, and a gate driver 401. The data driver 301 includes a plurality of source drive ICs. The gate driver 401 includes a plurality of gate driver ICs.

The liquid crystal display panel 101 includes first and second panel blocks PB1 and BP2 and the first and second panel blocks PB1 and BP2 are a TFT array substrate and a color filter array substrate And a liquid crystal layer formed between the TFT array substrate and the color filter array substrate. The first panel block PB1 includes m upper data lines DLT1 to DLTn and the second panel block PB2 includes m lower data lines DLB1 to DLBn.

The timing controller 201 generates a dummy data enable signal (DDE) in the vertical blanking period. The timing controller 201 can detect the vertical synchronization signal Vsync and the data enable signal DE and detect a constant section in which the data enable signal DE is not detected as the vertical blank period. The timing controller 200 generates a dummy data enable signal DDE during a predetermined period of time in the vertical blanking period and provides the dummy data enable signal DDE to the first and second data drivers 301 and 302. Also, the timing controller 200 provides the dummy data to the first and second data drivers 301 and 302 in response to the output of the dummy data enable signal DDE.

The data drivers 301 and 302 include first and second data drivers 301 and 302, respectively. The first data driver 31 includes the first to fourth source driver ICs SIC # 1 to SIC # 4 and is connected to the upper data lines DLT1 to DLTn formed in the first panel block PB1. And supplies the data voltage. The second data driver 32 includes the fifth to eighth source driver ICs SIC # 5 to SIC # 8 and is connected to the lower data lines DLB1 to DLBn formed in the second panel block PB2. And supplies the data voltage.

During the display period of the j frame period, the first and second data drivers 301 and 302 output the data voltage ADATA according to the digital video data DATA and the data enable signal of the input image. At this time, the first and second data drivers 301 and 302 output the first voltage level, for example, the negative data voltage ADATA by the polarity control signal POL provided from the timing controller 200. The first and second data drivers 301 and 302 output the dummy data voltage ADDATA based on the dummy data enable signal DDE and the dummy data DDATA in the vertical blanking period. At this time, the data driver 301 outputs a second voltage level, for example, a positive polarity data voltage ADATA, which is a voltage level opposite to the first voltage level, by the polarity control signal POL supplied from the timing controller 201 do.

The gate driver 400 independently scans the first and second panel blocks PB1 and BP2.

Referring to FIG. 7, the gate driver 401 drives the center gate line (m / 2) of the first panel block PB1 (m / 2) and the second gate line The central gate line [(m / 2) +1] of the panel block PB2 is simultaneously scanned. The first panel block PB1 is scanned in the direction of the first gate line GL1 and the second panel block PB2 is scanned in the direction of the mth gate line GLm.

The display device shown in Fig. 6 outputs a dummy data voltage ADDATA in the change period of the frame, thereby generating a dim phenomenon in the horizontal direction along the line for starting the scanning of the first and second panel blocks PB1 and BP2 Can be improved. Further, since the display device shown in Fig. 6 simultaneously scans the first and second panel blocks PB1 and BP2 while independently driving it, it is possible to secure a sufficient time for scanning one gate line.

8 is a view showing a scanning method of the display panel 101 according to another embodiment using the display device of FIG. As shown in FIG. 8, the gate driver 401 may change the gate line to be scanned first in the start section of the frame when the frame is changed, and reverse the scan direction. In other words. When the first gate line GL1 of the first panel block PB1 is scanned last in the jth frame, the (j + 1) th frame is transferred to the first gate line GL1 of the first panel block PB1 Scan first. Similarly, when the mth gate line GLm of the second panel block PB2 in the jth frame is scanned last, the (j + 1) th frame is transferred to the mth gate line GLm of the second panel block PB2, Is scanned first.

8, the position of the gate line at which ripple of the common voltage Vcom may occur can be changed by changing the gate line for starting scanning for each frame. That is, in the embodiment shown in FIG. 8, the region where the ripple of the common voltage Vcom is generated is changed in time by using the dummy data voltage, and the region where the ripple of the common voltage Vcom is generated is changed spatially do.

The above-described embodiments include an arrangement for inputting dummy data in a vertical blanking period before a frame starts. Dummy data DDATA generated by the timing controller 201 in the vertical blanking period in each of the embodiments can be obtained through the embodiment as shown in Figs. In Figs. 9 to 11, digital video data (DATA) and dummy data (DDATA) relatively represent a digital size.

As shown in Fig. 9, the timing controller 200 generates dummy data DDATA in the vertical blanking period adjacent to the display period, the same data as the digital video data (DATA) to be displayed in the start period of the display period. For example, if the dummy data DDATA is output during four horizontal periods of the vertical blanking period, the timing controller 201 outputs the digital video data DATA during the first to fourth horizontal periods 1H to 4H, Can be generated as dummy data DDATA.

10, the timing controller 201 generates a single average dummy data DDATA by averaging the digital video data DATA to be displayed in the start period of the display period, and outputs dummy data DDATA It is possible to output average dummy data (DDATA) in the output section.

Alternatively, as shown in Fig. 11, the timing controller 201 can output the dummy data DDATA gradually increasing in size in the section in which the dummy data DDATA is outputted gradually.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

A liquid crystal display panel in which a gate line and a data line are formed;
A gate driver for outputting a gate pulse to the gate line;
A timing controller for outputting a dummy data enable signal and dummy data within a vertical blanking period and outputting a data enable signal and digital video data during a display period; And
The digital video data is converted into a data voltage of a first polarity on the basis of the digital video data during a j-th (j is a natural number) frame period and is output to the data line, and the vertical blank period And a data driver for outputting a dummy data voltage of a second polarity opposite to the first polarity to the data line based on the dummy data enable signal and the dummy data.

The method according to claim 1,
Wherein the liquid crystal display panel includes first and second panel blocks,
Wherein the gate driver scans the second panel block after scanning the first panel block and sequentially scans the center gate line located at a boundary of the first and second panel blocks.

The method according to claim 1,
Wherein the liquid crystal display panel includes first and second panel blocks,
Wherein the gate driver independently scans the first and second panel blocks, and at least one of the panel blocks sequentially scans from a center gate line located at a boundary between the first and second panel blocks.

The method according to claim 2 or 3,
Wherein the gate driver changes the gate lines to be scanned at the beginning in the start period of the frame every predetermined frame interval.

The method according to claim 1,
Wherein the dummy data enable signal has the same pulse width as the data enable signal.