KR101641366B1 - Driving circuit for liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device for reducing power consumption and improving picture quality by applying a split inversion method, and more particularly to a driving apparatus for a liquid crystal display device in which pixels of odd- A liquid crystal panel including a second common voltage line connected thereto; First and second gate drivers driving odd-numbered gate lines and even-numbered gate lines of the liquid crystal panel, respectively; A common voltage supplier for supplying first and second common voltages of different levels to the first and second common voltage lines and inverting the levels of the first and second common voltages with respect to each frame; And each frame period is divided into first and second periods to drive any one of the gate drivers of the first and second gate drivers during the first period and drives the remaining one gate driver during the second period, And a timing controller for supplying image data inputted from outside according to a driving sequence of the first gate driver and the second gate driver to the data driver, wherein the data driver supplies the image signals of the first polarity to the data lines during the first period And supplies video signals of the second polarity different from the first polarity to the data lines during the second period.

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a liquid crystal display,

[0001] The present invention relates to a liquid crystal display (LCD), and more particularly, to a driving apparatus of a liquid crystal display apparatus capable of reducing display power consumption by performing a split inversion method, .

A liquid crystal display device displays an image using electrical and optical characteristics of a liquid crystal. Liquid crystals can have different anisotropic properties depending on the molecular axis and the direction of the short axis, such as refractive index and dielectric constant, and can easily control the molecular arrangement and optical properties. A liquid crystal display device using the same displays an image by changing the alignment direction of liquid crystal molecules according to the electric field size and adjusting the light transmittance transmitted through the polarizing plate.

The liquid crystal display device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the liquid crystal panel, and a data driver for driving the data lines of the liquid crystal panel.

In the liquid crystal display, an inversion driving method such as a frame inversion system, a line inversion system, and a dot inversion system is used to drive pixels of a liquid crystal panel . Among such inversion driving methods, the frame and line inversion methods can further reduce the power consumption as compared with the dot inversion method, and in the case of the dot inversion method, the image with higher image quality .

In recent years, the common voltage level supplied to each pixel of the liquid crystal panel is also inverted while adopting the line inversion or the frame inversion method, thereby improving the image quality while increasing the power consumption reduction effect.

However, although the data voltage supplied to each pixel is sequentially supplied from the first line to the last line of each frame, since the polarity of the common voltage is inverted every frame, the brightness characteristic of the display image is distorted Defects will occur. That is, since the polarity of the common voltage is inverted with the start of each frame, but the data voltage is sequentially supplied from the first line of every frame, the data voltage of the previous frame is charged, Ring phenomenon occurs. In this case, since the charged data voltage level changes, the brightness characteristic of the display image is distorted and a crosstalk phenomenon occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a driving apparatus for a liquid crystal display device which can improve display quality by preventing display defects of an image while reducing power consumption by performing split inversion It has its purpose.

According to an aspect of the present invention, there is provided an apparatus for driving a liquid crystal display, including a first common voltage line to which pixels of odd-numbered lines are connected in common, A liquid crystal panel including a first common voltage line; First and second gate drivers driving odd-numbered gate lines and even-numbered gate lines of the liquid crystal panel, respectively; A data driver for driving data lines of the liquid crystal panel; Supplying a first common voltage to the first common voltage line, supplying a second common voltage having a level different from the first common voltage to the second common voltage line, and outputting a level of the first and second common voltages, A common voltage supply unit for inverting each other; And each frame period is divided into first and second periods to drive any one of the gate drivers of the first and second gate drivers during the first period and drives the remaining one gate driver during the second period, 1 and the timing controller for supplying image data inputted from outside according to the driving sequence of the second gate driver to the data driver.
The data driver supplies the video signals of the first polarity to the data lines during the first period and the video signals of the second polarity different from the first polarity to the data lines during the second period.

The timing controller generates first and second gate control signals to supply the first and second gate drivers with the driving order of the first and second gate drivers, respectively, so that the driving order of the first and second gate drivers can be changed in units of frames.

The timing controller generates forward and backward directional control signals so that the driving directions of the first and second gate drivers can be switched forward or backward by at least one frame unit and outputs the forward and backward directional control signals together with the first and second gate control signals, And supplies them to the second gate driver.

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In the first period of the odd-numbered frame period, the timing controller sequentially supplies the video signals of the negative polarity to the pixels of the odd-numbered lines in the forward direction, and sequentially outputs the video signals in accordance with the difference voltage between the video signal and the first common voltage of the positive polarity level. And controls the first gate driver, the data driver, and the common voltage supply unit so as to be displayed.
The timing controller sequentially supplies video signals of positive polarity to the pixels of the second even-numbered lines in the odd-numbered frame period so that the video is sequentially displayed in accordance with the difference voltage from the second common voltage of the negative polarity 2 gate driver, a data driver, and a common voltage supply unit.
In the first period of the even-numbered frame period, the timing controller sequentially supplies the video signals of the negative polarity to the pixels of the even-numbered lines in the positive direction or the reverse polarity, so that the differential voltage between the negative polarity video signal and the second common voltage of the positive polarity And controls the second gate driver, the data driver, and the common voltage supply unit so that the image is sequentially displayed in accordance with the control signal.
In the second period of the even-numbered frame period, the timing controller sequentially supplies the positive-polarity video signals to the pixels of the odd-numbered lines in a forward direction so that the video is sequentially displayed in accordance with the difference voltage from the first common voltage of the negative polarity 1 gate driver, the data driver, and the common voltage supply unit.

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The driving apparatus for a liquid crystal display according to an embodiment of the present invention having the above-described features can improve the display quality by preventing the display failure of the image while reducing the power consumption by performing the split inversion method.

That is, it is possible to minimize the timing of the coupling phenomenon occurring due to the polarity inversion of the common voltage, thereby minimizing the distortion of the video signal due to the coupling phenomenon, and the video signal charging direction and the charging timing between the odd- The image quality of the display image can be further improved by reducing interference between adjacent pixel columns.

1 is a circuit diagram showing a driving apparatus for a liquid crystal display according to an embodiment of the present invention;
Fig. 2 is a configuration diagram more specifically showing the driving apparatus of the liquid crystal display shown in Fig. 1. Fig.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a driving apparatus for a liquid crystal display according to an embodiment of the present invention. FIG. 2 is a block diagram showing the driving apparatus of the liquid crystal display shown in FIG. 1 in more detail.

The driving apparatus of the liquid crystal display apparatus shown in Figs. 1 and 2 includes a liquid crystal panel 2 formed with a plurality of pixel regions; First and second gate drivers 6 and 7 for driving odd-numbered gate lines GL1 to GLn-1 and even-numbered gate lines GL2 to GLn in the direction of gate lines of the liquid crystal panel 2, ; A data driver 4 for driving a plurality of data lines DL1 to DLm provided in the liquid crystal panel 2; A common voltage supply unit for inverting and supplying the levels of the first common voltage Vcom1 supplied to the odd-numbered line pixel regions and the second common voltage Vcom2 supplied to the pixel regions of the even- (10); The first and second gate drivers 6 and 7 are driven alternately in every frame period and the first and second gate drivers 6 and 7 are driven in the order of the first and second gate drivers 6 and 7, And a timing controller 8 for aligning the image data RGB and supplying the image data RGB to the data driver 4.

The liquid crystal panel 2 includes a thin film transistor (TFT) and a thin film transistor (TFT) formed in each pixel region defined by odd and even gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, And a liquid crystal capacitor Clc connected to the liquid crystal capacitor Clc. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. At this time, the common lines are connected to the common electrodes of the odd-numbered lines to supply the common voltage to the respective common electrodes, and the second common voltage Vcom2 is applied to the common electrodes of the even- ) Are supplied. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the first or second common voltage supplied to the common electrode and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage Thereby implementing the gradation. At this time, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

2, the data driver 4 is provided between one side of the liquid crystal panel 2 and at least one of the source printed circuit boards 8a and 8b to drive the data lines DL1 to DLm And includes a plurality of data integrated circuits 4a and 4b. Each of the plurality of data integrated circuits 4a and 4b is mounted on the data circuit films 6a and 6b and connected between the liquid crystal panel 2 and one of the source printed circuit boards 8a and 8b.

Each of the data integrated circuits 4a and 4b includes a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, And converts the aligned data Data from the timing controller 8 into an analog voltage, that is, a video signal, using a source output enable (SOE) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the aligned data Data through the timing controller 8 in accordance with the SSC, and then, in response to the SOE signal, supplies the scan pulses to the gate lines GL1 to GLn And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period. At this time, the data driver 4 selects the positive or negative gamma voltage corresponding to the gradation value of the data Data arranged according to the negative signal from the timing controller 8, and outputs the selected gamma voltage as a video signal And supplies them to the respective data lines DL1 to DLm.

The first gate driver 6 may be formed on one side of the image non-display region of the liquid crystal panel 2 integrally with the liquid crystal panel 2, or may be provided on the other side of the liquid crystal panel 2 It is possible. The first gate driver 6 sequentially drives the odd-numbered gate lines GL1 to GLn-1 in the forward or reverse direction according to the first gate control signal GCS1 from the timing controller 8. [

Specifically, the first gate driver 6 receives a first gate control signal GCS1 from the timing controller 8, for example, a direction selection signal, a gate start signal GSP, a gate shift clock GSC Sequentially supplies a scan pulse or a gate low voltage to the odd-numbered gate lines GL1 to GLn-1 in the forward direction or the reverse direction by using gate shift clock (CLK), gate shift enable (GOE) .

Similarly, the second gate driver 7 may be formed on the other side of the image non-display area of the liquid crystal panel 2 integrally with the liquid crystal panel 2, or may be provided on the other side of the liquid crystal panel 2 . The second gate driver 7 sequentially drives the even-numbered gate lines GL2 to GLn in the forward direction or the reverse direction in accordance with the second gate control signal GCS2 from the timing controller 8. [

The common voltage supply unit 10 supplies the first common voltage Vcom1 supplied to the pixel regions of the odd-numbered lines and the second common voltage Vcom2 supplied to the pixel regions of the even-numbered lines, under the control of the timing controller 2. [ Vcom2 are inverted in units of the first frame and the second frame in each frame period.

In other words, the common voltage supply unit 10 inverts the levels of the first common voltage Vcom1 and the second common voltage Vcom2 every frame, or inverts the levels of the first common voltage Vcom1 and the second common voltage Vcom2 in the first period (for example, , A timing at which one of the gate drivers of the first or second gate driver is driven first) and a second period (for example, a timing at which the gate driver of the remaining one of the first or second gate drivers is driven Timing). For example, the common voltage supply unit 10 supplies the first common voltage Vcom1 to the 5V voltage (+) level in the first period, which is the start timing of one frame period, under the control of the timing controller 2 And the second common voltage Vcom2 can be supplied at a level of 0V (-) in a second period which is an intermediate period of one frame. In this case, the second common voltage Vcom2 is converted and supplied to the 5V voltage (+) level in the first period of the next frame period, and the first common voltage Vcom1 is set to the 0V voltage (-) level during the second period Can be changed and supplied.

The timing controller 8 may be provided on a separate control printed circuit board or may be provided on one of the at least one source printed circuit boards 8a and 8b to output image data RGB and a plurality of synchronization signals DCLK The data driver 4, and the first and second gate drivers 6 in accordance with the control signals Vsync, Vsync, Vsync, and DE.

Specifically, the timing controller 8 arranges image data (RGB) input from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data driver 4. The first and second gate control signals GCS1 and GCS2 are generated using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync. And GCS2 and a data control signal DCS to the first and second gate drivers 6 and 7 and the data driver 4, respectively.

At this time, the timing controller 8 is configured to alternately drive the first and second gate drivers 6 and 7 in every frame period, but also to drive the first and second gate drivers 6 and 7 The first and second gate control signals GCS1 and GCS2 are generated and supplied so that the first and second gate control signals GCS1 and GCS2 can be changed from frame to frame. For example, if the GSP is first supplied to the first gate driver 6 at the start timing of one frame and then all the scan pulses are supplied to the odd-numbered gate lines GL1 to GLn-1, It is possible to sequentially drive the first and second gate drivers 6 and 7 by supplying them to the driver 7. [ When all the scan pulses are supplied to the even-numbered gate lines GL2 to GLn after the GSP is first supplied to the second gate driver 7 at the start timing of the next frame, the GSP is again supplied to the first gate driver 6 So that the order of the first and second gate drivers 6 and 7 can be changed and driven.

At this time, the timing controller 8 sequentially arranges the image data (RGB) so as to correspond to the driving sequence of the first and second gate drivers 6 and 7, and sequentially supplies the image data RGB to the data driver 4.

On the other hand, the timing controller 8 controls the first and second gate drivers 6 and 7 so that the driving direction of the first and second gate drivers 6 and 7 can be changed in the forward direction or the reverse direction by at least one frame unit, And second gate control signals (GCS1, GCS2). For example, the GSP is first supplied to the first gate driver 6 together with the forward control signal at the start timing of one frame, and then all the scan pulses are supplied to the odd gate lines GL1 to GLn-1 in the forward direction The GSP is supplied to the second gate driver 7 together with the backward control signal so that the scan pulses are supplied to the even-numbered gate lines GL2 to GLn in the reverse direction. Of course, if the GSP is first supplied to the first gate driver 6 together with the backward control signal at the start timing of one frame and then all of the scan pulses are supplied to the odd-numbered gate lines GL1 to GLn-1 in the reverse direction The scan pulse may be supplied to the even-numbered gate lines GL2 to GLn in the forward direction by supplying the GSP to the second gate driver 7 together with the forward control signal.

At this time, the timing controller 8 controls the timing of driving the first and second gate drivers 6 and 7 and the image data RGB to correspond to the driving directions of the first and second gate drivers 6 and 7, And supplies the data to the data driver 4 sequentially.

The timing controller 8 supplies the direction control signal and the inversion signal (Pol Signal) to the common voltage supply unit 10 so that the common voltage supply unit 10 supplies the odd-numbered and even- So that the common voltage Vcom1 and the second common voltage Vcom2 are inverted and supplied. Then, the GSP and the corresponding control signal are supplied to the common voltage supply unit 10 at the timing when the GSP is supplied to the first and second gate drivers, respectively, so that the first period or the second period, which is the start period of each frame period, The level of the first common voltage Vcom1 or the level of the second common voltage Vcom2 may be inverted and supplied.

The driving method of the liquid crystal display according to the present invention will be described in more detail with reference to Tables 1 and 2 below.

Table 1 and Table 2 show the relationship between the number of pixels of odd-numbered pixel columns (Odd Line) and the number of pixels of even-numbered pixel columns (Even Line) in an odd frame period (N Frame) The drive sequence of the regions and the drive voltage level.

First, referring to Table 1, in the odd-numbered pixel column (Odd Line) driving period of the first period of the odd-numbered frame period (N Frame), that is, the odd-numbered frame period (N Frame) The first gate driver 6 sequentially drives the odd gate lines GL1 through GLn-1 in the forward direction and the data driver 4 sequentially drives the odd-numbered video signals (- The common voltage supply unit 10 applies the first common voltage (+ V) of positive polarity (+) V to the pixel regions of the odd-numbered pixel column (Odd Line) Vcom1.

That is, in the first period of one frame (N frame) period, the timing controller 8 sequentially supplies the video signals (-) data of negative polarity in the pixel regions of odd-numbered pixel columns (Odd Line) The data driver 4, and the common voltage supply unit 10 are sequentially arranged so as to sequentially display an image according to the difference voltage between the first common voltage Vcom1 and the first common voltage Vcom1 at the positive polarity level ((+)) .

Next, referring to Table 2, the second gate driver 7 is controlled in accordance with the control of the timing controller 8 in the second period of the one frame (N Frame) period, that is, the even- The data driver 4 sequentially drives the even-numbered gate lines GL2 to GLn in the reverse direction and the data driver 4 sequentially applies the positive-polarity video signal (+) data to the pixel regions of the even- The common voltage supply unit 10 supplies the second common voltage Vcom2 of the negative level (- (V)) to the pixel regions of the even-numbered pixel column (Odd Line).

That is, in the second period of one frame (N frame) period, the timing controller 8 sequentially supplies the positive video signals (+) data to the pixel regions of the even-numbered pixel columns (Even Line) The data driver 4 and the common voltage supply unit 10 are controlled so as to sequentially display an image in accordance with the difference between the first common voltage Vcom2 and the second common voltage Vcom2 at the polarity level (- (-) V) do.

On the other hand, Tables 3 and 4 show the pixel regions of the odd-numbered pixel columns (Odd Line) and the pixel columns of the even-numbered pixels (N + 1 frame) in the next frame period Even Line) and the drive voltage level of the pixel regions.

Referring to Tables 3 and 4, in the first period of the even-numbered frame period (N + 1 Frame), the timing controller 8 counts the number of pixels in the even-numbered pixel column (Even Line) (-) data of a negative polarity level (+) V and a negative common voltage Vcom2 of a negative polarity video signal (- The data driver 4, and the common voltage supply unit 10 so that the image is sequentially displayed according to the differential voltage between the first gate driver 7, the data driver 4, and the common voltage supplier 10.

The timing controller 8 supplies the positive video signal (+) data to the pixel regions of the odd-numbered pixel column (Odd Line) in the second period of the even-numbered frame period (N + The data driver 4 and the common voltage supply unit 10 (not shown) so that the video is sequentially displayed in accordance with the difference voltage between the first common voltage Vcom1 and the first common voltage Vcom1 of the negative polarity level ).

As described above with reference to Tables 1 to 4, in the present invention, the timing at which the coupling phenomenon can occur according to the polarity inversion of the first and second common voltages Vcom1 and Vcom2 is minimized, Distortion of the video signal ((+, -) data) can be minimized. Further, by reducing the interference between adjacent pixel columns by varying the charging direction and charging timing of the video signal ((+, -) data) between odd-numbered pixel rows (Odd Line) and even-numbered pixel columns (Even Line) Can be improved.

Meanwhile, Tables 5 and 6 show different driving procedures and drive voltage levels of odd-numbered pixel column (Odd Line) pixel regions and even-numbered pixel column (Even Line) pixel regions in one frame (N frame) period.

First, referring to Table 5, in the first period of a frame period (N Frame), the timing controller 8 outputs a negative video signal (-) data to the pixel regions of the odd-numbered pixel column (Odd Line) The data driver 4, and the common voltage Vcom1 are sequentially displayed in accordance with the difference voltage between the first common voltage Vcom1 and the first common voltage Vcom1 of the positive polarity level (+ And controls the voltage supply unit 10.

This is the same as the drive sequence and drive voltage level of the odd-numbered pixel row (odd line) pixel regions described in Table 1. [

However, referring to Table 6, in the second period of one frame period (N Frame), the timing controller 8 supplies the positive video signal (+) to the pixel regions of the even- the data driver 4 and the common voltage Vcom2 are sequentially displayed in accordance with the differential voltage between the first common voltage Vcom2 and the second common voltage Vcom2 of the negative polarity level The voltage supply unit 10 can be controlled.

That is, in the first or second period of a frame period (N frame), pixel regions of an odd line (Odd Line) or an even line (Even Line) are driven in the same direction, It is possible to minimize the distortion of the video signal ((+, -) data) due to the coupling phenomenon by minimizing the timing at which the coupling phenomenon can occur according to the polarity inversion of the two common voltages Vcom1 and Vcom2. Further, by reducing the interference between adjacent pixel columns by varying the charging direction and charging timing of the video signal ((+, -) data) between odd-numbered pixel rows (Odd Line) and even-numbered pixel columns (Even Line) Can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

2: liquid crystal panel 4: data driver
4a and 4b: data integrated circuits 6a and 6b: printed circuit film
8a, 8b: printed circuit board 6: first gate driver
7: second gate driver 8: timing controller
10: Common voltage supply part

Claims (10)

A liquid crystal panel including a first common voltage line to which pixels of odd-numbered lines are connected in common and a second common voltage line to which pixels of even-numbered lines are commonly connected;
A first gate driver for driving odd gate lines of the liquid crystal panel;
A second gate driver for driving even-numbered gate lines of the liquid crystal panel;
A data driver for driving data lines of the liquid crystal panel;
And supplies a second common voltage having a level different from that of the first common voltage to the second common voltage line, and supplies the first common voltage to the first common voltage line A common voltage supply unit for inverting the levels of the voltages with respect to each other; And
Each frame period is divided into first and second periods to drive any one of the gate drivers of the first and second gate drivers during the first period and to drive the remaining one gate driver during the second period And a timing controller for aligning image data inputted from outside according to a driving sequence of the first and second gate drivers and supplying the same to the data driver,
Wherein the data driver supplies the video signals of the first polarity to the data lines during the first period and supplies the video signals of the second polarity different from the first polarity to the data lines during the second period, A driving device for a display device. The method according to claim 1,
The timing controller
A gate driver for driving the first and second gate drivers to generate the first and second gate control signals so that the driving order of the first and second gate drivers can be switched in units of frames, . 3. The method of claim 2,
The timing controller
And generates forward and backward directional control signals so that the driving directions of the first and second gate drivers can be switched forward or backward in units of at least one frame to generate first and second gate control signals together with the first and second gate control signals, And supplies the second gate driver to the second gate driver. delete The method of claim 3,
The timing controller
During the first period of the odd-numbered frame period, the video signals of the negative polarity are sequentially supplied to the pixels of the odd-numbered lines, and the video signals are sequentially supplied to the pixels of the odd- And controls the first gate driver, the data driver, and the common voltage supply unit so as to be displayed,
Numbered lines are sequentially supplied to the pixels of the even-numbered lines in the positive or negative direction and the video signals are sequentially supplied to the pixels of the odd-numbered lines in the second period, The second gate driver, the data driver, and the common voltage supply unit,
In the first period of the even-numbered frame period, the video signals of the negative polarity are sequentially supplied to the pixels of the even-numbered lines in a forward or reverse direction to generate a difference between the video signal of the negative polarity and the second common voltage of the positive polarity level Controls the second gate driver, the data driver, and the common voltage supply unit so that an image is sequentially displayed according to a voltage,
Numbered lines in the second period of the even-numbered frame period so that the video signals are sequentially supplied to the pixels of the odd-numbered lines in the positive direction and the first common voltage of the negative level, The first gate driver, the data driver, and the common voltage supply unit. delete delete delete delete delete

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