KR101777130B1 - Driving circuit for liquid crystal display device - Google Patents

Abstract

The present invention relates to a driving apparatus for a liquid crystal display device capable of reducing a power consumption by inverting a common voltage level supplied to a liquid crystal panel and preventing a luminance difference from occurring between the upper and lower ends of the liquid crystal panel, A liquid crystal panel having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels; A gate driver for driving gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels; A data driver for driving data lines of the liquid crystal panel; And a timing controller for supplying the video data to the data driver and generating the gate and data control signals to control the gate and the data driver, respectively.

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a liquid crystal display,

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of reducing a power consumption by inverting a common voltage level supplied to a liquid crystal panel and preventing a luminance difference between the upper and lower ends of the liquid crystal panel, To a driving apparatus for a liquid crystal display apparatus.

A liquid crystal display device displays an image using electrical and optical characteristics of a liquid crystal. Liquid crystals can have different anisotropic properties depending on the molecular axis and minor axis direction, such as refractive index and dielectric constant, and can easily control the molecular arrangement and optical properties. A liquid crystal display device using the same displays an image by changing the alignment direction of liquid crystal molecules according to the electric field size and adjusting the light transmittance transmitted through the polarizing plate.

The liquid crystal display device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the liquid crystal panel, and a data driver for driving the data lines of the liquid crystal panel.

In the liquid crystal display, an inversion driving method such as a frame inversion system, a line inversion system, and a dot inversion system is used to drive pixels of a liquid crystal panel . Among such inversion driving methods, the frame and line inversion methods can further reduce the power consumption as compared with the dot inversion method, and in the case of the dot inversion method, the image with higher image quality .

In recent years, the common voltage level supplied to each pixel of the liquid crystal panel is also inverted while adopting the line inversion or the frame inversion method, thereby improving the image quality while increasing the power consumption reduction effect.

However, although the data voltage supplied to each pixel is sequentially supplied from the first line to the last line of each frame, since the polarity of the common voltage is inverted every frame, the brightness characteristic of the display image is distorted Defects will occur. That is, since the polarity of the common voltage is inverted with the start of each frame, but the data voltage is sequentially supplied from the first line of every frame, the data voltage of the previous frame is charged, Ring phenomenon occurs. In this case, since the charged data voltage level changes, a luminance difference occurs between the upper and lower ends of the display panel, and image quality defects such as a crosstalk phenomenon occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a liquid crystal display device capable of reducing the power consumption by inverting the common voltage level supplied to the liquid crystal panel and preventing a luminance difference between the upper and lower ends of the liquid crystal panel, And to provide a driving apparatus for a liquid crystal display device.

According to an aspect of the present invention, there is provided a driving apparatus for a liquid crystal display, including: a liquid crystal panel having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels; A gate driver for driving gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels; A data driver for driving data lines of the liquid crystal panel; And a timing controller for supplying the video data to the data driver and generating the gate and data control signals to control the gate and the data driver, respectively.
The voltage level of the gate low voltage is changed at the beginning of each frame in every frame and the gate low voltage supplied to the gate lines during one frame period is the same.

The gate driver sequentially supplies the scan pulse of the gate high voltage level to each gate line in accordance with the gate control signal and supplies the gate low voltage of the third voltage level or the gate of the fourth voltage level The low voltage is alternately supplied every frame.

The gate low voltages of the third or fourth voltage level are alternately supplied with the scan pulses in odd-numbered or even-numbered frame periods so as to correspond to the common voltage supply timing swinging at the first or second voltage level, respectively And supplied to each gate line in the remaining period.

In the frame period in which the common voltage of the first voltage level is supplied to the respective pixel regions at the negative voltage level, the gate low voltage of the third voltage level, which is lower than the negative common voltage of the first voltage level, And a common voltage of a second voltage level is supplied to each of the pixel regions at a positive polarity level, a gate low voltage of a fourth voltage level lower than the positive common voltage of the second voltage level And supplied to each gate line in the remaining period in which this scan pulse is not supplied.

The voltage widths between the third and fourth level gate low voltages are set to swing with a width equal to the voltage width between the common voltages of the first and second voltage levels.

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The driving apparatus for a liquid crystal display according to an embodiment of the present invention having such characteristics as described above can reduce the power consumption by inverting the common voltage level supplied to the liquid crystal panel. In addition, it is possible to prevent defects such as a difference in brightness between the upper and lower ends of the liquid crystal panel and the occurrence of a crosstalk phenomenon, thereby further improving the display quality of the image.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a circuit diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention; FIG.
Fig. 2 is a circuit diagram showing one pixel region of the liquid crystal panel shown in Fig. 1. Fig.
3 is a waveform chart for describing the driving method of the liquid crystal panel shown in Fig.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a driving apparatus for a liquid crystal display according to an embodiment of the present invention. 2 is a circuit diagram showing one pixel region of the liquid crystal panel shown in Fig.

The driving apparatus of the liquid crystal display shown in FIG. 1 includes a liquid crystal panel 2 having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels; A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2 with scan pulses having a gate low voltage and a gate high voltage swinging at the third and fourth voltage levels; A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; And the image data RGB inputted from outside are supplied to the data driver 4 and the gate and data control signals GCS and DCS are generated to control the gate and the data drivers 6 and 4 And a timing controller 8.

1 and 2, a liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, Transistor and a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. At this time, the common voltage of the first and second voltage levels is supplied to the common electrode of each pixel region by swinging every frame. On the other hand, the TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage at the first or second voltage level and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage, . At this time, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line interposed therebetween, and a parasitic capacitor Cgs may be further formed between the source electrode of the TFT and the gate line GL.

A common voltage of a first level or a common voltage of a second level is alternately supplied to each pixel region of the liquid crystal panel 2 by a common voltage supply unit (not shown) every frame. For example, in the odd frame period, the negative common voltage (-) of the first voltage level is supplied to each pixel region, and in the even frame period, the positive common voltage (+) of the second voltage level is supplied to each pixel Regions. ≪ / RTI > At this time, the positive voltage (+) of the second voltage level is supplied at the positive voltage level (+) of 5V in the odd frame period and the negative voltage (-) of the first voltage level is supplied in the even frame period 0V. ≪ / RTI >

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, a source output enable That is, a video signal, from the timing controller 8 using a source output enable (SOE) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the aligned data Data through the timing controller 8 in accordance with the SSC, and then, in response to the SOE signal, supplies the scan pulses to the gate lines GL1 to GLn And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period. At this time, the data driver 4 selects the positive or negative gamma voltage corresponding to the gradation value of the data Data arranged according to the negative signal from the timing controller 8, and outputs the selected gamma voltage as a video signal And supplies them to the respective data lines DL1 to DLm.

The gate driver 6 sequentially drives the gate lines GL1 to GLn in accordance with the gate control signal GCS from the timing controller 8. [ Specifically, the gate driver 4 outputs a gate start signal (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal Or the like so that the scan pulses of the gate high voltage (VGH) level are sequentially supplied to the gate lines GL1 to GLn. In addition, during the remaining periods when the scan pulse is not supplied, the gate-low voltage VGL1 of the third level or the gate-low voltage VGL2 of the fourth voltage level is alternately supplied every frame.

The gate low voltages VGL1 and VGL2 of the third or fourth voltage level are alternately scanned with each other in units of odd or even frame periods so as to correspond to the common voltage supply timing of the first or second voltage level, And supplied to the respective gate lines GL1 to GLn in the remaining period in which pulses are not supplied. The method of supplying the gate-low voltages VGL1 and VGL2 will be described later in detail with reference to the accompanying drawings.

On the other hand, the timing controller 8 includes a common voltage supply unit (not shown) according to external video data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync, (6). Specifically, the timing controller 8 arranges image data (RGB) input from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data driver 4. A gate control signal GCS and a data control signal GCS are generated by using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync DCS, and supplies them to the gate driver 6 and the data driver 4, respectively. At this time, the timing controller 8 supplies an inversion signal (Pol Signal) to a common voltage supply unit (not shown) and the gate driver 6, respectively. That is, the timing controller 8 controls the common voltage supply unit to invert the level of the common voltage Vcom every frame unit through the inversion signal, and controls the gate driver 6 to supply the third Or the gate-low voltages VGL1 and VGL2 of the fourth level to the gate lines GL1 to GLn. On the other hand, according to the common voltage (Vcom) supply structure of the first or second level of each pixel region formed in the liquid crystal panel 2, the timing controller 8 supplies each pixel region with a column inversion ) Method, a frame-inversion method, or a dot-inversion method.

3 is a waveform diagram for describing the driving method of the liquid crystal panel shown in Fig.

3 illustrates a method of driving the first pixel region included in the first horizontal lines disposed at the uppermost position of the liquid crystal panel 2 and a method of driving the first pixel region included in the last horizontal line disposed at the lowermost position of the liquid crystal panel 2 A driving waveform diagram for explaining a driving method of the included n-th pixel region is shown.

The polarity of the common voltage Vcom at the first and second voltage levels is reversed at the start of each frame in every frame and the video signal Vpixel is synchronized with the scan pulse VGH So that each pixel region is sequentially supplied from the first horizontal line of each frame. Accordingly, in the case of the horizontal lines disposed at the lower end of the liquid crystal panel 2, although the video signal Vpixel of the previous frame is charged, the inverted common voltage Vcom in the current frame is supplied to the video signal Vpixel The polarity of the common voltage Vcom becomes equal.

A method of driving the liquid crystal panel 2 according to an embodiment of the present invention will now be described. In the odd-numbered frame period of each frame period, a negative common voltage of a first voltage level is applied to each pixel region of the liquid crystal panel 2 (-) may be supplied to each pixel region, and a positive common voltage (+) of a second voltage level may be supplied to each pixel region in an even-numbered frame period.

In this case, each of the gate-low voltages VGL1 and VGL2 of the third or fourth voltage level is divided into odd-numbered or even-numbered frame periods so as to correspond to the common voltage supply timing of the first or second voltage level And are supplied to the gate lines CL1 to GLn in the remaining periods in which the scan pulses are not alternately supplied to each other.

In other words, in the odd frame period in which the negative common voltage (-) of the first voltage level is supplied to the respective pixel regions, the gate low voltage of the third voltage level lower than the negative common voltage (-) of the first voltage level (VGL2) is supplied to each gate line (GL1 to GLn) during the remaining period in which the scan pulse is not supplied, and in the even-numbered frame period in which the positive common voltage (+) of the second voltage level is supplied to each pixel region The gate low voltage VGL1 of the fourth voltage level lower than the positive common voltage (+) of the second voltage level can be supplied to each gate line GL1 to GLn in the remaining period in which no scan pulse is supplied.

3, the voltage width between the third and fourth level gate low voltages VGL1 and VGL2 is equal to the voltage width between the common voltage Vcom of the first and second voltage levels Can be set to swing. That is, the swing supply timing of the common voltage Vcom of the first and second voltage levels is made equal to the swing supply timing of the gate low voltages VGL1 and VGL2 of the third and fourth levels, The voltage width between the voltage level between the gate-low voltages VGL1 and VGL2 of the fourth level and the common voltage Vcom between the first and second voltage levels is maintained to be the same and is generated by the parasitic capacitor Cgs of each pixel region The voltage difference can be minimized.

When the voltage widths between the third and fourth level gate low voltages VGL1 and VGL2 and the common voltage Vcom between the first and second voltage levels are kept equal at the same timing, As shown, the voltage difference produced by the parasitic capacitors Cgs in each pixel region can be minimized.

In other words, when the voltage width (? Vcom) between the swinging gate low voltage (VGL1, VGL2) and the swinging common voltage (Vcom) is the same, the parasitic capacitor Ggs ) Approaches zero.

Accordingly, the common voltage polarity is inverted at the beginning of each frame in units of frames, and even if the video signal is sequentially supplied from the first horizontal line of each frame, the coupling phenomenon due to the change in the common voltage polarity can be minimized. Particularly, the coupling phenomenon caused by the parasitic capacitor Ggs is minimized also at the lower end of the liquid crystal panel 2, so that a luminance difference does not occur between the upper and lower ends of the liquid crystal panel 2.

On the other hand, as described above, when the gate-low voltages VGL1 and VGL2 of the third and fourth voltage levels are alternately supplied, the voltage level of the video signal is always kept higher than the gate-low voltages VGL1 and VGL2 The difference in luminance between the upper and lower ends due to the leakage current of the TFT can also be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

A liquid crystal panel having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels;
A gate driver for driving the gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels;
A data driver for driving data lines of the liquid crystal panel;
And a timing controller for supplying video data to the data driver and generating a gate and a data control signal to control the gate and the data driver, respectively,
The common voltage polarities of the first and second voltage levels are inverted at the start of each frame in units of frames and the plurality of pixel regions are supplied with the inverted common voltage in the current frame, The polarity is the same,
The voltage level of the gate low voltage is changed at the beginning of each frame in units of frames, and the gate low voltage supplied to the gate lines during one frame period is the same. The method according to claim 1,
The gate driver
Sequentially supplying a scan pulse of a gate high voltage level to each of the gate lines in accordance with the gate control signal,
And supplies the gate-low voltage of the third voltage level or the gate-low voltage of the fourth voltage level alternately in units of frames every remaining period during which the scan pulse is not supplied. 3. The method of claim 2,
Each of the gate low voltages of the third or fourth voltage level
Which is supplied to each of the gate lines in a remaining period in which the scan pulse is not alternately supplied to the gate lines in odd-numbered or even-numbered frame periods so as to correspond to the common voltage supply timing for swinging at the first or second voltage level, A driving device for a display device. The method of claim 3,
A gate low voltage of a third voltage level lower than the negative common voltage of the first voltage level is applied to the pixel regions in a period in which the common voltage of the first voltage level is supplied to the pixel regions with a negative voltage level, Is supplied to each of the gate lines during the remaining period in which the gate line is not supplied,
A gate low voltage of a fourth voltage level lower than the positive common voltage of the second voltage level is applied to the pixel regions during a period in which the common voltage of the second voltage level is supplied to the pixel regions with a positive polarity level, And the gate lines are supplied to the gate lines during the remaining periods during which the gate lines are not supplied. 5. The method of claim 4,
The voltage width between the third and fourth levels of the gate-low voltage is
And swing at a width equal to the voltage width between the common voltages of the first and second voltage levels. delete delete delete delete delete

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