KR20120116682A - Driving circuit for liquid crystal display device and method for driving the same - Google Patents

Abstract

PURPOSE: A device and method for driving a liquid crystal display device are provided to reduce power consumption by inverting a common voltage level supplied to a liquid crystal panel. CONSTITUTION: A liquid crystal panel(2) includes a plurality of pixel areas. A gate driver(6) drives gate lines of the liquid crystal panel. A data driver(4) drives data lines of the liquid crystal panel. A timing controller(8) supplies image data to the data driver. The timing controller respectively controls the gate driver and data driver by generating a gate control signal and a data control signal. [Reference numerals] (4) Data driver; (6) Gate driver; (8) Timing controller

Description

DRIVING CIRCUIT FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and in particular, by inverting the common voltage level supplied to the liquid crystal panel to reduce the power consumption while preventing the luminance difference between the upper and lower ends of the liquid crystal panel to improve display image quality. A driving device of a liquid crystal display device and a driving method thereof.

The liquid crystal display displays an image by using electrical and optical characteristics of the liquid crystal. Liquid crystals have different anisotropy in refractive index, dielectric constant, etc. according to molecular long axis direction and short axis direction, and can easily adjust molecular arrangement and optical properties. The liquid crystal display using the same displays an image by adjusting the light transmittance through the polarizing plate by changing the arrangement direction of the liquid crystal molecules according to the size of the electric field.

The liquid crystal display includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix, a gate driver driving a gate line of the liquid crystal panel, a data driver driving a data line of the liquid crystal panel, and the like.

In the liquid crystal display, inversion driving methods such as a frame inversion system, a line inversion system, and a dot inversion system are used to drive the pixels of the liquid crystal panel. . Among the inversion driving methods, the frame and line inversion methods can further reduce power consumption compared with the dot inversion method. In the case of the dot inversion method, an image of higher quality than the frame and line inversion methods can be obtained. To provide.

In recent years, while applying the line inversion or frame inversion method, the common voltage level supplied to each pixel of the liquid crystal panel is also inverted, thereby improving the power consumption and improving image quality.

However, despite the fact that the data voltage supplied to each pixel is sequentially supplied from the first line to the last line of every frame, the polarity of the common voltage is inverted every frame so that the brightness characteristics of the display image are distorted. Defects will occur. That is, since the polarity of the common voltage is inverted at the beginning of every frame, but the data voltage is sequentially supplied from the first line of every frame, the data voltage of the previous frame is charged and the pixels are coupled with the change of the common voltage polarity. Ring phenomenon will occur. In this case, since the data voltage level being charged changes, a luminance difference occurs between the upper and lower ends of the display panel, and a poor image quality such as a crosstalk phenomenon occurs.

The present invention is to solve the above problems, while reducing the power consumption by inverting the common voltage level supplied to the liquid crystal panel while preventing the luminance difference between the upper and lower ends of the liquid crystal panel can be improved display quality It is an object of the present invention to provide a driving device and a driving method thereof for a liquid crystal display.

According to an aspect of the present invention, there is provided a driving apparatus of a liquid crystal display device including: a liquid crystal panel having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels; A gate driver for driving the gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels; A data driver for driving data lines of the liquid crystal panel; And a timing controller for aligning and supplying image data input from the outside to the data driver, generating a gate and data control signal, and controlling the gate and data driver, respectively.

The gate driver sequentially supplies scan pulses having a gate high voltage level to each gate line according to the gate control signal, and gate low voltage or the gate voltage of the third voltage level during the remaining periods when the scan pulses are not supplied. The gate low voltage of the fourth voltage level is alternately supplied every frame.

Each of the gate low voltages of the third or fourth voltage level alternates the scan pulses in odd or even frame periods so as to correspond to a common voltage supply timing swinging to the first or second voltage level, respectively. Is supplied to each of the gate lines in the remaining period in which is not supplied.

In a frame period in which the common voltage of the first voltage level is supplied to the pixel regions at the negative voltage level, the gate low voltage of the third voltage level lower than the negative common voltage of the first voltage level is applied to the scan pulse. It is supplied to each of the gate lines in the remaining periods which are not supplied, and in a frame period in which the common voltage of the second voltage level is supplied to the pixel regions at the positive polarity level, it is lower than the positive common voltage of the second voltage level. The gate low voltage of the fourth voltage level is supplied to each of the gate lines in the remaining period during which the scan pulse is not supplied.

The voltage width between the gate low voltages of the third and fourth levels may be set to swing at the same width as the voltage width between the common voltages of the first and second voltage levels.

In addition, the driving method of the liquid crystal display according to the embodiment of the present invention for achieving the above object comprises the steps of supplying a common voltage swinging at the first and second voltage levels to each pixel area of the liquid crystal panel; Driving gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels; Driving data lines of the liquid crystal panel; Generating gate and data control signals to control the gate and data drivers, respectively.

In the driving of the gate lines, scan pulses having a gate high voltage level are sequentially supplied to the gate lines according to the gate control signal, and gates of the third voltage level are provided for the remaining periods when the scan pulses are not supplied. The low voltage or the gate low voltage of the fourth voltage level is alternately supplied every frame.

Each of the gate low voltages of the third or fourth voltage level alternates the scan pulses in odd or even frame periods so as to correspond to a common voltage supply timing swinging to the first or second voltage level, respectively. Is supplied to each of the gate lines in the remaining period in which is not supplied.

In a frame period in which the common voltage of the first voltage level is supplied to the pixel regions at the negative voltage level, the gate low voltage of the third voltage level lower than the negative common voltage of the first voltage level is applied to the scan pulse. It is supplied to each of the gate lines in the remaining periods which are not supplied, and in a frame period in which the common voltage of the second voltage level is supplied to the pixel regions at the positive polarity level, it is lower than the positive common voltage of the second voltage level. The gate low voltage of the fourth voltage level is supplied to each of the gate lines in the remaining period during which the scan pulse is not supplied.

The voltage width between the gate low voltages of the third and fourth levels may be set to swing at the same width as the voltage width between the common voltages of the first and second voltage levels.

The driving apparatus and driving method thereof of the liquid crystal display according to the exemplary embodiment of the present invention having the above-described characteristics can reduce power consumption by inverting the common voltage level supplied to the liquid crystal panel. In addition, the display quality of the image may be further improved by preventing a defect such as a luminance difference between the upper and lower ends of the liquid crystal panel and a defect such as a crosstalk phenomenon.

1 is a circuit diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating one pixel area of the liquid crystal panel shown in FIG. 1. FIG.
3 is a waveform diagram for clarifying a driving method of the liquid crystal panel shown in FIG.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration circuit diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention. 2 is a circuit diagram illustrating one pixel area of the liquid crystal panel illustrated in FIG. 1.

1 includes a liquid crystal panel 2 having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels; A gate driver 6 driving the gate lines GL1 to GLn of the liquid crystal panel 2 with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels; A data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2; And aligning and supplying image data RGB inputted from the outside to the data driver 4, and generating gate and data control signals GCS and DCS to control the gate and data drivers 6 and 4, respectively. The timing controller 8 is provided.

1 and 2, the liquid crystal panel 2 includes a thin film transistor TFT formed in each pixel area defined by a plurality of gate lines GL1 through GLn and a plurality of data lines DL1 through DLm. And a liquid crystal capacitor (Clc) connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode disposed with the pixel electrode and the liquid crystal interposed therebetween. In this case, the common voltages of the first and second voltage levels are supplied to the common electrode of each pixel area in every frame unit. On the other hand, the TFT supplies the image signals from the respective data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the respective gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage of the first or second voltage level, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. Implement In this case, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween, and a parasitic capacitor Cgs may be further formed between the source electrode and the gate line GL of the TFT.

Each pixel area of the liquid crystal panel 2 is alternately supplied with a common voltage of a first level or a common voltage of a second level by a common voltage supply unit (not shown). For example, a negative common voltage (−) of a first voltage level is supplied to each pixel region in an odd frame period, and a positive common voltage (+) of a second voltage level is supplied to each pixel in an even frame period. May be supplied to the areas. At this time, the positive voltage (+) of the second voltage level is supplied at the 5V voltage (+) level of the positive level in the odd frame period, and the negative voltage (-) of the first voltage level is supplied in the even frame period. Can be supplied at 0V.

The data driver 4 includes a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, and a source output enable signal. The SOE (Source Output Enable) signal, the inversion signal (Pol signal), and the like are used to convert the data Data aligned from the timing controller 8 into an analog voltage, that is, an image signal. Specifically, the data driver 4 latches the data Data aligned through the timing controller 8 according to the SSC, and then scan pulses are supplied to the gate lines GL1 to GLn in response to the SOE signal. Each horizontal line is supplied with one horizontal line of video signal to each of the data lines DL1 through DLm. At this time, the data driver 4 selects the gamma voltage of the positive or negative polarity corresponding to the gray value of the aligned data Data according to the inversion signal from the timing controller 8 and converts the selected gamma voltage into an image signal. Supply to each data line DL1 to DLm.

The gate driver 6 sequentially drives the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8. Specifically, the gate driver 4 may include a gate start signal (GSP), a gate shift clock (GSC), and a gate output enable (GOE) signal, which is a gate control signal GCS. Etc., the scan pulses having the gate high voltage VGH level are sequentially supplied to the gate lines GL1 to GLn. In the remaining periods during which the scan pulse is not supplied, the gate low voltage VGL1 of the third level or the gate low voltage VGL2 of the fourth voltage level is alternately supplied every frame.

The gate low voltages VGL1 and VGL2 of the third or fourth voltage levels are alternately scanned in odd or even frame periods so as to correspond to common voltage supply timings of the first or second voltage levels, respectively. The gate lines CL1 to GLn are supplied to the remaining periods in which no pulses are supplied. The method of supplying the gate low voltages VGL1 and VGL2 will be described in detail later with reference to the accompanying drawings.

The timing controller 8 includes a data driver 4 and a gate driver including a common voltage supply unit not shown according to external image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync, and DE. (6) is controlled respectively. Specifically, the timing controller 8 arranges the image data RGB input from the outside to be suitable for driving the liquid crystal panel 2 and supplies the image data RGB to the data driver 4. The gate control signal GCS and the data control signal (eg, at least one of a sync signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical sync signals Hsync and Vsync) may be used. DCS) is generated and supplied to the gate driver 6 and the data driver 4, respectively. At this time, the timing controller 8 supplies an inversion signal Pol signal to the common voltage supply unit and the gate driver 6, which are not shown. That is, the timing controller 8 controls the common voltage supply unit to invert and supply the level of the common voltage Vcom every frame through the inversion signal, and the gate driver 6 performs the third frame every frame. Alternatively, the gate low voltages VGL1 and VGL2 of the fourth level are supplied to the gate lines GL1 through GLn. In the meantime, the timing controller 8 may include a line inversion method and a column inversion in each pixel area according to the first or second level common voltage Vcom supply structure of each pixel area formed in the liquid crystal panel 2. The data driver 4 is controlled to be driven in at least one of the following methods:), frame inversion, and dot inversion.

3 is a waveform diagram for describing a method of driving the liquid crystal panel shown in FIG. 1.

More specifically, FIG. 3 illustrates a method of driving the first pixel region included in the first horizontal lines disposed on the top of the liquid crystal panel 2, and the last horizontal line disposed on the bottom of the liquid crystal panel 2. A driving waveform diagram for describing a driving method of an included n-th pixel region is illustrated.

When driving the liquid crystal panel 2, the polarity of the common voltage Vcom of the first and second voltage levels is inverted at the start of every frame in every frame unit, and the image signal Vpixel is synchronized with the scan pulse VGH. It is supplied to each pixel area sequentially from the first horizontal line of every frame. Therefore, the horizontal lines arranged at the bottom of the liquid crystal panel 2 are charged with the image signal Vpixel of the previous frame, but are supplied with the inverted common voltage Vcom in the current frame. The polarities of the common voltages Vcom become the same.

More specifically, in the driving method of the liquid crystal panel 2 according to the present invention, a negative common voltage having a first voltage level in each pixel area of the liquid crystal panel 2 in an odd numbered frame period of every frame period. (-) Is supplied to each pixel area, and a positive common voltage (+) of a second voltage level may be supplied to each pixel area in an even-numbered frame period.

In this case, each of the gate low voltages VGL1 and VGL2 of the third or fourth voltage level may be in odd or even frame periods so as to correspond to the common voltage supply timing of the first or second voltage level, respectively. The gate lines CL1 to GLn are supplied to the remaining periods in which scan pulses are not alternately supplied to each other.

In other words, in the odd frame period in which the negative common voltage (−) of the first voltage level is supplied to the pixel regions, the gate low voltage of the third voltage level lower than the negative common voltage (−) of the first voltage level is provided. (VGL2) is supplied to each of the gate lines CL1 to GLn in the remaining period in which the scan pulse is not supplied, and in the even-numbered frame period in which the positive common voltage (+) of the second voltage level is supplied to the pixel areas. The gate low voltage VGL1 of the fourth voltage level lower than the positive common voltage (+) of the second voltage level may be supplied to each gate line CL1 through GLn in the remaining period in which the scan pulse is not supplied.

Accordingly, as shown in FIG. 3, the voltage width between the gate low voltages VGL1 and VGL2 of the third and fourth levels is equal to the voltage width between the common voltage Vcom of the first and second voltage levels. It can be set to swing. That is, the swing supply time point of the common voltage Vcom of the first and second voltage levels and the swing supply time point of the gate low voltages VGL1 and VGL2 of the third and fourth levels become the same, The voltage width between the gate low voltages VGL1 and VGL2 of the fourth level and the voltage width between the common voltage Vcom of the first and second voltage levels are also maintained to be generated by the parasitic capacitor Cgs of each pixel region. The voltage difference can be minimized.

When the voltage width between the gate low voltages VGL1 and VGL2 of the third and fourth levels and the voltage width between the common voltage Vcom of the first and second voltage levels are kept the same at the same timing, Equation 1 below. As shown, the voltage difference generated by the parasitic capacitor Cgs of each pixel area may be minimized.

In other words, if the voltage width Δgate-low between the gate low voltages VGL1 and VGL2 swinging and the voltage width ΔVcom between the swinging common voltage Vcom are the same, the parasitic capacitor Ggs ), The voltage difference is close to zero.

Accordingly, even when the common voltage polarity is inverted at the start of every frame in every frame unit, and the image signal is sequentially supplied from the first horizontal line of every frame, the coupling phenomenon due to the change of the common voltage polarity can be minimized. In particular, the coupling phenomenon due to the parasitic capacitor Ggs is minimized even at the lower end of the liquid crystal panel 2 so that the luminance difference does not occur between the upper and lower ends of the liquid crystal panel 2.

Meanwhile, as described above, when the gate low voltages VGL1 and VGL2 of the third and fourth voltage levels are alternately supplied, the voltage level of the image signal is always maintained higher than the gate low voltages VGL1 and VGL2. The luminance difference of the upper and lower ends according to the leakage current of the TFT can also be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

A liquid crystal panel having a plurality of pixel regions supplied with a common voltage swinging at first and second voltage levels;
A gate driver for driving the gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels;
A data driver for driving data lines of the liquid crystal panel;
And a timing controller for aligning and supplying image data input from an external device to the data driver, generating a gate and data control signal, and controlling the gate and data driver, respectively. The method of claim 1,
The gate driver
In addition to sequentially supplying a scan pulse of a gate high voltage level to each gate line according to the gate control signal,
And the gate low voltage of the third voltage level or the gate low voltage of the fourth voltage level are alternately supplied every frame during the remaining periods during which the scan pulse is not supplied. The method of claim 2,
Each of the gate low voltages of the third or fourth voltage level
To be supplied to the gate lines in the remaining periods in which the scan pulses are not alternately supplied to each other in odd or even frame periods so as to correspond to common voltage supply timings swinging at the first or second voltage levels, respectively. A drive device for a liquid crystal display device. The method of claim 3, wherein
In a frame period in which the common voltage of the first voltage level is supplied to the pixel regions at the negative voltage level, the gate low voltage of the third voltage level lower than the negative common voltage of the first voltage level is applied to the scan pulse. Is supplied to each of the gate lines for the remaining periods of no supply,
In the frame period in which the common voltage of the second voltage level is supplied to the pixel regions at the positive polarity level, the gate pulse voltage of the fourth voltage level lower than the positive common voltage of the second voltage level is supplied with the scan pulse. The driving device of the liquid crystal display device, characterized in that being supplied to each of the gate lines in the remaining period. The method of claim 4, wherein
The voltage width between the gate low voltages of the third and fourth levels is
And a swing device having a width equal to a voltage width between the common voltages of the first and second voltage levels. Supplying a common voltage swinging at first and second voltage levels to respective pixel regions of the liquid crystal panel;
Driving gate lines of the liquid crystal panel with scan pulses of a gate low voltage and a gate high voltage swinging at third and fourth voltage levels;
Driving data lines of the liquid crystal panel;
Generating a gate and data control signal to control the gate and the data driver, respectively. The method according to claim 6,
Driving the gate lines
In addition to sequentially supplying a scan pulse of a gate high voltage level to each gate line according to the gate control signal,
And alternately supplying the gate low voltage of the third voltage level or the gate low voltage of the fourth voltage level in every frame unit during the remaining periods during which the scan pulse is not supplied. The method of claim 7, wherein
Each of the gate low voltages of the third or fourth voltage level
To be supplied to the respective gate lines in the remaining periods in which the scan pulses are not alternately supplied to each other in odd or even frame periods so as to correspond to common voltage supply timings swinging at the first or second voltage levels, respectively. A method of driving a liquid crystal display device. The method of claim 8,
In a frame period in which the common voltage of the first voltage level is supplied to the pixel regions at the negative voltage level, the gate low voltage of the third voltage level lower than the negative common voltage of the first voltage level is applied to the scan pulse. Is supplied to each of the gate lines for the remaining periods of no supply,
In the frame period in which the common voltage of the second voltage level is supplied to the pixel regions at the positive polarity level, the gate pulse voltage of the fourth voltage level lower than the positive common voltage of the second voltage level is supplied with the scan pulse. The method of driving a liquid crystal display device, characterized in that being supplied to each of the gate lines in the remaining period. The method of claim 9,
The voltage width between the gate low voltages of the third and fourth levels is
And swing to have a width equal to a voltage width between the common voltages of the first and second voltage levels.

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