KR20070121284A - Lcd and driving method thereof - Google Patents

Abstract

A liquid crystal display device and a method for driving the same are provided to prevent unnecessary power consumption by preventing a flow of current on one data line. A liquid crystal display panel(210) includes a plurality of data lines and a plurality of gate lines crossing the data lines, and a plurality of sub-pixels including unit pixels. Two unit pixels are formed at intersections between a pair of data lines and a gate line. A pole generation unit generates alternately a positive pole and a negative pole. A data driving unit(260) converts digital data voltage to an analog data voltage, supplies the analog voltage to the data lines, performs a column inversion process for the polarity of the analog data voltage according to the positive pole and the negative pole, and supplies the analog data voltage to the data lines.

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a configuration diagram of a general liquid crystal display device.

3 is an exemplary view illustrating a driving method of a general liquid crystal display device.

4 is a characteristic diagram of data voltage supplied from a general liquid crystal display.

5 is a configuration diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

6 is an exemplary view illustrating a driving method of a liquid crystal display according to the present invention.

7 is a characteristic diagram of data voltage supplied from a liquid crystal display according to the present invention;

Explanation of symbols on the main parts of the drawings

100, 200: liquid crystal display device 110, 210: liquid crystal display panel

120, 250: data driver 130, 260: gate driver

140 and 240: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generation unit 190, 220: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of simultaneously supplying positive and negative data voltages to one subpixel and supplying only data voltages of the same polarity to one data line. will be.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on, thereby maintaining a constant voltage of the liquid crystal cell Clc.

When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a general liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a configuration diagram of a general liquid crystal display device.

Referring to FIG. 2, the liquid crystal display device 100 includes a thin film transistor TFT for driving data lines DL1 to DLm and gate lines GL1 to GLn and driving the liquid crystal cell Clc at an intersection thereof. A liquid crystal display panel 110 having a thin film transistor, a data driver 120 for supplying data to the data lines DL1 to DLm of the liquid crystal display panel 110, and a gate of the liquid crystal display panel 110. A gate driver 130 for supplying scan pulses to the lines GL1 to GLn, a gamma reference voltage generator 140 for generating a gamma reference voltage and supplying it to the data driver 120, and a liquid crystal display panel 110. ) Generates a backlight assembly 150 for irradiating light, an inverter 160 for applying an alternating voltage and current to the backlight assembly 160, and a common voltage Vcom to generate liquid crystals of the liquid crystal display panel 110. A common voltage generator 170 for supplying the common electrode of the cell Clc, A timing for controlling the gate driving voltage generator 180 for generating the high voltage VGH and the gate low voltage VGL and supplying the gate voltage 130 to the gate driver 130, and for controlling the data driver 120 and the gate driver 130. The controller 190 is provided.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. The data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to the lower glass substrate of the liquid crystal display panel 110. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190, and digital video data supplied from the timing controller 190. After sampling and latching the RGB, the liquid crystal cell Clc of the liquid crystal display panel 110 is converted into an analog data voltage capable of expressing gray scale based on the gamma reference voltage supplied from the gamma reference voltage generator 140. Supply to the data lines DL1 to DLm.

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190 to generate the gate lines GL1 to GLn. Feed the fields. In this case, the gate driver 130 determines the high level voltage and the low level voltage of the scan pulse based on the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB, which is supplied from a digital video card (not shown), to the data driver 120, and also horizontal / vertical synchronization signals H and V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC may be generated and supplied to the data driver 120 and the gate driver 130, respectively. Here, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a source output enable signal SOE, and the gate driving control signal GDC is a gate start pulse GSP. ) And gate output enable (GOE).

In the liquid crystal display device having the above configuration and function, the liquid crystal display panel 110 is driven in a dot inversion manner as shown in FIG. 3, so that when the data voltage is supplied to one data line, the data is provided in units of one horizontal line. The polarity of the voltage is transferred. That is, as shown in FIG. 4, the data voltage supplied to one data line is transferred from the positive polarity (+) to the negative polarity (−) or in the negative polarity (−) in units of one horizontal line based on the common voltage Vcom. From to positive polarity. As the polarity of the data voltage is shifted on one data line, current flows from the positive data voltage to the negative data voltage, and power is unnecessarily consumed by the current.

In the case of the liquid crystal display device driven by the dot inversion method, in the odd frame, only pixels supplied with the positive data voltage are visible on the screen, and pixels supplied with the negative data voltage become black and do not appear on the screen. On the other hand, in the even-numbered frame, only the pixel to which the negative data voltage is supplied is visible on the screen, and the pixel to which the positive data voltage is supplied is black and is not visible on the screen. In this way, flicker occurs because the polarities of the data voltages that are displayed on the screen in the odd and even frames are switched.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display and a driving method thereof capable of simultaneously supplying positive and negative data voltages to one subpixel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display and a driving method thereof capable of simultaneously supplying positive and negative data voltages to one subpixel and supplying only data voltages of the same polarity to one data line.

An object of the present invention is to supply a positive data and a negative data voltage to one subpixel at the same time, and to supply a data voltage of the same polarity to one data line, thereby preventing current flow on one data line And a driving method thereof.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof which can prevent unnecessary consumption of power by preventing current flow on one data line.

SUMMARY OF THE INVENTION An object of the present invention is to supply a positive voltage and a negative data voltage to one subpixel at the same time, and to supply a data voltage having the same polarity to one data line so that the data voltage is displayed on the odd and even frames. The present invention provides a liquid crystal display device and a driving method thereof which can prevent flicker by allowing data voltages having opposite polarities to be canceled even if their polarities are changed.

In order to achieve the above object, the present invention provides a plurality of unit pixels formed by crossing a plurality of data lines and a plurality of gate lines, and formed in regions where a pair of data lines and a gate line cross each other. A liquid crystal display panel on which sub pixels are formed; Pole generating means for alternately generating a positive pole and a negative pole; And converting the input digital data voltage into an analog data voltage and supplying the plurality of data lines to the plurality of data lines, and the polarity of the analog data voltage according to the positive pole or the negative pole which are alternately inputted by the odd and even frames. And data driving means for supplying the data lines by column inversion.

The pole generating means is characterized in that for supplying a positive pole to the data driving means in the odd frame.

The data driving means supplies positive data to the odd data line and negative data to the even data line among the pair of data lines when a positive pole is input from the pole generating means in the odd frame. It is characterized by.

The pole generating means is characterized in that for supplying a negative pole to the data driving means in the even frame.

The data driving means supplies negative data to the odd data line and positive data to the even data line among the pair of data lines when a negative pole is input from the pole generating means in the even-numbered frame. It is characterized by.

The pole generating means may supply a negative pole to the data driving means in an odd frame.

The data driving means supplies negative data to the odd data line and positive data to the even data line among the pair of data lines when a negative pole is input from the pole generating means in the odd frame. It is characterized by.

The pole generating means is characterized in that for supplying a positive pole to the data driving means in the even frame.

The data driving means supplies positive data to the odd data line and negative data to the even data line among the pair of data lines when the positive pole is input from the pole generating means in the even-numbered frame. It is characterized by.

According to an exemplary embodiment of the present invention, a liquid crystal display panel includes a plurality of data lines and a plurality of gate lines intersecting each other, and sub pixels including two unit pixels formed in regions where a pair of data lines and one gate line cross each other. A method of driving a liquid crystal display device comprising: alternately generating a positive pole and a negative pole for each odd and even frame; And converting the input digital data voltage into an analog data voltage and supplying the plurality of data lines to the plurality of data lines, and the polarity of the analog data voltage according to the positive pole or the negative pole which are alternately inputted by the odd and even frames. Supplying to the data lines by column inversion.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, the liquid crystal display device 200 of the present invention shown in FIG. 5 is the backlight assembly 150, the inverter 160, the common voltage generator 170, and the liquid crystal display device 100 shown in FIG. 2. Although the gate driving voltage generator 180 is provided, these components are not shown.

Referring to FIG. 5, the liquid crystal display 200 of the present invention is formed by crossing a plurality of data lines DL1 through DL2m and a plurality of gate lines GL1 through GLn, and a pair of data lines. A liquid crystal display panel 210 in which subpixels formed of two unit pixels formed in regions where one gate line intersects, a supply of scan pulses, a supply of data voltages, and a control for generating a POL. The gamma reference is applied to the timing controller 220, the pole generator 230 for alternately generating the positive pole and the negative pole under the control of the timing controller 220, and the high potential power voltage VDD. The gamma reference voltage generator 240 for generating a voltage and the digital data RGB input from the timing controller 220 are converted into analog data voltages and supplied to the plurality of data lines DL1 to DL2m, Th and storm A data driver 250 for column inverting the polarity of the analog data voltage according to the positive pole (+) or the negative pole (−) inputted alternately for each frame and supplying the data lines to the data lines DL1 to DL2m; The gate driver 260 is configured to supply scan pulses to the gate lines GL1 to GLn of the liquid crystal display panel 210 under the control of the timing controller 220.

In the liquid crystal display panel 210, liquid crystal is injected between two glass substrates. The data lines DL1 through DL2m and the gate lines GL1 through GLn are orthogonal to each other on the lower glass substrate of the liquid crystal display panel 110. The data lines DL1 through DL2m and the gate lines GL1 through. TFTs are formed at the intersections of GLn). In particular, the neighboring odd-numbered and even-numbered data lines among the data lines DL1 to DL2m are paired to form a subpixel. That is, subpixels formed of two unit pixels formed in regions where a pair of data lines and one gate line cross each other are formed. As shown in FIG. 5, the unit pixel R and the even-numbered data line connected to the odd-numbered data line DL1 at regions where the pair of data lines DL1 and DL2 and the gate line GL1 intersect. A subpixel R made up of the unit pixels R connected to the DL2 is formed.

The timing controller 220 supplies digital video data RGB, which is supplied from an image processing scaler (not shown) included in a system such as a television receiver or a computer monitor, to the data driver 120, and also provides a clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC are generated using the horizontal / vertical synchronizing signals H and V and supplied to the data driver 120 and the gate driver 130, respectively. In addition, the timing controller 220 supplies a polarity control signal PCS for controlling the polarity of the analog data voltage to be supplied to the data lines DL1 to DL2m to the pole generator 230.

The pole generator 230 supplies the positive pole (+) to the data driver 250 in the odd frame according to the polarity control signal PCS input from the timing controller 220 and the negative pole in the even frame. (-) Is supplied to the data driver 250. Alternatively, the pole generator 230 supplies the negative pole (−) to the data driver 250 in the odd frame according to the polarity control signal PCS input from the timing controller 220, and determines the positive pole in the even frame. The polarity pole (+) is supplied to the data driver 250.

The gamma reference voltage generator 240 receives a high potential power voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage to output the data to the data driver 250.

The data driver 250 converts the gamma reference voltage input from the gamma reference voltage generator 240 into an analog data voltage according to the digital data voltage level supplied from the timing controller 220 to the data lines DL1 to DL2m. Supply. Herein, the data driver 250 displays the polarity of the analog data voltage according to the positive pole (+) or the negative pole (−) that are alternately input from the pole generator 230 for each frame, as shown in FIG. 6. The version is supplied to the data lines DL1 to DL2m.

For example, when the pole generator 230 supplies the positive pole (+) to the data driver 250 in the odd frame according to the polarity control signal PCS, the data driver 250 is one in the odd frame. Of the pair of data lines connected to the subpixel of, positive data is supplied to the odd data line and negative data is supplied to the even data line. When the pole generator 230 supplies the negative pole (−) to the data driver 250 in the even-numbered frame according to the polarity control signal PCS, the data driver 250 performs one sub-frame in the even-numbered frame. Of the pair of data lines connected to the pixel, the negative data is supplied to the odd data line and the positive data is supplied to the even data line.

When the pole generator 230 supplies the negative pole (−) to the data driver 250 in the odd frame according to the polarity control signal PCS, the data driver 250 may include one subpixel in the odd frame. Of the pair of connected data lines, negative data is supplied to the odd data line and positive data is supplied to the even data line. When the pole generator 230 supplies the positive pole (+) to the data driver 250 in the even-numbered frame according to the polarity control signal PCS, the data driver 250 performs one sub-frame in the even-numbered frame. Of the pair of data lines connected to the pixel, positive data is supplied to the odd data line and negative data is supplied to the even data line.

As described above, since the present invention performs column inversion of the polarity of the analog data voltage supplied to the pair of data lines connected to one subpixel, as shown in FIG. When only one positive data voltage is supplied to one data line, only the negative data voltage is supplied to another data line of the pair of data lines as shown in FIG. As such, the present invention prevents the polarity of the data voltage from being transferred on one data line to prevent generation of current. That is, since the current flows from the positive voltage to the negative voltage, in order to prevent such a current flow phenomenon, the present invention supplies only a data voltage having the same polarity to one data line.

In addition, the present invention forms a subpixel having two unit pixels and supplies data voltages of opposite polarity to the two unit pixels forming one subpixel, thereby displaying on the screen in the odd and even frames. Even if the polarities of the data voltages change, the data voltages of opposite polarities are canceled out to prevent flicker.

The gate driver 260 sequentially generates scan pulses in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 220 and supplies them to the gate lines GL1 to GLn. Here, the high level voltage of the scan pulse coincides with the gate high voltage VGH level, and the low level voltage of the scan pulse coincides with the level of the gate low voltage VGL.

As described above, according to the present invention, by simultaneously supplying the positive and negative data voltages to one subpixel and supplying only the data voltages of the same polarity to one data line, the current flow is prevented on one data line to prevent electric power. It is possible to prevent unnecessary consumption of the chip, and to prevent flicker by canceling the data voltages of opposite polarities even when the polarities of the data voltages to be displayed on the odd and even frames are reversed.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (14)

A liquid crystal display panel in which a plurality of data lines and a plurality of gate lines are formed to cross each other, and sub pixels including two unit pixels formed in regions where a pair of data lines and one gate line cross each other; Pole generating means for alternately generating a positive pole and a negative pole; And The digital data voltage is converted into an analog data voltage and supplied to the plurality of data lines, and the polarity of the analog data voltage is changed according to the positive pole or the negative pole which are alternately inputted for every odd and even frames. Data driving means for supplying the data lines by column inversion Liquid crystal display comprising a. The method of claim 1, And the pole generating means supplies a positive pole to the data driving means in an odd frame. The method of claim 2, The data driving means supplies positive data to the odd data line and negative data to the even data line among the pair of data lines when a positive pole is input from the pole generating means in the odd frame. Liquid crystal display device characterized in that. The method of claim 1, And the pole generating means supplies a negative pole to the data driving means in the even-numbered frame. The method of claim 4, wherein The data driving means supplies negative data to the odd data line and positive data to the even data line among the pair of data lines when a negative pole is input from the pole generating means in the even-numbered frame. Liquid crystal display device characterized in that. The method of claim 1, And the pole generating means supplies a negative pole to the data driving means in an odd frame. The method of claim 6, The data driving means supplies negative data to the odd data line and positive data to the even data line among the pair of data lines when a negative pole is input from the pole generating means in the odd frame. Liquid crystal display device characterized in that. The method of claim 1, And the pole generating means supplies a positive pole to the data driving means in the even-numbered frame. The method of claim 8, When the positive pole is input from the pole generating means in the even-numbered frame, the data driving means supplies positive data to the odd-numbered data line and negative data to the even-numbered data line among the pair of data lines. Liquid crystal display device characterized in that. A liquid crystal display panel includes a plurality of data lines and a plurality of gate lines formed to cross each other, and subpixels formed of two unit pixels formed in regions where a pair of data lines and one gate line cross each other. In the driving method of a liquid crystal display device, Alternately generating a positive pole and a negative pole for each odd and even frames; And The digital data voltage is converted into an analog data voltage and supplied to the plurality of data lines, and the polarity of the analog data voltage is changed according to the positive pole or the negative pole which are alternately inputted for every odd and even frames. Supplying the data lines by column inversion Method of driving a liquid crystal display comprising a. The method of claim 10, When the positive pole occurs in the odd frame, the positive data is supplied to the odd data line and the negative data is supplied to the even data line among the pair of data lines. . The method of claim 10, When the negative pole is input in the even-numbered frame, the negative data is supplied to the odd data line and the positive data is supplied to the even-numbered data line among the pair of data lines. . The method of claim 10, When the negative pole is input in the odd frame, the negative data is supplied to the odd data line and the positive data is supplied to the even data line among the pair of data lines. . The method of claim 10, When the positive pole is input in the even-numbered frame, positive data is supplied to the odd data line and negative data is supplied to the even-numbered data line among the pair of data lines. .

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