KR101264705B1 - LCD and drive method thereof - Google Patents

Abstract

The present invention provides a liquid crystal display device that can reduce the data charging amount of a later frame among neighboring frames without inversion in the N-frame inversion driving method, and generates a gate high voltage that determines the high level of the scan pulse. A gate high voltage generator; A timing controller controlling supply and deformation of the gate high voltage; A gate voltage processor configured to output a normal gate high voltage without modifying the gate high voltage or a modified gate high voltage with the gate high voltage modified according to the control of the timing controller; And a modified scan pulse having a modified high level determined by the modified gate high voltage or sequentially supplying a normal scan pulse having a normal high level determined by the normal gate high voltage according to the control of the timing controller. And a gate driver to sequentially supply the liquid crystal display panel to the liquid crystal display panel.

LCD, frame, inversion, strain gate high voltage, strain scan pulse

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is an illustrative example of N-frame inversion.

4 is a signal characteristic diagram of a conventional liquid crystal display device.

5 is a configuration diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

6 is a signal characteristic diagram of a liquid crystal display of the present invention.

7 is an operation characteristic diagram of a timing controller and a gate voltage generator shown in FIG. 5;

FIG. 8 is an operation characteristic diagram of a gate voltage generator and a gate driver shown in FIG. 5; FIG.

Description of the Related Art

100 and 200: liquid crystal display 110: liquid crystal display panel

120: data driver 130, 240: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generation unit 190, 220: timing controller

210: gate high voltage generator 230: gate voltage processor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, in an N-frame inversion driving scheme, a scan pulse having a gate high voltage and a high level determined by the same is modified to reduce the data charging amount of a later frame among adjacent frames without inversion. A liquid crystal display device and a driving method thereof which can be reduced.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

A common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst serves to charge the data voltage applied from the data line DL when the TFT is turned on to maintain the voltage of the liquid crystal cell Clc constant.

When a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode to apply a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film for driving the liquid crystal cell Clc at the intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. A liquid crystal display panel 110 including a TFT (TFT: Thin Film Transistor), a data driver 120 for supplying a data voltage Vdata to the data lines DL1 to DLm of the liquid crystal display panel 110, A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the liquid crystal display panel 110, and a gamma reference voltage generator for generating a gamma reference voltage and supplying the gamma reference voltage to the data driver 120. 140, the backlight assembly 150 for irradiating light to the liquid crystal display panel 110, the inverter 160 for applying alternating voltage and current to the backlight assembly 150, and the common voltage Vcom. Generated and supplied to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110. The voltage generator 170, the gate driving voltage generator 180 for generating and supplying the gate high voltage VGH and the gate low voltage VGL to the gate driver 130, the data driver 120 and the gate. A timing controller 190 for controlling the driver 130 is provided.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies the data voltage Vdata to the data lines DL1 through DLm in response to the data driving control signal DDC supplied from the timing controller 190. Here, the data driver 120 samples and latches the digital video data RGB supplied from the timing controller 190, and then the liquid crystal display panel based on the gamma reference voltage supplied from the gamma reference voltage generator 140. The liquid crystal cell Clc of 110 converts the grayscale into an analog data voltage Vdata and supplies the data to the data lines DL1 through DLm.

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190, thereby providing the gate lines GL1 to GLn. To feed. The gate driver 130 determines the high level voltage and the low level voltage of the scan pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate drive voltage generator 180, respectively.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies the digital video data RGB supplied from the system to the data driver 120 and controls the data driving by using the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 120 and the gate driver 130, respectively. The timing controller 190 generates a gate shift clock GSC and supplies it to the gate driver 130. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

Various inversion methods for driving a conventional LCD having such a configuration and function have been developed. For example, an N-frame inversion method has been developed to improve interlace afterimages.

Referring to the N-frame inversion driving method, the frames ((N-3) F, (N-2) F, (N-1)) sequentially input to the conventional LCD as shown in FIG. Inversion is performed between neighboring frames among F, (N) F, (N + 1) F, and (N + 2) F, but any two neighboring frames ((N) F, (N-1) There is no inversion between F). That is, the N-frame inversion driving method inverts a plurality of frames which are sequentially input in order, but does not invert adjacently input frames at every specific time by dividing the plurality of input frames into a certain number of frame units. .

Signal characteristics of the conventional liquid crystal display device driven by the N-frame inversion method will be described with reference to FIG. 4 as follows.

As shown in FIG. 4B, the gate high voltage VGH, which determines the high level of the scan pulse, is kept constant in all frames input in the N-frame inversion scheme. In this case, when the gate high voltage VGH is kept constant, the neighboring frames ((N) F, (N + 1) F, and (N + 2) F) inverted as shown in FIG. ), The polarity of the data voltage (Vdata) is inverted based on the common voltage (Vcom), but the polarity of the data voltage (Vdata) between the adjacent frames ((N-1) F, (N) F) without inversion Remains the same.

Then, as shown in Fig. 4A, the data charging amount of the next frame (N) F among the adjacent frames (N-1) F and (N) F without inversion is the previous frame ((N−). 1) F) is larger than the data charging amount, the next frame ((N) F) of neighboring frames ((N-1) F, (N) F) without inversion as shown in Fig. 4C. The luminance level of? Is significantly higher than the luminance level of the previous frame (N-1) F.

As described above, the conventional liquid crystal display device driven by the N-frame inversion method has a large amount of change in luminance between neighboring frames ((N-1) F and (N) F) without inversion, thereby preventing flicker. Have

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to modify a scan pulse having a gate high voltage and a high level determined by the N-frame inversion driving method so that a neighboring frame without inversion is made. Among them, there is provided a liquid crystal display device and a driving method thereof capable of reducing the data charging amount of a later frame.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display and a driving method thereof in which an amount of change in luminance can be reduced by reducing the data charging amount of a subsequent frame among neighboring frames without inversion in the N-frame inversion driving scheme. .

An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of removing flicker by reducing the amount of change in luminance in the N-frame inversion driving method.

According to one aspect of the present invention, there is provided a liquid crystal display device including: a gate high voltage generator configured to generate a gate high voltage for determining a high level of a scan pulse; A timing controller controlling supply and deformation of the gate high voltage; A gate voltage processor configured to output a normal gate high voltage without modifying the gate high voltage or a modified gate high voltage with the gate high voltage modified according to the control of the timing controller; And a modified scan pulse having a modified high level determined by the modified gate high voltage or sequentially supplying a normal scan pulse having a normal high level determined by the normal gate high voltage according to the control of the timing controller. And a gate driver to sequentially supply the liquid crystal display panel to the liquid crystal display panel.

The timing controller may be configured to control N-frame inversion of frames input in sequence.

The gate voltage processor supplies the normal gate high voltage to the gate driver during the driving period of neighboring frames inverted by the N-frame inversion driving.

The gate voltage processor supplies the modified gate high voltage to the gate driver during a driving period of a next frame among neighboring frames that are not in-versioned in the N-frame inversion driving.

The gate driver may supply the modified scan pulse having a high level and a deformation level proportional to a high level and a deformation level of the modified gate high voltage.

The modified gate high voltage may be increased to the normal gate high voltage level after the voltage level is lowered with a predetermined slope every predetermined period.

The modified scan pulse has a high level in a certain section and a deformation level in which a voltage level decreases with a certain slope in a section other than the high level.

The gate voltage processor supplies the normal gate high voltage to the gate driver during a driving period of a previous frame among neighboring frames that are not in-versioned in the N-frame inversion driving.

According to the driving method of the liquid crystal display of the present invention, after generating a normal gate high voltage during the driving period of the inverted neighboring frames, a normal scan pulse having a high level proportional to the normal gate high voltage is sequentially applied to the liquid crystal display panel. Supplying; Supplying a modified scan pulse having a voltage level proportional to the modified gate high voltage level after generating a modified gate high voltage during a driving period of a subsequent frame among the non-inverted neighboring frames; And sequentially generating a normal scan pulse having a voltage level proportional to the normal gate high voltage level after generating the normal gate high voltage during a driving period of a previous frame among the non-inverted neighboring frames. Steps.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention. However, the liquid crystal display device 200 of the present invention also has the same gamma reference voltage generator 140, backlight assembly 150, inverter 160, and common voltage as the liquid crystal display device 100 shown in FIG. 2. Although the generator 170 is provided, these components are not shown in FIG. 5 for convenience of description.

Referring to FIG. 5, in the liquid crystal display device 200 of the present invention, the data lines DL1 through DLm and the gate lines GL1 through GLn intersect with each other to drive the liquid crystal cell Clc at an intersection thereof. The liquid crystal display panel 110 includes a thin film transistor TFT.

The liquid crystal display 200 of the present invention supplies and modifies the gate high voltage generation unit 210 for generating the gate high voltage VGH for determining the high level of the scan pulse, and the gate high voltage VGH. And a gate high voltage VGH output from the gate high voltage generator 210 under the control of the timing controller 220 and the timing controller 220 controlling the supply timing of the scan pulse and the data voltage Vdata. The gate voltage processor 230 outputs the modified gate high voltage VGH_M without deformation, and outputs the modified gate high voltage VGH_M, and the normal gate high voltage VGH output from the gate voltage processor 230 under the control of the timing controller 220. The modified high voltage determined by the modified gate high voltage VGH_M is sequentially supplied to the liquid crystal display panel 110 or output from the gate voltage processor 230. The gate driver 240 which sequentially supplies the modified scan pulse having a bell to the liquid crystal display panel 110 and the frames which are sequentially input according to the control of the timing controller 220 are N-frame inverted to form the liquid crystal display panel ( The data driver 250 is implemented in the 110.

The gate high voltage generator 210 receives the high potential power supply voltage VDD to generate a normal gate high voltage VGH that determines the high level of the scan pulse and outputs it to the gate voltage processor 230.

The timing controller 220 outputs an inversion control signal NIC for instructing N-frame inversion of frames sequentially input from the system to the data driver 250. That is, the data driver 250 N-frames the frames input through the timing controller 220 in response to the inversion control signal NIC to implement the N-frame in the liquid crystal display panel 110. The data driver 250 supplies the data voltage Vdata to the data lines DL1 to DLm of the liquid crystal display panel 110.

More specifically, as shown in FIG. 3, the data driver 250 includes frames ((N-3) F, (N-2) F, (N-1) F, (N) F, The neighboring frames of (N + 1) F and (N + 2) F are inverted, but the two neighboring frames ((N) F and (N-1) F) are not inverted.

When the N-frame is inverted in this manner, the common voltage (N) between the inverted neighboring frames ((N) F, (N + 1) F, and (N + 2) F) as shown in FIG. The polarity of the data voltage Vdata is inverted with respect to Vcom, but the polarity of the data voltage Vdata remains the same between the adjacent frames (N-1) F and (N) F without inversion.

When inversion is performed in N-frame inversion driving, as shown in FIG. 6B, the timing controller 220 performs the inversion of neighboring frames ((N + 1) F and (N + 2) F). The gate voltage processor 230 is controlled such that the normal gate high voltage VGH is supplied to the gate driver 240 during the driving period. Here, the timing controller 220 supplies a low level polarity channel control signal POLCH to the gate voltage processor 230 to control the output of the normal gate high voltage VGH.

When frame inversion is not performed in N-frame inversion driving, as shown in FIG. 6 (B), the timing controller 220 performs neighboring frames ((N-1) F and (N) without inversion. The gate voltage processor 230 is controlled such that the modified gate high voltage VGH_M is supplied to the gate driver 240 during the driving period MT of the next frame (N) F. The gate voltage processor 230 is controlled such that the normal gate high voltage VGH is supplied to the gate driver 240 during the driving period of 1) F). Here, the timing controller 220 supplies the low level polarity channel control signal POLCH to the gate voltage processor 230 to output the normal gate high voltage VGH in the previous frame (N-1) F. Next, in the next frame (N) F, the high level polarity channel control signal POLCH is supplied to the gate voltage processor 230 to output the modified gate high voltage VGH_M.

In addition, the timing controller 220 supplies the digital video data RGB supplied from the system to the data driver 250, and also uses the horizontal / vertical synchronization signals H and V according to the clock signal CLK. The driving control signal DDC and the gate driving control signal GDC are generated and supplied to the data driver 250 and the gate driver 240, respectively. The timing controller 220 generates a gate shift clock GSC and supplies it to the gate driver 240. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

As shown in FIGS. 7A and 7B, the gate voltage processor 230 inputs a modulation timing control signal FLK in which a high level and a low level are converted at a predetermined period as well as a polarity channel control signal POLCH. Then, the polarity channel control signal POLCH and the modulation timing adjustment signal FLK are logically operated to generate the modified modulation timing adjustment signal FLK_M as shown in FIG. 7C. Here, as shown in FIG. 7, while the low level polarity channel control signal POLCH is input, the gate voltage processor 230 generates the first modified modulation timing control signal FLK_M1 having only a high level. While the high level polarity channel control signal POLCH is input, the gate voltage processor 230 generates a second modified modulation timing control signal FLK_M2 which is substantially the same as the input modulation timing control signal FLK.

When the first modified modulation timing control signal FLK_M1 is generated by the low-level polarity channel control signal POLCH, the gate voltage processor 230 has only the high level in the state where the high potential power voltage VDD is applied. In response to the first modified modulation timing control signal FLK_M1, the normal gate high voltage VGH as shown in FIG. 8 is supplied to the gate driver 240. On the contrary, when the second modified modulation timing control signal FLK_M2 is generated by the high-level polarity channel control signal POLCH, the gate voltage processor 230 receives a high period power voltage VDD at a predetermined period. The modified gate high voltage VGH_M as shown in FIG. 8 is supplied to the gate driver 240 in response to the second modified modulation timing adjustment signal FLK_M2 in which the level and the low level are converted. Here, the modified gate high voltage VGH_M is increased to a normal gate high voltage VGH level after the voltage level is lowered with a predetermined slope as shown in FIG. 8, and the modified gate high voltage VGH_M is modified. The period coincides with the conversion period between the high level and the low level of the second modified modulation timing adjustment signal FLK_M2.

When inversion is performed in N-frame inversion driving, the timing controller 220 performs a low level polarity channel during the driving period of the inverted neighboring frames ((N + 1) F and (N + 2) F). Since the control signal POLCH is supplied to the gate voltage processor 230, the gate voltage processor 230 generates the first modified modulation timing control signal FLK_M1 having only a high level, and then the first modified modulation timing control signal ( The normal gate high voltage VGH is supplied to the gate driver 240 according to FLK_M1.

When frame inversion is not performed in N-frame inversion driving, the timing controller 220 performs the next frame ((N) F) among the neighboring frames ((N-1) F, (N) F) without inversion. Since the high-level polarity channel control signal POLCH is supplied to the gate voltage processor 230 during the driving period MT, the gate voltage processor 230 converts the high level and the low level at regular intervals to form a second modified modulation. After generating the timing control signal FLK_M2, the modified gate high voltage VGH_M is supplied to the gate driver 240 according to the second modified modulation timing control signal FLK_M2. In contrast, the timing controller 220 controls the low-level polarity channel during the driving period of the previous frame (N-1) F among the neighboring frames (N-1) F and (N) F without inversion. Since the signal POLCH is supplied to the gate voltage processor 230, the gate voltage processor 230 generates the first modified modulation timing control signal FLK_M1 having only a high level, and then the first modified modulation timing control signal FLK_M1. ), The normal gate high voltage VGH is supplied to the gate driver 240.

The gate driver 240 sequentially scans the pulses while the frame is driven on the liquid crystal display panel 110 in response to the gate driving control signal GDC and the gate shift clock GSC from the timing controller 220. It supplies to (GL1-GLn).

More specifically, as shown in FIG. 8, when the normal gate high voltage VGH is supplied from the gate voltage processor 230, the gate driver 240 has a high level proportional to the normal gate high voltage level. The normal scan pulse GP is sequentially supplied to the gate lines GL1 to GLn.

In contrast, as shown in FIG. 8, when the modified gate high voltage VGH_M is supplied from the gate voltage processor 230, the gate driver 240 is proportional to the high level and the modified level of the modified gate high voltage VGH_M. The modified scan pulse GP_M having a high level and a modified level is sequentially supplied to the gate lines GL1 to GLn. Here, as shown in FIG. 8, the modified scan pulse GP_M maintains a constant high level in the high level section of the modified gate high voltage VGH_M, and also performs a modified scan in the modified level section of the modified gate high voltage VGH_M. The pulse GP_M is lowered with a constant slope of the voltage level, which is proportional to the decreasing voltage level of the modified gate high voltage VGH_M. As shown in FIG. 8, there is a blank period BLK between which the scan pulses are not supplied.

That is, when frame inversion is not performed in N-frame inversion driving, as shown in FIG. 8, the next frame ((N-1) F, (N) F) of the neighboring frames without inversion (( The modified gate high voltage VGH_M is supplied to the gate driver 240 during the driving period of the N) F), and the normal gate high voltage VGH is supplied to the gate driver during the driving period of the previous frame (N-1) F. Since it is supplied to 240, the previous frame (N-1) F is driven by the normal scan pulse GP, while the after frame (N) F is driven by the modified scan pulse GP_M. As a result, as shown in FIG. 6A, the data charging amount of the rear frame N is reduced compared to the conventional case shown in FIG. 4A, and the previous frame N-1 is substantially reduced. As the data charging amounts of F) and the subsequent frame (N) F become equal, the luminance of the previous frame (N-1) F and the subsequent frame (N) F as shown in Fig. 6C. The level is the same. 4 (C) and 6 (C), the luminance level of the frame (N) F is drastically reduced after being driven by the liquid crystal display 200 of the present invention.

As described above, according to the present invention, a scan pulse having a gate high voltage and a high level determined by the N-frame inversion driving method is modified to reduce the data charging amount of a later frame among neighboring frames without inversion. Therefore, the amount of change in luminance can be reduced, thereby eliminating flicker.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of illustration and not for the purpose of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (11)

A gate high voltage generator configured to generate a gate high voltage for determining a high level of the scan pulse; A timing controller controlling supply and deformation of the gate high voltage; A gate voltage processor configured to output a normal gate high voltage without modifying the gate high voltage or a modified gate high voltage with the gate high voltage modified according to the control of the timing controller; And According to the control of the timing controller, a normal scan pulse having a normal high level determined by the normal gate high voltage is sequentially supplied to a liquid crystal display panel or a modified scan pulse having a modified high level determined by the modified gate high voltage. A gate driver which sequentially supplies the liquid crystal display panel; The timing controller controls the frames to be N-frame inverted in order; The N-frame inversion is a driving scheme which inverts a plurality of frames which are sequentially input in order, but divides the plurality of input frames into a predetermined number of frame units and does not invert adjacently input frames at every specific second. Is; And the gate voltage processor supplies the modified gate high voltage to the gate driver during a driving period of a later frame among neighboring frames which are not in-versioned in the N-frame inversion driving. delete The method of claim 1, And the gate voltage processor supplies the normal gate high voltage to the gate driver during the driving period of neighboring frames inverted by the N-frame inversion driving. delete The method of claim 1, And the gate driver supplies the strain scan pulse having a high level and a strain level proportional to a high level and a strain level of the strain gate high voltage. 6. The method of claim 5, And the modified gate high voltage is increased to the normal gate high voltage level after the voltage level is lowered with a predetermined slope every predetermined period. The method of claim 6, Wherein the modified scan pulse has a high level in a predetermined section and a deformation level in which a voltage level decreases with a predetermined slope in a section other than the high level. The method of claim 1, And the gate voltage processor supplies the normal gate high voltage to the gate driver during a driving period of a previous frame among neighboring frames that are not in-versioned in the N-frame inversion driving. Supplying a normal scan pulse having a high level proportional to the normal gate high voltage after the normal gate high voltage is generated during the driving of the inverted neighboring frames to the liquid crystal display panel in sequence; Supplying a modified scan pulse having a voltage level proportional to the modified gate high voltage level after generating a modified gate high voltage during a driving period of a subsequent frame among the non-inverted neighboring frames; And Sequentially generating a normal scan pulse having a voltage level proportional to the normal gate high voltage level after generating the normal gate high voltage during a driving period of a previous frame among the non-inverted neighboring frames; Method of driving a liquid crystal display comprising a. The method of claim 9, And wherein the modified gate high voltage is increased to the normal gate high voltage level after the voltage level decreases with a predetermined slope every predetermined period. The method of claim 9, And wherein the modified scan pulse has a high level in a certain section and a deformation level in which a voltage level decreases with a certain slope in a section other than the high level.

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