KR101994777B1

KR101994777B1 - Liquid crystal display and driving method thereof

Info

Publication number: KR101994777B1
Application number: KR1020120138781A
Authority: KR
Inventors: 이승주
Original assignee: 엘지디스플레이 주식회사
Priority date: 2012-12-03
Filing date: 2012-12-03
Publication date: 2019-09-25
Also published as: KR20140072346A

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to increase the pulse width of a source output enable signal (SOE), thereby reducing the amount of data charging in a later frame among neighboring frames without inversion. It is a technical problem to provide an apparatus and a driving method thereof. To this end, the liquid crystal display according to the present invention comprises: a panel in which pixels are formed at intersections of gate lines and data lines; A gate driver for driving the gate lines; A data driver for converting image data into a data voltage and outputting the data voltage to the data lines; And generating a polarity control signal for driving the panel in an N-frame inversion scheme, transmitting the polarity control signal to the data driver, analyzing the input image data, and reducing the luminance. And a timing controller configured to control the data driver with a second source output enable signal, and to transmit the image data aligned with the panel to the data driver.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing flicker.

A liquid crystal display device displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field.

To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving unit for driving the liquid crystal panel.

The liquid crystal display device drives the liquid crystal panel in various inversion methods to prevent deterioration of the liquid crystal and to improve display quality. The inversion method may include a frame inversion system, a line inversion system, a column inversion system, a dot inversion system, or a z-inversion ( Z-Inversion System).

In addition, an N-frame inversion scheme is also used to improve interlace afterimage.

1 is an exemplary view for explaining a problem occurring in the conventional N-frame inversion scheme.

The N-frame inversion scheme is proposed to improve interlace afterimage, and as shown in FIG. 1, the polarity of the data voltage is changed every two frames.

When the liquid crystal display is driven by the interlace driving method, as shown in FIG. 1, only odd lines are output in the (N-3) frame, only even lines are output in the (N-2) frame, and (N -1) Only odd lines are output in frame, and only even lines are output in (N) frame.

Therefore, data voltages having a negative polarity in odd lines of the (N-3) frame are held in the (N-2) frame and have a positive polarity in the (N-1) frame. As a result, data voltages having different polarities may be output to the odd lines every two frames. Even in the even lines, data voltages having different polarities may be output every two frames.

However, when the panel driven by the interlace driving method is driven by the general driving method, a case in which neighboring input frames are not inverted may occur.

For example, when a still image is output or an image with little image change is output, power consumption can be reduced by using the interlace driving method and the N-frame inversion method as described above, and the degradation of liquid crystal is prevented. can do.

However, when the video is output, the problem of deterioration in image quality occurs when the above-described interlace driving method is used. Therefore, even in the liquid crystal display device using the interlace driving method and the N-frame inversion method as described above, even when the video is output, even-numbered lines and odd lines of one frame during one vertical period are not used. It is driven by the general driving method that outputs all the second lines.

In this case, if the inversion scheme is changed, since the configuration of the liquid crystal display device becomes complicated, the N-frame inversion scheme is generally maintained as it is.

Therefore, when the frames shown in FIG. 1 are output in all frames without distinguishing between even lines and odd lines, a case where inversion is not performed between two neighboring frames may occur.

That is, when the polarity of the data voltage output to the first pixel of the (N-2) frame is (-), the polarity of the data voltage output to the first pixel of the (N-1) frame becomes (+). Because of this, inversion works normally.

However, since the polarity of the data voltage output to the first pixel of frame (N) becomes (+), the polarity of the data voltage output to the first pixel of frame (N-1) and the first of (N) frame The polarities of the data voltages output to the pixels become the same.

That is, when a moving image is input to the liquid crystal display device driven by the interlace driving method and the N-frame inversion method, and the liquid crystal display device is not driven by the interface driving method, inversion is performed between two adjacent frames. If not, a case may occur.

2 is an exemplary view showing various waveform diagrams in a liquid crystal display device driven by a conventional N-frame inversion method. As described above, the waveform of the data voltage Vdata shown in FIG. 2B shows that the liquid crystal display device driven by the interlace drive method and the N-frame inversion method is a general drive rather than an interlace drive method. Driving in the system, the waveform of the data voltage generated when the N-frame inversion system is used as it is.

That is, as illustrated in (A) of FIG. 2, the polarities of the data voltages Vdata between the inverted neighboring frames (N) F and (N + 1) F are based on the common voltage Vcom. Although inverted, the polarities of the data voltages Vdata remain the same between adjacent frames (N-1) F and (N) F without inversion.

Also, as shown in (A) of FIG. 2, the data charging amount of the next frame (N) F among neighboring frames (N-1) F and (N) F without inversion is the previous frame ( It becomes larger than the data charging amount of (N-1) F). Therefore, as shown in (B) of FIG. 2, the luminance level of the next frame (N) F among the neighboring frames (N-1) F and (N) F without inversion is changed to the previous frame ( It becomes significantly higher than the luminance level of (N-1) F).

As described above, in the conventional liquid crystal display device driven by the N-frame inversion method, inversion may not occur between neighboring frames (N-1) F and (N) F. In this case, since the amount of change in luminance between neighboring frames (N-1) F and (N) F increases without inversion, flicker may occur.

That is, the N-frame inversion scheme used to improve the interlace persistence frame inverts a plurality of frames input by the interlace driving scheme. However, for a plurality of frames input by a general driving method other than the interlace driving method, neighboring input frames are not inverted in a predetermined number of frame units.

In this case, in the conventional liquid crystal display device as described above, since the amount of data charging in the next frame among neighboring frames without inversion increases, the luminance level becomes higher than the luminance level of the previous frame. Therefore, flicker may occur due to the change of the luminance level, and the quality of the liquid crystal display may be degraded.

The present invention has been proposed to solve the above-described problem, and by increasing the pulse width of the source output enable signal (SOE), it is possible to reduce the amount of data charging in a later frame of neighboring frames without inversion, It is a technical problem to provide a liquid crystal display device and a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a panel in which pixels are formed at intersections of gate lines and data lines; A gate driver for driving the gate lines; A data driver for converting image data into a data voltage and outputting the data voltage to the data lines; And generating a polarity control signal for driving the panel in an N-frame inversion scheme, transmitting the polarity control signal to the data driver, analyzing the input image data, and reducing the luminance. And a timing controller configured to control the data driver with a second source output enable signal, and to transmit the image data aligned with the panel to the data driver.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the timing controller comprising: generating a polarity control signal for driving a panel in an N-frame inversion method and transmitting the polarity control signal to a data driver; Analyzing, by the timing controller, the input image data to determine whether it is necessary to reduce the brightness; If it is determined that the luminance needs to be reduced, the timing controller controlling the data driver with a second source output enable signal having an increased pulse width; And after the data driver converts the image data transmitted from the timing controller to a data voltage, outputting the data voltage to a data line of the panel using the second source output enable signal.

According to the present invention, by increasing the pulse width of the source output enable signal (SOE) to reduce the amount of data charging in subsequent frames of neighboring frames without inversion, the flicker generated in the N-frame inversion scheme Can be reduced.

That is, according to the present invention, in the N-frame inversion scheme, since the data charging amount of the next frame among neighboring frames can be reduced without inversion, flicker can be reduced.

1 is an exemplary diagram for explaining a problem occurring in the conventional N-frame inversion scheme.
2 is an exemplary view showing various waveform diagrams in a liquid crystal display device driven by a conventional N-frame inversion method.
3 is an exemplary view showing a configuration of a liquid crystal display device according to the present invention.
4 is a flowchart illustrating one embodiment of a method of driving a liquid crystal display device according to the present invention;
5 is a configuration diagram of an embodiment of a timing controller applied to a liquid crystal display according to the present invention.
6 is a configuration diagram of an embodiment of a data driver applied to a liquid crystal display according to the present invention.
7 is a waveform diagram illustrating an example of a relationship between a source output enable signal and a data voltage applied to a liquid crystal display according to the present invention.
8 is an exemplary view for explaining a method of improving luminance by the liquid crystal display according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is an exemplary view showing a configuration of a liquid crystal display according to the present invention.

In the liquid crystal display according to the present invention, a panel 100 having a data line DL and a gate line GL intersected and a thin film transistor (“TFT”) formed at an intersection thereof, A data driver 300 for supplying a data voltage OUTPUT to the data lines DL of the panel 100, and a gate driver for sequentially driving the gate lines GL formed on the panel 100. 200 and a timing controller 400 for controlling the data driver 300 and the gate driver 200.

First, the panel 100 is composed of two glass substrates, and the liquid crystal is injected between the two glass substrates. A pixel (pixel P) is formed at an intersection of the data lines DL and the gate lines GL formed in the panel 100, and TFTs provided in each pixel are applied from the gate driver. In response to the scanning pulse, the data voltage applied from the data driver is supplied to the pixel electrode provided in each pixel.

In particular, the panel 100 applied to the present invention is driven in an N-frame inversion method. That is, as described above with reference to FIG. 1, the pixels of the panel 100 change the polarity of the data voltage every two frames and vice versa.

Next, the timing controller 400 receives a driving voltage from an external system such as a personal computer or a television. The timing controller 400 aligns the input image data of red (R), green (G) and blue (B) transmitted from the external system according to the panel, and then aligns the aligned image data with the data driver 300. To the source drive IC.

The timing controller 400 uses a dot clock Dclk and various control signals SSP, SSC, SOE, REV, POL, GSC, GOE, using a horizontal / vertical synchronization signal (timing signal) input from the external system. GSP, etc.) to control the data driver 300 and the gate driver 200.

The control signals for controlling the data driver 300 among the control signals are called data control signals DCS, and the control signals for controlling the gate driver 200 are referred to as gate control signals GCS.

The dot clock Dclk and the data control signals SSP, SSC, SOE, REV, and POL are supplied to the source drive IC 300, and the gate control signals GSP, GSC, GOE, and the like are provided in the gate driver 200. Is supplied.

In particular, the timing controller 400 applied to the present invention compares the frames to determine whether the input image data currently being input is a moving image, and if the moving image controller is not a moving image, a first source having a first pulse width. The data driver is controlled using an output enable signal (hereinafter, simply referred to as 'first SOE (SOE1)'). In addition, in the case of a video, the next frame among neighboring frames without inversion is used by using a second source output enable signal having a second pulse width (hereinafter, simply referred to as 'second SOE (SOE2)'). The data driver is controlled, and in the remaining frames, the data driver 300 is controlled using the first SOE (SOE1). Here, the second pulse width is formed larger than the first pulse width.

In addition, the timing controller 400 generates a polarity control signal (POL) corresponding to the N-frame inversion driving method to drive the panel 100 in the N-frame inversion method. The data driver 300 transmits the data.

Next, the gate driver 200 may include a shift register that sequentially generates scan pulses in response to a gate start pulse GSP input from the timing controller 400, and a level suitable for driving the liquid crystals of the scan pulses. Level shifter and the like for shifting. The gate driver may be configured of at least one gate drive IC. Hereinafter, the gate drive IC refers to each gate drive IC constituting the gate driver 200.

However, when the gate driver 200 is a gate in panel (GIP) type mounted on the panel 100, the gate driver 200 includes a gate start signal VST and a gate clock generated by the timing controller 400. It may be driven by gate control signals such as (GCLK). At least one gate driver may be provided according to the size and characteristics of the panel 100.

Finally, the data driver 300 supplies the data voltage to the data line of the panel at the falling time of the SOE and cuts off the supply of the data voltage at the rising point of the SOE. The data driver may be configured of at least one source drive IC. Hereinafter, the source drive IC refers to each source drive IC constituting the data driver 300.

In this case, depending on whether the SOE is the first SOE or the second SOE, a difference occurs in the amount of the data voltage charged in the panel, thereby changing the brightness of the image output to the panel.

4 is a flowchart illustrating an embodiment of a method of driving a liquid crystal display device according to the present invention. 5 is a configuration diagram of a timing controller applied to a liquid crystal display according to an exemplary embodiment of the present invention, where (a) shows components constituting the timing controller and (b) shows components shown in (a). In particular, it is an exemplary view showing the configuration of the control signal generator 420. 6 is a configuration diagram of an embodiment of a data driver applied to a liquid crystal display according to the present invention.

First, referring to FIG. 4, in the liquid crystal display driving method according to the present invention, the timing controller 400 generates a polarity control signal for driving the panel in an N-frame inversion scheme and transmits the generated polarity control signal to the data driver. The timing controller 400 analyzes the input image data to determine whether it is necessary to reduce the brightness (S402), and when it is determined that it is necessary to reduce the brightness, the timing controller 400 In operation S404 of controlling the data driver with a second source output enable signal SEO2 having an increased pulse width, when it is determined that it is not necessary to decrease the luminance, the timing controller determines that the timing controller is the first controller. Controlling the data driver by a source output enable signal SEO1 (S406), and the data driver 300 has been transmitted from the timing controller 400; After converting phase data into a data voltage, the data voltage is converted into a data line of the panel 100 using at least one of the first source output enable signal SOE1 or the second source output enable signal. Outputting step (S408).

Among the above processes, the reason why it is necessary to determine whether it is necessary to reduce the brightness (S402) is as follows. This reason has been described in detail in connection with the above prior art, and thus will be briefly described below.

That is, the liquid crystal display device according to the present invention uses the proposed N-frame inversion method to improve the interlaced afterimage, and as described above, the polarity of the data voltage is changed in units of pixels every two frames.

That is, the present invention uses the N-frame inversion method for the interlace driving method, and a still image or an image having a small image change (hereinafter, a still image and an image having a small image change collectively is called a 'still image'). When inputted, it can be operated efficiently. However, when a video or video with a lot of video change (hereinafter, referred to as a video with a lot of video or video change) is input, among neighboring frames without inversion, In subsequent frames, the brightness may increase, resulting in poor image quality.

Therefore, when the video is input, instead of maintaining the N-frame inversion method as it is, instead of reducing the amount of data voltage charged in the panel in the next frame of the adjacent frame without inversion, thereby reducing the brightness of the panel To lower the quality of the picture.

That is, the timing controller 400 determines whether it is necessary to reduce the luminance (S402), and determines whether the input image is a moving image or a still image.

To this end, the timing controller 400 or an external memory stores setting information for distinguishing the moving image from the still image, and the timing controller classifies the moving image using the setting information.

For example, the timing controller 400 may convert the input image into a still image if the change amount of the input image data constituting each frame does not exceed the change amount stored in the setting information on the basis of tens to hundreds of frames. If it is determined that the amount of change exceeds the amount of change, it is determined as a video and a process of reducing luminance may be performed.

Therefore, in the controlling of the data driver 300 with the first and second source output enable signals SOE1 and SOE2 (S404 and S406), the input image data does not constitute a moving image. In the case where the timing controller controls the data driver using a first source output enable signal according to an interlace driving method (S406) and as a result of the determination, the input image data constitutes a video. Controlling, by a timing controller, the data driver by using the second source output enable signal and the first source output enable signal having a pulse width that is greater than a pulse width of the first source output enable signal ( S404).

In particular, the controlling of the data driver using the second source output enable signal and the first source output enable signal (S404) may include: when the input image data constitutes a video, The timing controller 400 controls the data driver with the second source output enable signal in a later frame among the neighboring frames without inversion, and the data driver with the first source output enable signal in the remaining frames. Control 300).

That is, when it is necessary to reduce the luminance, the timing controller 400 controls the data driver 300 using both the first SOE and the second SOE.

In this case, the timing controller 400 may use the first SOE and the second SOE in two ways as follows.

In the first method, when the input image data constitutes a video, the timing controller generates the second source output enable signal SOE2 and the first source output enable signal SOE1. The data driver 300 transmits the data.

That is, the timing controller 300 transmits the second SOE to the data driver 300 together with the polarity control signal POL in a period in which a later frame among neighboring frames without the inversion is output. In the period in which the remaining frames are output, the first SOE is transmitted to the data driver 300 together with the polarity control signal POL.

To this end, as shown in FIG. 5A of the timing controller 300, the receiver 410 for receiving an input image signal, the data control signal DCS and the gate control signal GCS are generated. The control signal generation unit 420 for aligning the input image data, the data aligning unit 430 for outputting the aligned image data, and the image data and the data control signals DCS to the data driver 300. And an output unit 440 for transmitting the gate control signals GCS to the gate driver 200.

In addition, as shown in FIG. 5B, the control signal generator 420 may include a timing signal receiver 421 for receiving various timing signals, and the first SOE according to the video determination result S402. A first SOE generation unit 422 for generating a second SOE, a second SOE generation unit 423 for generating the second SOE according to the video determination result, and outputting the first SOE and the second SOE to the output unit 440. It may be configured to include a SOE output unit 424 to.

In this case, the video determination process (S402) may be performed by the data aligning unit 430. In this case, the data aligning unit 430 generates the second SOE and the first SOE to generate the input image data. The brightness control signal for controlling the brightness of the light source may be transmitted to the timing signal receiving unit 421.

The first SOE generator 422 and the second SOE generator 423 may generate the first SOE and the second SOE according to the luminance control signal and transmit the generated first SOE and the second SOE to the data driver.

However, the video determination process (S402) may be performed by the timing signal receiver 421 of the control signal generator 420.

According to a second method, when the input image data constitutes a moving picture, the timing controller 400 selects the second source output enable signal or the first source output enable signal. A method of transmitting a signal to the data driver.

That is, in the second method, the control signal generator 420 of the timing controller does not directly generate the first SOE and the second SOE and transmit the first SOE and the second SOE to the data driver 300. And generating only a selection control signal for selecting one of the second SOEs and transmitting the selected control signal to the data driver 300.

The data driver 300 receiving the selection control signal generates the first SOE or the second SOE according to the selection control signal, and outputs a data voltage to the panel.

That is, the data driver 300 outputs the data voltage using the second source output enable signal in a later frame among the adjacent frames without inversion according to the selection control signal, and outputs the data voltage in the remaining frames. The data voltage is output using a first source output enable signal.

To this end, as illustrated in FIG. 6, the data driver 300 selects a shift register 310, a latch 320, a digital-to-analog converter (DAC) 330, an output buffer 340, and an SOE. The unit 350 may be configured.

The shift register unit 310 generates a sampling signal using the data control signals SSC, SSP, etc. received from the timing controller 400.

The latch unit 320 latches the image data Data sequentially received from the timing controller 400, and simultaneously outputs the image data to the digital-to-analog converter 330 (DAC).

The digital-to-analog converter 330 simultaneously converts the image data transmitted from the latch unit 320 into a positive or negative data voltage and outputs the same. That is, the digital analog converter 330 converts the image data into a positive or negative analog data voltage (video signal) using the polarity control signal POL transmitted from the timing controller 400. To print.

For example, the digital-to-analog converter (DAC) 330 according to the polarity control signal (POL) signal, the polarity of the data voltages output to the panel in the (N-2) frame and (N-1) frame All the pixels may have different polarities, and in (N−) and (N) frames, polarities of the data voltages output to the panel may have different polarities in all the pixels.

That is, the polarity control signal is to control the data driver 200 so that the pixels of the frames have the polarity as shown in FIG. 1, and the polarity control signal is the N-frame inversion scheme. The control signal generator 420 of the timing controller 400 is generated and transmitted to the data driver 300.

The output buffer 340 stores the positive or negative data voltage transmitted from the digital-to-analog converter 330 according to the rising time and the falling time of the first or second SOE. Output to data lines.

In this case, the first SOE or the second SOE is generated by the control signal generator 420 of the timing controller 400 as in the first method described with reference to FIG. 5 to generate the output buffer 340. As described in the second method, the data driver 300 directly receiving the selection control signal transmitted from the timing controller 400 may directly generate and supply it to the output buffer 340. have.

When the second method is used, the data driver 300 may additionally include an SOE selector 350 as shown in FIG. 6.

That is, the SOE selector 350 generates the first SOE or the second SOE according to the selection control signal and the polarity control signal and supplies them to the output buffer 340.

In the following, with reference to Figures 7 and 8 will be described the basic operating method and effects of the first SOE and the first SOE applied to the present invention.

7 is a waveform diagram illustrating an example of a relationship between a source output enable signal and a data voltage applied to a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 8 is a luminance diagram of the liquid crystal display according to the present invention. It is an illustration for demonstrating a method.

First, referring to FIG. 7, when the first SOE of the first SOE or the second SOE output to the output buffer 340 is raised (x) and polled (y), the output buffer 340 is A data voltage Vdata is output to the data line.

Thereafter, when the second SOE rises (x '), the output buffer 340 blocks the output of the data voltage Vdata.

The data voltage Vdata may be charged to the panel from the time when the first SOE rises (x) to the time when the second SOE rises (x '). That is, the charge amount of the data voltage charged to the panel may vary depending on the charger P from the time when the first SOE rises (x) to when the second SOE rises (x '). Can be.

At this time, the time x when the first SOE rises and the time x 'when the second SOE rises are constantly formed by the horizontal synchronization signal Hsync.

Thus, between the charger (P) from when the first SOE is rising (x) to when the second SOE is rising (x '), the pulse width (Z) of the first SOE and the second SOE Depends on.

That is, as shown in FIG. 7, the pulse width Z of the first SOE is smaller than the pulse width Z ′ of the second SOE. Therefore, the charger P 'of the second SOE is shorter than the charger p of the first SOE.

Therefore, when the data voltage is charged to the panel by the second SOE, the amount of data charging is smaller than when the data voltage is charged to the panel by the first SOE.

The present invention utilizes the features as described above.

That is, as shown in (a) of FIG. 8, in a period in which a later frame (N frame) of neighboring frames (N-1 frame and N frames) is output without inversion, (b) of FIG. 8. As shown in FIG. 2, the data voltage is output to the panel using the second SOE SO2 of which the pulse width Z ′ is increased.

In this case, as described above, the period during which the data voltage is charged in the panel is shortened.

When the amount of charge of the data voltage decreases, the liquid crystal cannot be driven normally, so that the intended brightness of the output voltage does not occur.

Therefore, as shown in (c) of FIG. 8, since the luminance in the subsequent frame (N frame) is reduced, the luminance is output evenly over the entire panel, so that image quality can be improved.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100 panel 200 gate driver
300: source drive IC 400: timing controller
410: receiver 420: control signal generator
430: data alignment unit 440: output unit
421: timing signal receiver 422: first SOE generator
423: second SOE generation unit 424: SOE output unit
310: shift register section 320: latch section
330: digital-to-analog converter (DAC) 340: output buffer
350: SOE selector

Claims

A panel in which pixels are formed at intersections of the gate lines and the data lines;
A gate driver for driving the gate lines;
A data driver for converting image data into a data voltage and outputting the data voltage to the data lines; And
A timing controller which generates a polarity control signal for driving the panel in an N-frame inversion scheme and transmits the polarity control signal to the data driver;
The timing controller,
Determine whether the input image data constitutes a video,
When the input image data does not constitute a video, the data driver controls the data driver by using a first source output enable signal.
When the input image data constitutes a moving picture, the data driver using the first source output enable signal and a second source output enable signal having a pulse width increased from a pulse width of the first source output enable signal. Control the
And a liquid crystal display for transmitting the image data aligned with the panel to the data driver.

The method of claim 1,
The timing controller,
And comparing the change amount of the input image data constituting each frame with the change amount stored in the preset setting information, and determining whether the input image data constitutes a video based on a comparison result.

The method of claim 1,
The timing controller,
When the input image data constitutes a video, the data driver controls the data driver by the second source output enable signal in the next frame among the adjacent frames without inversion, and the first source output enable signal in the remaining frames. And a control unit of the data driver.

The method of claim 1,
The timing controller,
If the input image data does not constitute a video, the data driver controls the data driver to output one of an even line and an odd line for each frame.
And when the input image data constitutes a video, controlling the data driver to output both even lines and odd lines for each frame.

The method of claim 1,
The timing controller,
When the input image data constitutes a video, a selection control signal for selecting the second source output enable signal or the first source output enable signal is transmitted to the data driver.
The data driver,
In response to the selection control signal, the data voltage is output using the second source output enable signal in a later frame among the adjacent frames without inversion, and the first source output enable signal is used in the remaining frames. And the data voltage is output.

Generating, by the timing controller, a polarity control signal for driving the panel in an N-frame inversion scheme and transmitting it to the data driver;
Determining, by the timing controller, whether input image data constitutes a moving image;
Controlling the data driver by using a first source output enable signal when the input image data does not constitute a moving image;
When the input image data constitutes a moving picture, the data driver using the first source output enable signal and a second source output enable signal having a pulse width increased from a pulse width of the first source output enable signal. Controlling; And
And converting the image data transmitted from the timing controller into a data voltage, and then outputting the data voltage to a data line of the panel under control of the timing controller.

The method of claim 6, wherein the timing controller determines whether the input image data constitutes a moving image.
And comparing, by the timing controller, a change amount of the input image data with a change amount stored in pre-stored setting information, and determining whether the input image data constitutes a moving image according to a comparison result.

The method of claim 6,
The controlling of the data driver by using the second source output enable signal and the first source output enable signal may include:
When the input image data constitutes a video, the timing controller controls the data driver with the second source output enable signal in a later frame among the adjacent frames without inversion, and the first source in the remaining frames. And controlling the data driver with an output enable signal.

The method of claim 7, wherein
If the input image data does not constitute a moving image, controlling the data driver to output one of an even line and an odd line for each frame; And
And controlling the data driver to output both even lines and odd lines for each frame when the input image data constitutes a moving image.

The method of claim 7, wherein
The controlling of the data driver by using the second source output enable signal and the first source output enable signal may include:
When the input image data constitutes a video, the timing controller transmits a selection control signal for selecting the second source output enable signal or the first source output enable signal to the data driver.
The outputting of the data voltage may include:
Outputting, by the data driver, the data voltage using the second source output enable signal in a later frame among adjacent frames without inversion, according to the selection control signal; And
And the data driver outputting the data voltage in the remaining frames using the first source output enable signal.