KR20070079103A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to minimize deviation in kick-back voltages which are commonly generated from pixels by varying the timing of a driving signal. An LCD(Liquid Crystal Display) device includes a gate driver(60) and a data driver(50). The gate driver outputs a gate pulse alternately to odd-numbered and even-numbered gate lines every two frame periods, in response to a gate clock signal(GCS) of a timing controller(10). The data driver generates a data pulse which is inversed every two frames, in response to a data clock signal(DCS) of the timing controller. The gate driver includes a first gate driver for driving the odd-numbered gate line and a second gate driver for driving the even-numbered gate line.

Description

Liquid Crystal Display Device And Driving Method Thereof

1 is a block diagram illustrating a liquid crystal display according to a preferred embodiment of the present invention.

2 illustrates a gate driver according to a preferred embodiment of the present invention.

3 is a waveform diagram of a gate pulse and a data pulse according to a preferred embodiment of the present invention.

4 illustrates that the gate driver according to the exemplary embodiment of the present invention is provided on both sides of the liquid crystal panel.

<Description of the symbols for the main parts of the drawings>

10: timing control unit 20: power input unit

30: DC-DC converter 40: gray voltage generator

50: data driver 60: gate driver

70: liquid crystal display panel

The present invention relates to a liquid crystal display and a driving method thereof. More particularly, by changing the timing of a driving signal, all pixels have a kick-back in common, thereby minimizing kick-back variation. The present invention relates to a liquid crystal display device and a driving method thereof capable of improving display quality.

In general, a liquid crystal display (LCD), which is one of flat panel display devices, has advantages such as small size, light weight, and low power consumption compared to cathode ray tube (CRT). It is being used as a TV and the demand for liquid crystal display devices is continuously increasing.

Conventional liquid crystal displays mainly use a dot inversion scheme in which the polarity of the analog gray voltage applied to each pixel electrode is changed to solve the problem of deterioration when an electric field having the same polarity is applied.

In addition, in order to reduce cost and power consumption, a method of driving two pixel electrodes adjacent to each other with one data line has been applied. In this case, however, the number of output terminals of the data driving circuit is reduced by half, whereas the number of output terminals of the gate driving circuit is doubled.

Therefore, since two left and right pixels are driven by one data line, two gate lines are required to drive pixels of one gate line, and the inter-pixel voltage causing coupling due to the time difference between the two gate lines. As a result of this difference, a kick-back voltage deviation occurs, resulting in a fatal problem that the structure is vulnerable to poor vertical streaks due to variations in luminance between pixels.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a liquid crystal display device and a driving method thereof which can improve display quality by minimizing kick-back voltage variation.

In order to achieve the above object, the liquid crystal display according to the present invention sequentially outputs a gate pulse in response to the gate clock signal of the timing controller, but the odd-numbered gate lines GL ₁ , GL ₃ , ... GL _{m − 1)} and the even-numbered gate lines _{(GL 2, GL 4, ...} GL m) gate driver which outputs a gate pulse to the at least two-frame period output order are mutually alternated and; And a data driver for outputting data pulses inverted in at least two frame units in response to the data clock signal of the timing controller.

The gate driver outputs a gate pulse by changing the odd-numbered gate line from 1 frame to 1 frame + 1/2 H period → 1 frame → 1 frame − 1/2 H period, and the even-numbered gate line is 1 frame → 1 frame. The gate pulse is output by changing the 1 / 2H period → 1 frame → 1 frame + 1 / 2H period period.

The gate driver may include a first gate driver for driving odd-numbered gate lines and a second gate driver for driving even-numbered gate lines.

Meanwhile, in the liquid crystal display driving method according to the present invention, the gate driver sequentially outputs the gate pulse in response to the gate clock signal, and is even with the odd _- numbered gate lines GL ₁ , GL ₃ , ... GL _m-1 . Outputting gate pulses in which the second gate lines (GL ₂ , GL ₄ ,... GL _m ) alternate in output order in at least two frame periods; And a data driver outputting a data pulse inverted at least every two frames in response to the data clock signal.

Here, in the outputting of the gate-on pulse, the odd-numbered gate line is changed into a period of 1 frame → 1 frame + 1 / 2H period → 1 frame → 1 frame-1 / 2H period to output the gate pulse and the even-numbered gate line is The gate pulse is output by changing from 1 frame to 1 frame-1 / 2H period to 1 frame → 1 frame + 1 / 2H period.

The outputting of the gate pulse may include a first gate driver driving an odd-numbered gate line and a second gate driver driving an even-numbered gate line.

Hereinafter, the specific configuration and operation of the present invention will be described in detail with reference to embodiments and drawings.

1 is a block diagram illustrating a liquid crystal display according to a preferred embodiment of the present invention.

In the liquid crystal display device 1 shown in FIG. 1, each of the liquid crystal cells arranged in a matrix form displays an image by adjusting light transmittance according to an image signal. The liquid crystal display device 1 includes a liquid crystal display panel 70 for displaying an image and a driving circuit unit for driving the liquid crystal display panel 70.

The liquid crystal display panel 70 includes a liquid crystal cell Clc formed at each pixel area divided by an intersection of the gate line GL and the data line DL, and the gate line GL, the data line DL, and the liquid crystal cell Clc. A thin film transistor (TFT) connected therebetween is provided. The thin film transistor TFT supplies the data signal of the data line DL to the liquid crystal cell Clc in response to the scan signal of the gate line GL. The liquid crystal cell Clc charges the pixel voltage, which is the difference between the supplied data signal and the common voltage Vcom, and drives the liquid crystal according to the charged pixel voltage to adjust the light transmittance. In this case, in order to maintain the pixel voltage charged in the liquid crystal cell Clc in a stable manner, a storage capacitor Cst connected in parallel with the liquid crystal cell Clc is further provided.

The driving circuit unit includes a gate driver 60 for driving a gate line, a data driver 50 for driving a data line, a power input unit 20 for receiving a driving voltage VDD from a power output unit (not shown) of the system, and an analog device. The gate on / off voltage (Von / Voff) is supplied to the gray voltage generator 40 and the gate driver 60 to generate the gray voltage and supply the gray voltage to the data driver 60, and then analog drive the gray voltage generator 40. And a DC-DC converter 30 for supplying the voltage AVDD, and a timing controller 10 for controlling the gate driver 60 and the data driver 50.

The power input unit 20 receives the driving voltage VDD from the power output unit of the system, outputs the timing driving voltage TVDD to the timing controller 10, and supplies the power driving voltage PVDD to the DC-DC converter 30. Outputs

The DC-DC converter 30 generates a gate on / off voltage (Von / Voff) and an analog driving voltage (AVDD) by boosting or reducing the power driving voltage PVDD from the power input unit 20 to generate a gate driver. 60 to the gray voltage generator 50, respectively. In addition, the DC-DC converter 30 also generates a common voltage Vcom which is a reference of the data voltage difference in the thin film transistor, and the generated common voltage Vcom is supplied to the common electrode of the pixel.

The timing controller 10 receives an input control signal for controlling digital data R, G, and B and its display from an external system. The input control signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, a data enable signal DE, and the like. At this time, any one of Low Voltage Differential Signaling (LVDS), Transition Minimized Differential Signaling (TMDS), and CMOS / TTL is used as the interface method.

The timing controller 10 generates a gate control signal GCS for controlling the operation of the gate driver 60 by using input control signals, supplies the gate control signal GCS to the gate driver 60, and controls the operation of the data driver 50. The data control signal DCS is generated and supplied to the data driver 50.

The gate driver 60 transmits the gate-on voltage Von output from the DC-DC converter 30 to the gate lines of the liquid crystal panel 70 in response to the gate control signal GCS from the timing controller 10. The power is sequentially supplied, and the gate-off voltage Voff is supplied in the remaining period. The gate control signal GCS includes a gate clock signal CPV for controlling the output timing of the gate pulse, a gate start pulse STV, an output enable signal OE for limiting the width of the gate pulse, and the like.

Here, the gate driver 60 outputs a gate pulse for sequentially applying to the gate line in response to the gate start pulse STV, but the odd-numbered gate lines GL ₁ , GL ₃ , ... GL _{m -1} ) The gate pulses are output so that the output order of the and even gate lines GL ₂ , GL ₄ , ... GL _m is alternated by at least two frames. A specific driving method will be described in detail below.

The data driver 50 receives the digital image signals R, G, and B from the timing controller 10 in response to the data control signal DCS from the timing controller 10. In addition, the data driver 50 selects the analog gray voltage corresponding to the digital data R, G, and B among the analog gray voltages from the gray voltage generator 40 as an analog data, thereby selecting the data line of the liquid crystal panel 70. To supply.

Here, the data control signal DCS is a data start pulse STH for instructing to start input of the digital video signals R, G, and B, and a load signal TP for instructing the output of an analog data signal of the data driver 50. ), The inversion signal RVS and the data clock signal DCLK for inverting the polarity of the analog gradation voltage with respect to the common voltage Vcom.

2 illustrates a gate driver according to a preferred embodiment of the present invention,

3 is a waveform diagram of a gate pulse and a data pulse according to a preferred embodiment of the present invention.

2 and 3, the gate driver 60 outputs a gate pulse for sequentially applying to the gate line in response to the gate start pulse STV provided from the timing controller 10. After a gate pulse is applied to one gate line GL _N , a carry signal is generated to sequentially activate the gate line so that the next gate line GL _{N +1} is activated.

In this case, the secondary kick-back voltage generated at a specific pixel cannot be excluded due to the characteristics of the source IC reduction structure. In addition, when the gate pulse is sequentially applied to the gate line, only the pixels of one line generate the secondary kick-back voltage and the pixels of the other line do not generate the secondary kick-back voltage. Accordingly, a luminance difference is generated between the pixel where the secondary kick-back voltage is generated and the pixel line where the secondary kick-back voltage is not generated, thereby being recognized as a vertical line unevenness.

More specifically, in the data driver reduction structure, two gates are required at the upper and lower sides to drive one gate horizontal line, and the upper gate corresponds to the odd-numbered gate lines GL ₁ , GL ₃ , ... GL _{m −. 1} ), and the lower gate corresponds to even-numbered gate lines GL ₂ , GL ₄ , ... GL _m . Here, the voltage difference occurs due to the gate pulse difference between the upper and lower portions, and the kick-back deviation occurs due to the coupling resulting from the odd gate line corresponding to the upper gate, because the gate pulse is always output before the even gate line. Secondary kick-back voltage always occurs, and on the contrary, even-numbered gate lines do not always generate secondary kick-back voltage because the gate pulse is always output later than the odd gate line. Here, a luminance difference is generated along the data line between the pixel generating the secondary kick-back voltage and the pixel not generating the secondary kick-back voltage, resulting in poor vertical streaks.

Therefore, the kick pulse may be eliminated only by changing the gate pulse such that all pixels alternately generate a secondary kick-back voltage.

To this end, in the liquid crystal display according to the present invention, the gate driver 60 sequentially outputs the gate pulses from the first gate line by the timing controller 10, and the odd-numbered gate lines and the even-numbered gate lines are at least two frame periods long. Outputs gate pulses that alternate in output order.

Here, it is apparent that the period in which the output order of the odd-numbered gate lines and even-numbered gate lines alternate with each other can be adjusted to two or more frames by timing control.

In addition, the data driver 60 outputs a data pulse inverted by at least two frames in response to the data clock signal of the timing controller.

Here, the period in which the data pulse is inverted may be two or more frames, and the output pulses of the odd-numbered gate lines and the even-numbered gate lines of the gate pulse are determined according to the alternating periods.

Referring to FIG. 3 as a specific embodiment, gate pulses are sequentially applied to each gate line for each frame, but odd-numbered gate lines GL ₁ , GL ₃ , ... GL _{m −1} are one frame to one frame. The gate pulse is applied by changing the period from 1 / 2H period → 1 frame → 1frame-1 / 2H period, and even-numbered gate lines (GL ₂ , GL ₄ , ... GL _m ) are 1 frame → 1 frame-1 The gate driving unit may be operated by the timing controller 10 to change the output order of the odd gate lines and the even gate lines in units of two frames by changing the periods of the periods of / 2H → 1 frame → 1 frame + 1 / 2H. The gate pulse of 60 can be adjusted.

Since the period of the gate pulse of the gate line is changed in units of two frames as described above, the data driver 60 must adjust the inversion signal RVS to increase the period in which the data pulse is also inverted from one frame to two frames. However, even if the inversion period is increased to 2 frames, the existing 1 × 1 inversion scheme can be maintained.

By the data and gate pulse driving as described above, all the pixels undergo the second kick-back voltage in units of two frames, thereby minimizing the kick-back voltage deviation.

In other words, the odd-numbered gate lines (GL ₁ , GL ₃ , ... GL _{m -1} ) are output before the even-numbered gate lines (GL ₂ , GL ₄ , ... GL _m ) until the first two frames. A secondary kick-back voltage occurs, but outputs later than the even-numbered gate lines during the next two frames, so that no secondary kick-back voltage occurs. On the other hand, even-numbered gate lines (GL ₂ , GL ₄ , ... GL _m ) are output second until the first two frames are later than odd-numbered gate lines (GL ₁ , GL ₃ , ... GL _{m -1} ). Kick-back does not occur, but during the next two frames it is output before the odd-numbered gate lines, resulting in a second kick-back voltage.

Eventually, the even-numbered and odd-numbered gates alternate in two-frame increments, causing secondary kick-back voltage and alternating without the secondary kick-back voltage, thereby dithering at the pixel itself to kick-back. Voltage deviation can be minimized, which can improve display quality by preventing chronic vertical defects.

4 illustrates that the gate driver according to the exemplary embodiment of the present invention is provided on both sides of the liquid crystal panel.

Referring to FIG. 4, the gate driver 60 may be configured to include a first gate driver 61 and a second gate driver 62 on both sides of the liquid crystal panel 70, and the first gate driver 61. Supplies gate pulses to the odd-numbered gate lines GL ₁ , GL ₃ ,... GL _{m -1} , and the second gate driver 62 supplies the even-numbered gate lines GL ₂ , GL ₄ ,... Supply a gate pulse to .GL _m ).

Accordingly, by adjusting the control signal applied from the timing controller 10, the first gate driver 61 controls one frame to one frame + with respect to the odd-numbered gate lines GL ₁ , GL ₃ , ... GL _{m −1} . The gate pulse is applied by changing the period of 1 / 2H → 1 frame → 1 frame-1 / 2H period, and the second gate driver 61 performs an even-numbered gate line GL ₂ , GL ₄ , ... GL _m . 1 frame → 1 frame-1 / 2H line → 1 frame → 1 frame + 1 / 2H line and apply gate pulse to alternating the output order of odd and even gate lines in units of 2 frames. This eliminates kick-back voltage variations.

As described above, the liquid crystal display and the driving method thereof according to the present invention change the timing of the driving signal so that all pixels have a kick-back voltage in common, thereby reducing the kick-back voltage deviation. An excellent effect that can be minimized to improve display quality occurs.

Although the detailed description of the present invention described above has been described with reference to the preferred embodiment of the present invention, the protection scope of the present invention is not limited to the above embodiment, and those skilled in the art will appreciate It will be understood that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A gate driver which sequentially outputs gate pulses in response to a gate clock signal of the timing controller, and outputs gate pulses in which the odd-numbered gate lines and the even-numbered gate lines alternate output sequences in two frame periods; And a data driver for outputting data pulses inverted in units of two frames in response to the data clock signal of the timing controller. The gate driver of claim 1, wherein the gate driver changes the odd-numbered gate line to a period of 1 frame → 1 frame + 1 / 2H period → 1 frame → 1 frame-1 / 2H period, and outputs a gate pulse.  And the even-numbered gate line is changed from one frame to one frame to 1/2 H period to one frame to one frame + 1/2 H period to output gate pulses. The liquid crystal display of claim 1 or 2, wherein the gate driver comprises a first gate driver for driving an odd gate line and a second gate driver for driving an even gate line. Outputting gate pulses sequentially by the gate driver in response to the gate clock signal, wherein the odd-numbered gate lines and the even-numbered gate lines alternate output pulses in at least two frame periods; And a data driver outputting a data pulse inverted at least every two frames in response to a data clock signal. The method of claim 4, wherein the outputting of the gate pulses comprises changing the odd-numbered gate lines from 1 frame to 1 frame + 1/2 H period to 1 frame → 1 frame − 1/2 H period. And the even-numbered gate line is changed in a period of 1 frame-1 frame-1 / 2H period-1 frame-1 frame + 1 / 2H period to output a gate pulse. The liquid crystal display of claim 4 or 5, wherein the outputting of the gate pulse comprises: driving the odd-numbered gate line by the first gate driver and driving the even-numbered gate line by the second gate driver; Driving method.

Images