KR102480834B1 - Display Device Being Capable Of Driving In Low-Speed - Google Patents

Abstract

A display device capable of low-speed driving according to the present invention includes a display panel, a timing controller, and a data driver. A table panel has a plurality of pixels arranged in a horizontal line, and data lines and gate lines connected to the pixels are arranged. The timing controller varies the frame frequency according to the mode change control signal, and divides one frame into a first subframe and a second subframe when driving with a lower frame frequency than normal driving. The data driver outputs data voltages of the first sub-frame to odd-numbered pixel lines during the first field and outputs data voltages of the second sub-frame to even-numbered pixel lines during the second field. The timing controller determines that the data voltage provided to the (2i-1) (i is a natural number) pixel line in the first field ends within the 2i horizontal period, and the data voltage provided to the 2i pixel line in the second field. A timing control signal is output so as to end within the (2i+1)th horizontal period.

Description

Display device capable of driving at low speed {Display Device Being Capable Of Driving In Low-Speed}

The present invention relates to a display device capable of low-speed driving.

Display devices are used in various displays such as portable information devices, office devices, computers, and televisions.

Several methods are known for reducing power consumption in a display device, and one of them is a low-speed driving technology. The low-speed drive technology changes the frame frequency (i.e., drive frequency) according to the amount of data change, and displays the screen of the display device with a frame frequency slower than the input frame frequency (normal frame frequency, for example, 60Hz) in a still image without data change. Refresh. On the other hand, in a video with data change, the screen of the display device is refreshed in a normal driving method according to the input frame frequency. The display device may change the frame frequency according to a panel self refresh (PSR) control signal input from the system. For example, the display device reduces the frame frequency at a slower rate than 60 Hz when the PSR control signal is input at an on level corresponding to a still image, and maintains the frame frequency at 60 Hz when the PSR control signal is input at an off level in response to a moving image. can

The low-speed driving technology may be implemented through interlace driving. In the interlace low-speed driving method, one frame is time-divided into a plurality of sub-frames, and gate lines driven in each sub-frame are interlaced. In interlace driving, as the number of subframes increases, one frame period increases and the frame frequency decreases accordingly. As the frame frequency gradually decreases from 60 Hz for low-speed driving, the data transition frequency used to supply the data voltage in the data driver decreases, thereby reducing power consumption.

However, when low-speed driving is performed in an interlace method, a problem in that image quality is deteriorated due to a gate pulse delay phenomenon occurs. This is because the data voltage charged in the pixel is discharged to the data line when the gate pulse is not completely discharged and the gate voltage maintains a high voltage even after the gate pulse is delayed and the charging period of the data voltage is completed.

When the data voltage charged in the pixel is discharged due to the delay of the gate pulse as described above, the pixel is eventually charged in a state in which the data voltage is insufficient, so that a desired gray level cannot be expressed.

Accordingly, an object of the present invention is to provide a display device capable of being driven at a low speed by changing a frame frequency, in order to improve image quality defects caused by insufficient charging of a data voltage due to delay of a gate pulse.

A display device capable of low-speed driving according to the present invention includes a display panel, a timing controller, and a data driver. A table panel has a plurality of pixels arranged in a horizontal line, and data lines and gate lines connected to the pixels are arranged. The timing controller varies the frame frequency according to the mode change control signal, and divides one frame into a first subframe and a second subframe when driving with a lower frame frequency than normal driving. The data driver outputs data voltages of the first sub-frame to odd-numbered pixel lines during the first field and outputs data voltages of the second sub-frame to even-numbered pixel lines during the second field. The timing controller determines that the data voltage provided to the (2i-1) (i is a natural number) pixel line in the first field ends within the 2i horizontal period, and the data voltage provided to the 2i pixel line in the second field. A timing control signal is output so as to end within the (2i+1)th horizontal period.

Since the present invention extends the output period of the data voltage in the interlace mode driving state, even if the gate pulse is delayed, the gate pulse is completely discharged before the end of the data voltage output period. As a result, it is possible to prevent the data voltage charged in the pixel from being discharged, thereby reducing the occurrence of image quality defects.

1 is a view showing a display device according to the present invention;
2 is a diagram showing a pixel structure according to an embodiment of the present invention;
3 is a view showing an embodiment of a display panel according to the present invention.
FIG. 4 is a diagram illustrating stages of the first shift register shown in FIG. 3;
5 is a view showing a driving method according to the present invention.
6 is a diagram showing timing of gate pulses in an interlace mode according to the present invention;
7 is a diagram showing data voltage output timing in an interlace mode according to the present invention;
8 and 9 are diagrams showing timing of gate pulses according to comparative examples.
10 is a diagram explaining the principle of compensating for the gate pulse delay phenomenon according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings, focusing on the liquid crystal display device. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. The names of the components used in the following description are selected in consideration of the ease of writing the specification, and may differ from the names of actual products.

1 is a block diagram showing a display device capable of low-speed driving according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram illustrating a pixel structure according to an exemplary embodiment of the present invention. Although the following embodiments are described centering on the liquid crystal display, it should be noted that the display device of the present invention is not limited to the liquid crystal display. For example, an embodiment of the present invention is a field emission display (FED), a plasma display panel (PDP), an organic light emitting display (OLED), an electrophoretic display ( Electrophoresis, EPD) may be implemented as a flat panel display device.

Referring to FIGS. 1 and 2 , the display device according to the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , and gate drivers 131 , 132 , 141 , and 142 . The gate drivers 131 , 132 , 141 , and 142 may include first and second level shifters 131 and 132 and first and second shift registers 141 and 142 .

The display panel 100 includes a liquid crystal layer formed between two glass substrates. The display panel 100 includes a display area 100A and a non-display area 100B. A pixel array is disposed in the display area 100A, and first and second shift registers 141 and 142 are disposed in the non-display area 100B.

The pixel array includes liquid crystal cells (Clc, pixels) formed at intersections of data lines DL and gate lines GL, TFTs connected to the pixel electrodes 1 of the pixels, and pixels opposite to the pixel electrodes 1. A common electrode 2 and storage capacitors Cst are included. Each of the liquid crystal cells Clc is connected to a thin film transistor (TFT) and driven by an electric field between the pixel electrode 1 and the common electrode 2 . A black matrix, red (R), green (G), and blue (B) color filters, etc. are formed on the upper glass substrate of the display panel 100 . A polarizer is attached to each of the upper glass substrate and the lower glass substrate of the display panel 100, and an alignment layer for setting a pre-tilt angle of liquid crystal is formed. The common electrode 2 is formed on the upper glass substrate in vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and in IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. It is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving method.

The timing controller 110 receives digital video data (RGB) of an input image from a host system (not shown) through a low voltage differential signaling (LVDS) interface method, and converts the digital video data (RGB) of the input image into mini- It is supplied to the data driver 120 through the LVDS interface method. The timing controller 110 aligns the digital video data (RGB) input from the host system according to the arrangement of the pixel array and supplies the data to the data driver 120 .

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (CLK) from a host system, and the data driver 120 ) and control signals for controlling the operation timing of the gate driver 130 are generated. The control signals include a gate timing control signal for controlling the operation timing of the gate driver 131 , 132 , 141 , and 142 and a source timing control signal for controlling the operation timing of the data driver 120 .

The gate timing control signal includes first and second start pulses VST1 and VST2, odd gate clocks CLK1, CLK3, CLK5... and even gate clocks CLK2, CLK4, CLK6.... The first start pulse VST1 is provided to the first shift register 141 to determine the output timing of the first gate pulse G1. The second start pulse VST2 is provided to the second shift register 142 to determine the output timing of the second gate pulse G2 in the interlace mode.

The source timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). include The source start pulse SSP controls data sampling start timing of the data driver 120 . The source sampling clock SSC is a clock signal that controls data sampling timing in the data driver 120 based on a rising or falling edge. The polarity control signal POL controls the polarity of data voltages sequentially output from each output channel of the source driver 12 . The source output enable signal SOE controls output timing of the data driver 120 .

The timing controller 110 receives a mode change control signal from the host system, and changes the frame frequency for controlling the operation of the data driver 120 and the gate driver 131, 132, 141, 142 according to the mode change control signal to display the display panel ( 100) can be operated in a normal driving mode or an interlace full speed driving mode. Frame frequency is defined as the number of frames displayed in one second. The mode change control signal may be selected as a panel self refresh (PSR) control signal. The host system can determine whether an input image is a still image or a moving image by using various known image determination means. The host system may generate the PSR control signal at an on level when a still image is input, and generate a PSR control signal at an off level when a moving image is input.

The timing controller 110 controls the operation of the data driver 120 and the gate driver 131 , 132 , 141 , and 142 in a normal driving mode in which the frame frequency is a reference value according to the off-level PSR control signal. In the following embodiments, the reference value is described as 60 Hz, but the technical spirit of the present invention is not limited thereto. The reference value may vary according to the model, resolution, etc. of the display panel, but for convenience of description, 60 Hz is taken as an example. In the normal driving mode, a source timing control signal and a gate timing control signal are generated according to a frame frequency of 60Hz.

The timing controller 110 controls the operation of the data driving unit 120 and the gate driving units 131, 132, 141, and 142 in an interlace low-speed driving mode in which the frame frequency is less than (or slower than) 60 Hz according to the on-level PSR control signal. In the interlace low-speed driving mode, the source timing control signal and the gate timing control signal are generated according to a frame frequency of 60 Hz/n (n is a positive integer greater than or equal to 2).

In particular, the timing controller 110 controls the timing of the source timing control signal to extend the output period of the data voltage in preparation for the normal driving mode. The source timing control signal in the low-speed driving mode will be described later.

The data driver 120 latches the digital video data (RGB) according to the source timing control signal, converts the latched data into an analog positive/negative polarity gamma compensation voltage, and generates data voltages whose polarities are reversed at predetermined cycles. It is supplied to the data lines DL. The data driver 120 includes an output circuit for outputting a data voltage, and the output circuit includes a plurality of buffer units. The buffer units are connected to the output channels, and each of the output channels is connected to the data lines DL on a one-to-one basis.

The gate drivers 131 , 132 , 141 , and 142 include first and second level shifters 131 and 132 and first and second shift registers 141 and 142 .

The first level shifter 131 level-shifts the odd clock signals CLK[2i-1] and the first start pulse VST1 under the control of the timing controller 110 and then supplies them to the first shift register 141. do. The second level shifter 132 level-shifts the even clock signals CLK[2i] and the second start pulse VST2 under the control of the timing controller 110 and supplies them to the second shift register 142 .

3 is a diagram showing first and second shift registers 141 and 142 according to an embodiment of the present invention, and FIG. 4 is a diagram showing one stage in the first shift register.

1, 3, and 4, the first and second shift registers 141 and 142 are formed by a combination of a plurality of thin film transistors (hereinafter referred to as TFTs) in the non-display area 100B of the display panel 100 by the GIP method. is formed The first shift register 141 shifts and outputs an odd gate pulse corresponding to the odd gate clock (CLK[2i-1]) and the first start pulse (VST1) provided from the first level shifter 131, and outputs the odd number stage. consists of Figure 3 shows the three jockey stages located at the top.

The (2i-1)th (i is a natural number) odd stage (GIP L[2i-1]) includes a pull-up transistor (Tpu), a pull-down transistor (Tpd) and a node control circuit ( NCON).

The pull-up transistor Tpu outputs the gate high voltage VGH of the [2i-1] odd-numbered gate clock CLK[2i-1] according to the Q node voltage. The pull-down transistor Tpd discharges the output voltage to the low potential voltage VSS according to the QB node voltage.

The node control circuit NCON includes a node control circuit NCON that controls the Q node and the QB node. The node control circuit NCON controls the gate voltage of the pull-up transistor Tpu by charging the Q node with the output voltage of the first start pulse VST1. In addition, the node control circuit NCON receives the downstream signal NEXT and charges the QB node to control the gate voltage of the pull-down transistor Tpd.

The second shift register 142 includes even stages that shift and output even gate pulses in response to the even gate clock CLK and the second start pulse VST2 provided from the second level shifter 132 . Figure 3 shows three excellent stages located at the top. The even stage may have the same circuit configuration as that of the odd stage shown in FIG. 4 , and an even gate clock may be input to a pull-up transistor of the even stage.

5 is a diagram illustrating operations of a timing controller in normal driving and interlace driving.

Referring to FIGS. 4 and 5 , the timing controller 110 operates in normal driving mode when the PSR control signal is at an off level. As a result, the timing controller 110 controls the gate timing control signal so that the first to 2m gate pulses G1 to G2m are sequentially output.

Since the first polling control transistor T1 is turned on during the output period of the third gate pulse G3, at the start of the third horizontal period H3, the first gate line G1 is in the first stage. (GIP L1) and the second stage (GIP R2) are connected in a double feeding method. Since the amount of change in voltage passing through the drain-source electrode of the first polling control transistor T1 is proportional to the gate-source potential, at the time when the third gate pulse G3 starts to be input, the first gate pulse G1 Discharge faster. That is, the first polling control transistor T1 can shorten the polling time of the first gate pulse G1 at the start of the third horizontal period H3. As such, the polling control transistors T1, T2, T3, T4, T5, T6... can shorten the polling time of the gate pulse.

When the PSR control signal is at an on level, the timing controller 110 controls the source timing control signal and the gate timing control signal to operate in interlacing driving.

To operate with 30Hz interlace driving, the timing controller 110 divides one frame of input image data into first and second subframes. The first sub-frame includes input image data of odd-numbered pixel lines HL1, HL3...HL[2m-1], and the second sub-frame includes even-numbered pixel lines HL2, HL4...HL [2m]) of the input image data.

In FIG. 6 , the ith horizontal period Hi is defined as a period in which the data voltage is supplied to the ith pixel line HLi. For example, the first horizontal period H1 is a period in which the data voltage is supplied to the first pixel line HL1, and the 2m horizontal period H2m is a period in which the data voltage is supplied to the 2m pixel line HL2m. The first to 2m gate pulses G1 to G2m are each set to a pulse width of 3 horizontal periods to perform overlap driving.

The timing controller 110 transmits the first start pulse VST1 and the odd gate clocks CLK1, CLK3, CLK5... to the first level shifter 131 during the first field period. Also, the timing controller 110 transmits the second start pulse VST2 and even gate clocks CLK2, CLK4, CLK6... to the second level shifter 132 during the second field period.

As a result, as shown in FIG. 6, odd-numbered pixel lines (HL1, HL3...HL[2m-1]) are sequentially scanned during the first field (1 field) period, and the image data of the first subframe is written. do. During the first field (1 field), the even-th pixel lines (HL2, HL4...HL[2m]) maintain the previously written data voltage.

And, during the second field (2field), even-th pixel lines (HL2, HL4...HL[2m]) are sequentially scanned to write the image data of the second subframe. During the second field 2, odd-numbered pixel lines HL1, HL3...HL[2m-1] maintain the data voltages written during the first field 1.

In particular, the timing controller 110 extends the data voltage charging period in an interlace driving state. That is, as shown in FIG. 7 , the data voltage charging period in the interlace driving state may be a period of 1H to 2H. For example, since the first data voltage Data1 is polled within the second horizontal period H2, the output period of the first data voltage Data1 is between the first horizontal period H1 and the second horizontal period H2. Including some sections Similarly, the output period of the second data voltage Data2 includes a partial period of the second horizontal period H2 and the third horizontal period H3.

In order to control the data voltage output period, the timing controller 110 may control output timings of the source output enable signal (Source Output Enable, SOE) and the data enable signal (Data Enalbe, DE).

As described above, in the interlace driving operation, since the data voltage charging period is extended, the problem of deterioration in image quality due to gate pulse delay can be improved. This is explained as follows.

If the polling time of the gate pulse and the polling time of the data voltage are set to be the same as in FIG. 8, even after the charging timing of the data voltage (Data) ends as shown in FIG. The gate electrode of the TFT shown in Fig. 2 maintains a high potential. As a result, since the data voltage charged in the pixel is discharged to the data line DL, a desired data voltage cannot be charged in the pixel. That is, since the pixels are charged with a data voltage lower than the data voltage to be actually written, a quality defect occurs.

In normal mode operation, the polling timing of the gate pulses (G1, G2, G3, G4, G5, G6...) is shortened due to the operation of the polling control transistors (T1, T2, T3, T4, T5, T6...). The delay phenomenon of pulses (G1, G2, G3, G4, G5, G6...) has been improved.

On the other hand, in the interlace mode, odd gate pulses (G1, G3, G5...) are output during the first field (1 field) and even gate pulses (G2, G4, G6...) are output during the second field (2 field). Since it is output, the polling control transistors T1, T2, T3, T4, T5, and T6 do not operate.

Since the present invention extends the output period of the data voltage Data to 1H or more as shown in FIG. 7 in the interlace mode, even if the gate pulse is delayed, the gate pulse ( G1, G2, G3, G4, G5, G6...) can be discharged to the turn-off voltage level. As a result, the gate pulses (G1, G2, G3, G4, G5, G6...) maintain the turn-on voltage after the output period of the data voltage (Data) to prevent the data voltage charged in the pixel from being discharged. Therefore, deterioration of image quality due to poor charging of the data voltage can be improved.

Through the above description, those skilled in the art will know that various changes and modifications are possible within the scope without departing from the technical spirit of the present invention. Therefore, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

100: display panel 110: timing controller
120: data driver 130: gate driver
DL: data lines GL: gate lines

Claims (7)

a display panel having a plurality of pixels arranged in a horizontal line, and a data line and a gate line connected to the pixels;
a timing controller for varying a frame frequency according to a mode switching control signal and dividing one frame into a first subframe and a second subframe when driving at a lower frame frequency than normal driving; and
a data driver outputting data voltages of the first sub-frame to odd-numbered pixel lines during a first field and outputting data voltages of the second sub-frame to even-numbered pixel lines during a second field;
The timing controller
The data voltage supplied to the (2i-1) (i is a natural number) pixel line within the first field ends within the 2i horizontal period, and the data voltage supplied to the 2i pixel line within the second field A display device capable of low-speed driving that outputs a timing control signal to end within a (2i+1)th horizontal period. According to claim 1,
The data voltage is a display device capable of low-speed driving that is output within a section greater than one horizontal period and less than two horizontal periods. According to claim 1,
A display device capable of low-speed driving in which an output timing of the data voltage provided to the i-th pixel line is synchronized with a start timing of an i-th horizontal period. According to claim 1,
The display panel
a first shift register providing gate pulses to odd-numbered gate lines during the first field; and
A second shift register providing a gate pulse to an even gate line during the second field;
A display device capable of low-speed driving, wherein a gate pulse supplied to the ith pixel line has a pulse width of three horizontal periods and ends at the ith horizontal period. According to claim 4,
The output period of the data voltage provided to the ith pixel line ends after the ith gate pulse is inverted to a turn-off voltage. According to claim 4,
The shift register is
an i-th stage outputting an i-th gate pulse supplied to an i-th gate line; and
An i-th polling control transistor comprising a first electrode connected to the i-th stage, a second electrode connected to a low potential voltage input terminal, and a gate electrode connected to the (i+2)th stage;
In the case of the normal driving mode, the gate electrode of the i-th polling control transistor is raised by the (i+2)th gate pulse provided at the start of the (i+2)th horizontal period, so that the first electrode and the second A display device capable of low-speed driving that shortens the voltage discharge period between electrodes. According to claim 6,
The first and second shift registers are disposed on both sides of the display area of the display panel, respectively;
The (2i-1)th polling control transistor is included in the second shift register,
The 2i polling control transistor is a display device capable of low-speed driving included in the first shift register.

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